############################################################################################
#
#                            CMX Net-to-Resource File for the
#              Topo Function FPGA IO signals used for the connections to the Debug Connector
#             -=============------------------------------------------======================
#
#
#     Original Rev. 28-Mar-2012
#              Rev. 03-Apr-2013 find location for these 10x signals without interfering with backplane inputs
#  Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector
#
#  Signal Nets referenced in this file:
#  ------------------------------------
#
#   TP_DEBUG_n            (n=0:9)  10x spare connections from the BF FPGA to debug connector J14
#
############################################################################################


# 10x signals are going to the Debug Connector on layer 6

NET  'TP_DEBUG_0'                      U2-<IO_L19N_26>           #> F06 #> T06        F42
NET  'TP_DEBUG_1'                      U2-<IO_L15N_26>           #> F06 #> T06        D41
NET  'TP_DEBUG_2'                      U2-<IO_L16N_26>           #> F06 #> T06        F41
NET  'TP_DEBUG_3'                      U2-<IO_L15P_26>           #> F06 #> T06        D42
NET  'TP_DEBUG_4'                      U2-<IO_L19P_26>           #> F06 #> T06        E42
NET  'TP_DEBUG_5'                      U2-<IO_L17N_26>           #> F06 #> T06        E40
NET  'TP_DEBUG_6'                      U2-<IO_L18P_26>           #> F06 #> T06        G41
NET  'TP_DEBUG_7'                      U2-<IO_L13N_26>           #> F06 #> T06        C41
NET  'TP_DEBUG_8'                      U2-<IO_L18N_26>           #> F06 #> T06        G42
NET  'TP_DEBUG_9'                      U2-<IO_L11N_SRCC_26>      #> F06 #> T06        B42