------------------------------------------------------------------------------- -- Design : VME/ACE/TTC interface (& CANbus?) -- Author : Yuri ERMOLINE -- Created : 01.11.2011 - start schematics Last Modified: 01.05.2014 : 26.03.2012 - start PCB layout : 06.04.2012 - merged 2 design (6u VME test card and VAT card) : 01.06.2012 - PCB manufacturing request to Pascal : 05.06.2012 - Order created DAI 4971040 (€1,634.00/SFr.1,994.00) : 11.06.2012 - Order sent to company (6 days to make) : 15.06.2012 - SBC registration, network address, booting etc. : 15.06.2012 - All non-standard components given to the W/S : 22.06.2012 - PCB received : 04.07.2012 - PCB accembled : 09.07.2012 - Software installation started on SBC and Linux PC : 09.08.2012 - Start standalone tests (powering, configuration) : 01.11.2012 - Start tests in VME crate : 26.01.2013 - Study CMX_VAT VHD : 05.06.2013 - Implemented ACE access ------------------------------------------------------------------------------- PCB layout comments during card debugging - write fuse values on the schematics and on the PCB near the fuse - Add Ext. Pull-up on STATLED_L and ERRLED_L (ACE pins 95 and 96) - TS label on the board for TS<5..1> is in fact for ST - Wrong pin numbering of the CADENCE library component COMPACTFLASH_SOCKET50P - QZ2 shall be powered from 2V5 (not 3V3) - 00006 RW ControlPulseReg bits 11/12 ??? - 00008 RO StatusReg bit 1 - use DONE from Spartan? ------------------------------------------------------------------------------- 0. VHDL design 1. Current CMM implementation 1.1. (U71) XCR3384XL-10FT256C CPLD (VME) 1.2. (U70) XCR3384XL-10FT256C CPLD (ACE) 1.3. (U68) Xilinx XCV100E-6FG256C FPGA (TTC) 1.4. TTCDec daughter card and clock distribution 1.5. XILINX System ACE controller and Compact Flash card 1.6. JTAG chain 1.7. LEDs 1.8. Instrument Access points 2. VME/ACE/TTC (VAT) daughter card for CMX 2.1. VME/ACE/TTC (VAT) daughter card interfaces 2.2. Merging VME and ACE CPLDs in the new CPLD (CoolRunner-II) 2.3. Merging VME and ACE CPLDs and TTC FPGA in the new FPGA (Spartan-3AN) 2.4. VME/ACE/TTC (VAT) daughter card implementation 3. 6U VME test card for the VAT daughter card 3.1. VMM module logic for VME to VME-- conversion and VME-- logic (5V0 and 3V3 power domain) 3.2. TTCDec daughter card and clock distribution (3V3 power domain + 5V0 optical receiever) 3.3. Configuration 3.4. VAT DC connectors 3.5. Main FPGA - XILINX Virtex 6 (CMX_ALG) 4. Merging 6U VME test card and VAT daughter card 4.1 PCB layout check 4.2 CMX_ALG VHDL design after layout (pages 12-14) 5. Standalone tests 5.1 6U VME crate preparation (Bruce, Markus, Murrough -> Seth) 5.2 6U VME test card preparation 5.3 Spartan3AN configuration using JTAG and iMPACT software 5.4 Virtex6 configuration using JTAG and iMPACT software 5.5 Chain configuration (Spartan + Virtex6) via JTAG 5.6 Virtex6 configuration on power-on from CF card by System ACE 5.7 CMX power consumption 6. VME tests 6.1 Preparation for the VME tests 6.2 Connecting to SBC in the 6U VME crate in the test rig 6.3 Connecting to XILINX iMPACT on ASTRA 6.4 Study CMX_VAT VHDL 6.5 Study CMX_ALG VHDL 6.6 Study TTCDec card and TTC interface (i2c_ttc) 6.7 Study TTC_DUMP memory 6.8 Study VAT registers 7. Study ACE interface: 7.1 Ian ACE interface 7.2 JEM ACE interface (from Uli): 7.3 Study ACE chip access 7.4 Adapting Uli’s code to work with Ian CMM code 8. CMX_ALG 8.1 Firmware inventory 8.2 CMX_ALG VME access implementation 8.3 CMM VME addressing scheme 8.4 Study of Ian VHDL for CP crate FPGA XCV1000E-6FG860 (U61) 8.5 Work on vme-interface for the BASE FPGA 9. DCS interface (CANbus) 9.1 PPM CANbus microcontroller programming 9.2 CAN code programming 9.3 PVSS/CANbus/TCM 10 CMX test plans 11 CMX firmware 11.1 CMX_BSPT VCCAUX level, Card Serial Number, Resets 11.2 CMX LVDS links control 11.3 Work on ACE interface for the BSPT FPGA (Test on the VAT card 11.4 Work on vme-interface for the BSPT FPGA 11.5 Work on TTC interface for the BSPT FPGA (Test on the VAT card) 11.6 Work on SFP control 11.7 Work on MiniPOD control 11.8 CAN-Bus Monitoring Readout ------------------------------------------------------------------------------- The proposal is to re-implement the VME/ACE/TTC (& CANbus) parts of CMM. The CMX VME/ACE/TTC interface will be based on the current CMM design. HW will be redesigned based on new components and legacy FW ported on new HW. (Part of the interface will be implemented on a VME/ACE/TTC (VAT) daughter card for possible further use on CMX.) In order to test (the VAT daughter card and the rest of the hardware) a 6U VME test card will be designed. To run the 6U VME test card, the L1Calo software will be adapted. Development process Start IN PARALLEL: . Definition of the VAT daughter card interface (with some spare connections), . Selection of the small Virtex 6 FPGA, . definition of a possible CANbus controller card interface, . CADENCE schematics of the VME card based on CMM schematics, . When schematics is done, the PCB layout/production/assembly can be launched IN PARALLEL with the PCB implementation start to work on the firmware (CPLD and FPGA). As soon as the FPGA on the daughter card is defined, a daughter card PCB schematics can be launched. 0. VHDL design ============== Directory structure: ------------------------------------------------------------------------------- .\(XILINX ISE13.x projects)\projectname - project directory .\(XILINX ISE13.x projects)\projectname\projectname_sources - all VHLD files Naming: ------------------------------------------------------------------------------- VHDL design: File name: ------------ Projectname (module_component): CMX_VAT Top level name: CMX_VAT cmx_vat.vhd Package name: CMX_VAT_PKG cmx_vat_pkg.vhd Testbench name: CMX_VAT_TB cmx_vat_tb.vhd PROJECTNAME_IN - input text file for the top module testbed PROJECTNAME_out - output text file for the top module testbed -------------------------------------------------------------------------------- -- Design : CMX_VAT -- Author : Yuri ERMOLINE -- Created : 01.12.2011 Last Modified: xx.xx.201x -- Comments : VME/ACE/TTC interface in CPLD CoolRunner-II -- xx.xx.201x : first modification details; Name FAMILYNAME -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- for testbenches use work.test_pkg.all; -- for modules and testbeds use std.textio.all; -- basic I/O use ieee.std_logic_textio.all; -- I/O for 1164 logic types -------------------------------------------------------------------------------- entity PROJECTNAME is port ( -- general CLK: in std_logic -- FPGA clock pin ); end PROJECTNAME; -- architecture STR of PROJECTNAME is -- STR: structure architecture RTL of PROJECTNAME is -- RTL: Reg Tr Level architecture FSM of PROJECTNAME is -- FSM: Fin Sta Mach architecture BEH of PROJECTNAME is -- BEH: behavioral -- signal declaration begin -- component instantiation end RTL; -------------------------------------------------------------------------------- package PROJECTNAME_PKG is -- type declaration -- constant declaration -- component declaration end PROJECTNAME_PKG; -- package body PROJECTNAME_PKG is end PROJECTNAME_PKG; -------------------------------------------------------------------------------- entity PROJECTNAME_TB is end PROJECTNAME_TB; -- architecture BEH of PROJECTNAME_TB is -- constant declarations -- signal declarations -- component declarations begin -- component instances end BEH; -------------------------------------------------------------------------------- 1. Current CMM implementation ============================= Currently VME part of the CMM is composed of the following parts: - VME bus buffers and logic, connected to the CMM VME/ACE/TTC interface, main CMM FPGAs and the CANbus controller. logic level conversion from 5V0 (VME) to 3V3 (board) - non-volatile VME CPLD which contains some basic registers in a case of a malfunction in the FPGA configuration process. - non-volatile ACE CPLD which provides access to the CMM XILINX System ACE controller, - XILINX System ACE controller and Compact Flash card, - TTC FPGA, which provides an access to the CMM TTC daughter card, - TTCDec daughter card. There are 2 power domains for VME part - 5V0 (VMEbus) and 3V3 (board logic) The original CMM schematics contains 2 CPLD (VME and ACE) and 1 FPGA (TTC): 1.1. (U71) XCR3384XL-10FT256C CPLD (VME) ---------------------------------------- - The CoolRunner XPLA3 XCR3384XL 3.3V, 384 macrocell CPLD; - 10 ns FT256 256-ball Fine-Pitch BGA (FT); 212 user I/O VHDL top file: vme_interface_struct.vhd ENTITY vme_interface IS -- PCB signal PCB component Description PORT( (7) clk40 : IN std_logic; -- CLK40_XTL_VME U54 CY7B991V clock buffer for 40 MHz XTL clock (1) geoadd : IN std_logic_vector (6 DOWNTO 4); -- GEOADD6-4 backplane (1) geoadd_0 : IN std_logic; -- GEOADD0 backplane (+) module_id_b : IN std_logic_vector (11 DOWNTO 0); -- MODULE_ID_B jumpers for U71 only (1) n_ds0_int : IN std_logic; -- DS0_INT* DL2 DELAY delayed BDS0* from 74LVT24 (1) n_sysreset : IN std_logic; -- SYS_RESET* 74LVT245 VME buffer (1) n_write : IN std_logic; -- BWRITE* 74LVT245 from VME buffer (also to U61 and U44) (7) pon_reset : IN std_logic; -- PON_RESET U37 74LCX14 POWER-ON RESET circuit status1_Bus : IN std_logic_vector (15 DOWNTO 0); (5) -- status1_Bus<0> -- CMM_PEC_NZERO U61 XCV1000E crate FPGA (+) -- status1_Bus<4> -- I2C_DONE U68,U70 i2c_ttc FPGA configuration done (?) -- status1_Bus<5> -- CORE_DONE ? not connectes on schematics (CMM_DONE ?) (?) -- status1_Bus<6> -- SERVICE_DONE ? not connectes on schematics (CMMS_DONE ?) (3) -- status1_Bus<7> -- TTC_READY_BUF U59 74LVT245 TTC_READY from TTC card (5) -- status1_Bus<8> -- CMM_LOCKED_DLL U61 DLL locked crate FPGA (5) -- status1_Bus<9> -- CMMS_LOCKED_DLL U44 DLL locked system FPGA (6) -- status1_Bus<10> -- GDAQ_LINKRDY U39 GLink HDMP-1022 (6) -- status1_Bus<11> -- GROI_LINKRDY U40 GLink HDMP-1022 status2_Bus : IN std_logic_vector (7 DOWNTO 0); (5) -- status2_Bus<0> -- CMM_DAQ_FIFO_EF U61 XCV1000E crate FPGA (5) -- status2_Bus<1> -- CMMS_DAQ_FIFO_EF U44 XCV1000E system FPGA (5) -- status2_Bus<2> -- CMM_ROI_FIFO_EF U61 XCV1000E crate FPGA (5) -- status2_Bus<3> -- CMMS_ROI_FIFO_EF U44 XCV1000E system FPGA (5) -- status2_Bus<4> -- CMM_DAQ_FIFO_FF U61 XCV1000E crate FPGA (5) -- status2_Bus<5> -- CMMS_DAQ_FIFO_FF U44 XCV1000E system FPGA (5) -- status2_Bus<6> -- CMM_ROI_FIFO_FF U61 XCV1000E crate FPGA (5) -- status2_Bus<7> -- CMMS_ROI_FIFO_FF U44 XCV1000E system FPGA (1) vme_address : IN std_logic_vector (23 DOWNTO 1); -- VMEA 74LVT574 buffered VME address (1) board_ds : OUT std_logic; -- BOARD_DS DL1 DELAY DTACK* generation, also for U68, U70 (1) brdsel_n : OUT std_logic; -- BRDSEL_N 74LVT245 data transceivers, (?) brdsel_p : OUT std_logic; -- BRDSEL_P U71 only comes to U70 (! unused in U70) (4) can_reg2_bus : OUT std_logic_vector (3 DOWNTO 0); -- CAN_IRQ<0-3> U69 74HCT244 (5) clrpe : OUT std_logic; -- CLRPE comes to U61 and U44 (+) flashs_en : OUT std_logic; -- FLASHS_EN* U70 only comes to U70 (+) int_geoadd : OUT std_logic_vector (6 DOWNTO 4); -- INT_GEOADD6-4 U70 only comes to U70 (+) int_geoadd_0 : OUT std_logic; -- INT_GEOADD0 U70 only comes to U70 (6) laser_dis_daq : OUT std_logic; -- LASER_DIS_DAQ U4 laser disable (6) laser_dis_roi : OUT std_logic; -- LASER_DIS_ROI U5 laser disable (5) n_board_reset : OUT std_logic; -- BOARD_RESET* XCV1000E crate and system FPGAs (4) n_can_reg1_en : OUT std_logic; -- CAN_BUF_EN* U42 74LVT245 read MB90F594 data to VME (4) n_can_reset : OUT std_logic; -- VMECANRESET* (5) n_dll_reset : OUT std_logic; -- DLL_RESET* XCV1000E crate and system FPGAs (+) n_fls_rlalgo : OUT std_logic; -- FLS_RLALGO U70 only comes to U70 (6) n_gdaq_reset : OUT std_logic; -- GDAQ_RESET* U39 GLink HDMP-1022 (6) n_groi_reset : OUT std_logic; -- GROI_RESET* U40 GLink HDMP-1022 (+) n_i2c_en : OUT std_logic; -- I2C_ENABLE* U68 only comes to U68 but not used in VHDL (+) n_reset_i2c : OUT std_logic; -- I2C_RESET* U68 only comes to U68 but not used in VHDL? (3) n_ttc_reset : OUT std_logic; -- TTC_RESET* U17 generate TTC_RESET_XTD* for TTC card (duration?) (5) plybk_en : OUT std_logic; -- PLYBK_EN XCV1000E crate and system FPGAs (5) sp_core : OUT std_logic_vector (2 DOWNTO 1); -- SP_CORE U61 XCV1000E crate FPGA -- sp_core<1> -- Rate Counter Inhibit -- sp_core<2> -- Reset Rate Meter Counters (5) sp_service : OUT std_logic_vector (1 DOWNTO 0); -- SP_SERVICE U44 XCV1000E system FPGA -- sp_service<0> -- Rate Counter Inhibit -- sp_service<1> -- Reset Rate Meter Counters (3) ttc_clksel : OUT std_logic; -- TTC_CLKSEL goes to TTC card (3) ttc_pd : OUT std_logic; -- TTC_PD goes to TTC card (1) vme_data : INOUT std_logic_vector (15 DOWNTO 0) -- VMED 74LVT245 buffered VME data ); Design structure: - vme_interface (vme_interface_struct.vhd) <- package - vme_cmm (vme_cmm.vhd) - CMM_Board_Select (cmm_board_select_rtl.vhd) - CMM_VMEdecoder (cmm_vmedecoder_rtl.vhd_ - Registers (registers_fullstruct.vhd) - ControlGeo (controlgeo_rtl.vhd) - RW_Reg (rw_reg_rtl.vhd) - ReadOnly_Reg (readonly_reg_rtl.vhd) - gen_nds (gen_nds_rtl.vhd) - gen_rlalgo (gen_rlalgo_fsm.vhd) <- package vme_cmm (vme_cmm.vhd) - input_latch (input_latch_rtl.vhd) - pulse_reg_a (pulse_reg_a_fsm.vhd) 2-bytes VME registers (addresses decoded by CMM_VMEdecoder): 00000 RO ModuleIdA Module ID Register A -> ReadOnly_Reg 00002 RO ModuleIdB Module ID Register B -> ReadOnly_Reg 00004 RW ControlModeReg Control Mode Register -> ControlGeo? 00006 RW ControlPulseReg Control Pulse Register -> gen_rlalgo + pulse_reg_a? 00008 RO StatusReg Status Register -> ReadOnly_Reg 0000A RO FifoStatusReg FIFO Status Register -> ReadOnly_Reg 00056 RO VmeId VME CPLD firmware version -> ReadOnly_Reg 00058 RO SystemAceVMEIf System Ace VME Interface -> not implemented in vme_interface CPLD, implemented in cmm_ace_interface 0005C RW CanAccessA CAN Access Register A -> not implemented in vme_interface CPLD 0005E RW CanAccessB CAN Access Register B -> RW_Reg 001FA RW TtcI2Cid TtcI2cId Register -> not implemented in vme_interface CPLD ISE 13.1 report (Fri 4. Nov): Macrocells Pterms Registers Pins FunctionBlockInputs Max.ClockFrequency 101/384(27%) 183/1152(16%) 74/384(20%) 116/208(56%) 471/960(50%) 97.087 MHz 1.2. (U70) XCR3384XL-10FT256C CPLD (ACE) ---------------------------------------- - The CoolRunner XPLA3 XCR3384XL 3.3V, 384 macrocell CPLD; - 10 ns FT256 256-ball Fine-Pitch BGA (FT); 212 user I/O VHDL top file: cmm_ace_interface_struct.vhd ENTITY cmm_ace_interface IS -- PCB signal PCB component Description PORT( (1) addr_vme : IN std_logic_vector (16 DOWNTO 1); -- VMEA 74LVT574 buffered VME address (2) clk : IN std_logic; -- ACE_CLK U46 OSC 20 MHz XTL clock (5) cmm_done : IN std_logic; -- CMM_DONE U61 configuration done (5) cmms_done : IN std_logic; -- CMMS_DONE U44 configuration done (1) ds : IN std_logic; -- BOARD_DS U71 board DS (+) i2c_done : IN std_logic; -- I2C_DONE U68 i2c_ttc FPGA configuration done (+) int_geoadd : IN std_logic_vector (6 DOWNTO 4); -- INT_GEOADD6-4 U71 comes from U71 (+) int_geoadd_0 : IN std_logic; -- INT_GEOADD0 U71 comes from U71 (2) mpu_brdy_b : IN std_logic; -- MPU_BRDY_B U43 ACE System ACE Controller (2) mpu_irq_b : IN std_logic; -- MPU_IRQ_B U43 ACE System ACE Controller (+) n_fls_rlalgo : IN std_logic; -- FLS_RLALGO U71 comes from U71 (+) ncs : IN std_logic; -- FLASHS_EN* U71 comes from U71 (1) rd_nwr : IN std_logic; -- BWRITE* 74LVT245 VME buffer (2) all_done : OUT std_logic; -- ALL_DONE u19 LED (2) cfg_addr : OUT std_logic_vector (2 DOWNTO 0); -- CFG_ADDR U43 ACE System ACE Controller (2) cfg_mode_pin : OUT std_logic; -- CFG_MODE_PIN U43 ACE System ACE Controller (2) mpu_addr : OUT std_logic_vector (6 DOWNTO 0); -- MPU_ADDR U43 ACE System ACE Controller (2) mpu_ce_b : OUT std_logic; -- MPU_CE_B U43 ACE System ACE Controller (2) mpu_oe : OUT std_logic; -- MPU_OE U43 ACE System ACE Controller (2) mpu_we_b : OUT std_logic; -- MPU_WE_B U43 ACE System ACE Controller (2) n_ace_reset : OUT std_logic; -- ACE_RESET* U43 ACE System ACE Controller (1) data_vme : INOUT std_logic_vector (15 DOWNTO 0); -- VMED 74LVT245 buffered VME data (2) mpu_data : INOUT std_logic_vector (15 DOWNTO 0) -- MPU_DATA U43 ACE System ACE Controller ); Design structure: - cmm_ace_interface (cmm_ace_interface_struct.vhd) <- package - vme_cmm (vme_cmm.vhd) - geo_decode (geo_decode_rtl.vhd) - mpi_ctrl (mpi_ctrl_fsm.vhd) - mpu_iface_go (mpu_iface_go_rtl.vhd) - transcvr (transcvr_rtl.vhd) - ff_e (ff_e_rtl.vhd) - reg_e (reg_e_rtl.vhd) - vme_inreg (vme_inreg_rtl.vhd) - vme_outreg (vme_outreg_rtl.vhd) 2-bytes VME registers (addresses decoded by vme_inreg and vme_outreg) 00058 RO SystemAceVMEIf System Ace VME Interface 00300 RW ia_ace_ctrl 00302 RW ia_ace_d_msb 00304 RW ia_ace_rst 00306 RO ia_ace_out 00308 RO ia_ace_stats ISE 13.1 report (Fri 4. Nov) Macrocells Pterms Registers Pins FunctionBlockInputs Max. Clock Frequency 74/384(20%) 148/1152(13%) 51/384(14%) 74/208(36%) 351/960(37%) 97.087 MHz. 1.3. (U68) Xilinx XCV100E-6FG256C FPGA (TTC) --------------------------------------------- - Virtex™-E 1.8 V 600 CLB FG256 (176 I/O) Device CLBArray LogicCells MaxUserI/O RAMBlocks BlockRAMBits DistributedRAM Bits XCV100E 20x30 2,700 196 20 (4K) 81,920 38,400 VHDL top file: i2c_ttc_struct.vhd ENTITY i2c_ttc IS -- PCB signal PCB component Description PORT( (1) addr_vme : IN std_logic_vector (16 DOWNTO 1); -- VMEA 74LVT574 buffered VME address (3) brcst : IN std_logic_vector (7 DOWNTO 2); -- TTC_BRCST U64 74LVT245 from TTC card (3) brcststr1 : IN std_logic; -- TTC_BRCSTSTR1 U58 74LVT245 from TTC card (3) brcststr2 : IN std_logic; -- TTC_BRCSTSTR2 U58 74LVT245 from TTC card (7) clk40 : IN std_logic; -- CLK40_XTL_I2C U54 CY7B991V --> use CLK40_XTL_VME (3) dout : IN std_logic_vector (7 DOWNTO 0); -- TTC_DOUT U66 74LVT245 from TTC card (3) doutstr : IN std_logic; -- TTC_DOUTSTR U58 74LVT245 from TTC card (3) dq : IN std_logic_vector (3 DOWNTO 0); -- BUFDQ U60 74LVT245 from TTC card TTC_DQ (1) ds : IN std_logic; -- BOARD_DS U71 board DS (1) rd_nwr : IN std_logic; -- BWRITE* 74LVT245 VME buffer (-) sp_i2c : IN std_logic_vector (1 DOWNTO 1); -- SP_I2C<1> connected to U71 (T1) but not used? (see 6.7) (3) subaddr : IN std_logic_vector (7 DOWNTO 0); -- TTC_SUBADDR U65 74LVT245 from TTC card (3) ttc_ready_buf : IN std_logic; -- TTC_READY_BUF U59 74LVT245 TTC_READY from TTC card (3) scl : OUT std_logic; -- TTC_SCL to TTC card (-) ttc_buf_dir : OUT std_logic; -- TTC_BUF not connected on PCB to any other chip (1) data_vme : INOUT std_logic_vector (15 DOWNTO 0); -- VMED 74LVT245 buffered VME data (3) sda : INOUT std_logic -- TTC_SDA to/from TTC card ); Design structure: i2c_ttc (i2c_ttc_struct.vhd) <- package vme_cmm (vme_cmm.vhd) bufg_ipb (bufg_ipb_xlx.vhd) ff (ff_rtl.vhd) i2c_clk_gen (i2c_clk_gen_rtl.vhd) i2c_ttc_engine (i2c_ttc_engine_fsm.vhd) i2c_vme (i2c_vme_struct.vhd) ff_e -(ff_e_rtl.vhd) i2c_trigger (i2c_trigger_rtl.vhd) reg_e -(reg_e_rtl.vhd) vme_inreg -(vme_inreg_rtl.vhd) vme_inreg_init (vme_inreg_init_rtl.vhd) vme_outreg -(vme_outreg_rtl.vhd) ibufg_ipb (ibufg_ipb_xlx.vhd) o_tbuf (o_tbuf_rtl1.vhd) sda_outmux (sda_outmux_rtl.vhd) sr_i2c_input (sr_i2c_input_rtl.vhd) sr_ps (sr_ps_rtl.vhd) ttc_dump (ttc_dump_struct.vhd) reg_e -(reg_e_rtl.vhd) ttc_dump_ram (ttc_dump_ram_struct.vhd) dpr256x16 (dr256x16_xcore1.vhd) dpr256x16_xc - XILINX CoreGenerator (not available for CoolRunner-II CPLD !!!) vme_dqram (vme_dqram_rtl.vhd) vme_outreg -(vme_outreg_rtl.vhd) vme_outreg -(vme_outreg_rtl.vhd) 2-bytes VME registers (addresses decoded by ) RW ia_ttc_dqram -->> to be added ISE 10.1 compilation to XCV100E-6FG256C: - translation failed (no dpr256x16_xc for dr256x16_xcore1.vhd) - get EDIF file dpr256x16_xc.edn from Ian - can't directly add EDIF to the sorce files Note EDIF and NGC macros files should not be added to a top level Schematic or HDL project. However, EDIF and NGC files that are instantiated in the design must be included in the project directory or in the macro search path. For details about the macro search path, see Translate Properties. You can set the Translate Properties in the Process Properties dialog box. - set macro search path for Translate, now Translate passed... - Map failed ERROR:MapLib:93 - Illegal LOC on IPAD symbol "ttc_ready_buf" or BUFGP symbol "ttc_ready_buf_BUFGP" (output signal=ttc_ready_buf_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. - remove .ucf file from the project -> automatic pin allocation - Map (and Implement) passed... ISE 13.1 report () -->> to be added ISE 13.1 compilation to Spartan6 Synthesize - XST vme_inreg_init: -- attribute init of floppy: label is init_val(1+ibit downto 1+ibit); -- YE 08.11.2011 ??? -- Line 129: Slice direction does not match type range direction. -- YE 08.11.2011 ??? attribute init of floppy: label is init_val(1+ibit to 1+ibit); -- YE 08.11.2011 ??? changed "downto" to "to" -->> under study ISE 13.1 compilation to Spartan-3AN Spartan-3AN FPGA Slices 1792 3584 5888 11264 Max I/O 195 311 372 502 FT256: 195 195 FG400: 195 311 FG484: 372 375 FG676: 502 Spartan-3AN FPGA XC3S200AN-FTG256 ISE 13.1 report (Mon 12. Dec) Slices Pins 131/1792(7%) 69/195(70%) 1.4. TTCDec daughter card and clock distribution ------------------------------------------------ TTCDec operates with only 3V3 !!! Connector TTCS1 (Samtec QSH-030-01-L-D-A): Pin# Pin Name PCB signal PCB component Description ---- -------- ----------- ------------- ----------- 1 * DoutStr TTC_DOUTSTR U58 74LVT245 VAT DC TTCDSTR 2 * GND 3 * DQ0 TTC_DQ<0> U60 74LVT245 VAT DC TTCDQ<0> 4 * DQ1 TTC_DQ<1> U60 74LVT245 VAT DC TTCDQ<1> 5 * DQ2 TTC_DQ<2> U64 74LVT245 VAT DC TTCDQ<2> 6 * DQ3 TTC_DQ<3> U64 74LVT245 VAT DC TTCDQ<3> 7 * GND 8 * GND 9 * SubAddr0 TTC_SUBADDR<0> U65 74LVT245 VAT DC TTCSADDR 10 * SubAddr1 . 11 * SubAddr2 . 12 * SubAddr3 . 13 * SubAddr4 . 14 * SubAddr5 . 15 * SubAddr6 . 16 * SubAddr7 . 17 * GND 18 * GND 19 * Dout<0> TTC_DOUT<0> U66 74LVT245 VAT DC TTCDOUT 20 * Dout<1> . 21 * Dout<2> . 22 * Dout<3> . 23 * Dout<4> . 24 * Dout<5> . 25 * Dout<6> . 26 * Dout<7> . 27 * GND 28 * GND 29 * Reset_b TTC_RESET_XTD* U17 74F08 VAT DC TTCRST_L 30 * Status1 TTC_READY U59 74LVT245 VAT DC TTCRDY; U52 74FCT244A; U3 74LCX14; LED DS1 31 * GND 32 Status2 TTC_STATUS2 U3 74LCX14 LED??? 33 * GND 34 * GND 35 * In TTCP_BUF MAX9321B use HFBR2119T + MC100LVEL92 36 * GND 37 * In_b TTCN_BUF MAX9321B 38 * GND 39 * GND 40 * GND 41 * GND 42 * P/D TTC_PD U71 VAT DC TTCPD 43 * SCL TTC_SCL U68 VAT DC TTCSLC 44 * ClkSel TTC_CLKSEL U71 VAT DC TTCCLKSE 45 * SDA TTC_SDA U68 VAT DC TTCSDA 46 * VCC 47 * GND 48 * VCC 49 - JTAGTDI TTC_JTAGTDI not connected 50 * VCC 51 - JTAGTMS TTC_JTAGTMS U2 74LVT245 JTAG chain (not used on test card) 52 * VCC 53 - JTAGTDO TTC_JTAGTDO not connected 54 * VCC 55 - JTAGTCK TTC_JTAGTCK U2 74LVT245 JTAG chain (not used on test card) 56 * VCC 57 - JTAGTRST_b TTC_JTAGTRST not connected 58 * VCC 59 * GND 60 * VCC Connector TTCS2 (Samtec QSH-030-01-L-D-A): Pin# Pin Name PCB signal PCB component Description ---- -------- ----------- ------------- ----------- 1 - SinErrStr TTC_SINERRSTR U58 74LVT245 (U68, but not used in VHDL) 2 - DbErrStr TTC_DBERRSTR U58 74LVT245 (U68, but not used in VHDL) 3 * GND 4 * GND 5 * Clock40Des1 not connected not used on CMM -> use on test card (mux with XTL CLK 40 MHz) 6 - Clock40L1A TTC_CLKL1ACC U58 74LVT245 (U68, but not used in VHDL) 7 * GND 8 * GND 9 * Clock40Des2_FBIN CLK40DES2_FDBK U60 74LVT245 10 * GND 11 * GND 12 * Clock40Des1_FBIN CLK40DES1_FDBK U59 74LVT245 13 * Clock40Des2_PLL1 UNBUF_CLK40DES2_OUT1 U60 74LVT245 14 * GND 15 * GND 16 * Clock40Des1_PLL1 UNBUF_CLK40DES1_OUT1 U59 74LVT245 17 - Clock40Des2_PLL2 UNBUF_CLK40DES2_OUT2 TP only (not used?) 18 * GND 19 * GND 20 - Clock40Des1_PLL2 UNBUF_CLK40DES1_OUT2 TP only (not used?) 21 * GND 22 * GND 23 * GND 24 * GND 25 * BrcstStr1 TTC_BRCSTSTR1 U58 74LVT245 VAT DC TTCBSTR1 26 * Brcst2 TTC_BRCST<2> U64 74LVT245 VAT DC TTCBRCST 27 * Brcst3 TTC_BRCST<3> U64 74LVT245 VAT DC TTCBRCST 28 * Brcst4 TTC_BRCST<4> U64 74LVT245 VAT DC TTCBRCST 29 * Brcst5 TTC_BRCST<5> U64 74LVT245 VAT DC TTCBRCST 30 * BrcstStr2 TTC_BRCSTSTR2 U58 74LVT245 VAT DC TTCBSTR2 31 * Brcst7 TTC_BRCST<7> U64 74LVT245 VAT DC TTCBRCST 32 * Brcst6 TTC_BRCST<6> U64 74LVT245 VAT DC TTCBRCST 33 * BCntRes UNBUF_BCNTRST U59 74LVT245 U61 (TTC_BCNTRST) --> ! 34 - EvCntRes TTC_EVCNTRST not used 35 * GND 36 * GND 37 - EvCntHStr TTC_EVCNTHSTR not used 38 * L1Accept UNBUF_L1ACCEPT U58 74LVT245 (U68, but not used in VHDL); U61 --> ! 39 - BCntStr TTC_BCNTSTR not used 40 - EvCntLStr TTC_EVCNTLSTR not used 41 * GND 42 * GND 43 - BCnt1 TTC_BCNT<1> not used 44 - BCnt0 TTC_BCNT<0> not used 45 - BCnt3 TTC_BCNT<3> not used 46 - BCnt2 TTC_BCNT<2> not used 47 - BCnt5 TTC_BCNT<5> not used 48 - BCnt4 TTC_BCNT<4> not used 49 * GND 50 * GND 51 - BCnt7 TTC_BCNT<7> not used 52 - BCnt6 TTC_BCNT<6> not used 53 - BCnt9 TTC_BCNT<9> not used 54 - BCnt8 TTC_BCNT<8> not used 55 - BCnt11 TTC_BCNT<11> not used 56 - BCnt10 TTC_BCNT<10> not used 57 * GND 58 * GND 59 * GND 60 - Ser_B_Ch TTC_SERIAL_B U58 74LVT245 (U68, but not used in VHDL) Clock from 40 MHz XTL and TTC clock Samtec Q-Strip Mezzanine Connectors: • QSH-030-01-L-D-A (socket on motherboard) • QTH-030-01-L-D-A (header on TTCDec) • Pin pitch: 0.5mm, Stack height: 5mm • Pin number: 60 (30 per row, dual rows) 1.5. XILINX System ACE controller and Compact Flash card -------------------------------------------------------- System ACE CF Controller XCCACE-TQG144I has 2 power supply voltages: VCCH (0-7V) - for: Compact Flash port, TSTJTAG port, Power on reset - can be set to 3V3 VCCL (0-4V) - for: other parts - can be set to 2V5 Pin name: IO: Pin # PCB signal: Comment: --------- --- ----- ----------- -------- VCCL domain: Common: CLK IN 93 ACECLK RESET* IN 33 ACERST_L STATLED* OK 95 ERRLED* OK 96 MPU port (VME-- interface via VAT card): MPCE* IN 42 MPCE_L MPWE* IN 76 MPWE MPOE* IN 77 MPOE_L MPIRQ OUT 41 MPIRQ MPBRDY out 39 MPBRDY MPA00-06 IN MPADDR<6..0> MPD00-15 INOUT MPDATA<15..0> CFGJTAG (CMX FPGA configuration): CFGTDO out 82 CFGTDO main FPGA CFGTDI IN 81 CFGTDI main FPGA CFGTCK OUT 80 CFGTCK main FPGA CFGTMS OUT 85 CFGTMS main FPGA CFGINIT* IN 78 CFGINIT_L main FPGA CFGPROG* 79 !No Connect on the board! VCCH domain: Compact Flash port: CFA0-10 A00-10 CF card CFDO-15 D00-15 CF card 8 Control signals CF card CFRSVD IN 133 Pull-up resistor CFGADDR0-2 IN CFGADDR<2..0> CFGMODEPIN IN 89 CFGMODE TSTJTAG port (JTAG connector): TSTTDI IN 102 ACETDI JTAG connector chain TSTTCK IN 101 ACETCK JTAG connector chain TSTTMS IN 98 ACETMS JTAG connector chain TSTTDO OUT 97 ACETDO JTAG connector chain Power on reset: POR_BYPASS IN 108 Jumper H/L * POR_RESET IN 72 PONRST TPS3825-33 POR_TEST* 74 !No Connect on the board! 1.6. JTAG chain --------------- JTAG connecor -> buffer -> TTCDec -> CPLD -> ACE 1.7. LEDs --------- 5.4.1 Front Panel Monitoring (LEDs) The LEDs are located at the top (status indicators) and bottom (power indicators) of the front panel, positioned to match the CPM layout. Colours and behaviour follow a common convention throughout the calorimeter trigger. Fast signals are stretched so that they light the LEDs for long enough to be seen. Green signals indicate normal static conditions, yellow indicate transient operating conditions, and red indicate errors. Description Signal name Colour ----------- ----------- ------ +5 Volts Green Internally generated +3.3V Green Internally generated +2.5V Green Internally generated +1.8V Green System clock is active SYSCLK Green System ACE Status ASTST Green System ACE Error AERR Red Configuration Done ALL_DONE Green TTC Ready TTC_READY Green (also on TTCDec card) VME access in progress Board_Select Yellow Level-1 accept L1Accept Yellow CAN Transmit Yellow CAN Receive Yellow 1.8. Instrument Access points ----------------------------- - Test and Set-up Points - Logic analyser probe points are provided on various data paths to aid in debugging the module. - Oscilloscope test points are provided for important signals including L1A, G-Link DAV. - JTAG boundary scan port - A single In-System-Programming (ISP) port is included for configuring FPGAs. All FPGAs are linked to this port. FPGA configurations are normally memory resident, but loading from VME or ISP is possible for testing. - Ground Points are provided for scope probe grounding in exposed areas of the motherboard. 2. VME/ACE/TTC (VAT) daughter card for CMX ========================================== The 2 CPLDs and TTC FPGA are obsolete now and for the CMX must be replaced by a new devices. Initial study shows that 2 CPLDs can be replaced by a single new device. The TTC FPGA also can be replaced by a small recent XILINX FPGA. These 2 components (CPLD and FPGA) have well defined interface with the rest of the CMM board. For the CMX design this interface can be preserved with some provisional spare connections. They can be grouped on the VAT daughter card for a possible further use on CMX board. The VAT daughter card will be connected to the VME bus, System ACE controller, TTC daughter card, CANbus controller and CMX main FPGA (s). The rest of CMM VME bus buffers and logic will be located on the CMX board, as it’s also connected to the CMX FPGA(s). The TTC daughter card (same as on CMM), XILINX System ACE controller and Compact Flash card and CANbus controller will be located on the CMX board. 2.1. VME/ACE/TTC (VAT) daughter card interfaces ----------------------------------------------- VME-- backplane interface signals: Signal mnemonic Name Component Daughtercard --------------- ---- --------- ------------ A01-A23 Address bus 74LVT574 input fuffer, clock BDS0 (inverted BDS0*) 74LVT574 outputs (for U71, U70, U68) DS* Data Strobe 74LVT245 TS transceiver, output - BDS0* delayed BDS0* from DELAY (DS0_INT*) - for U71 only? D00-D15 Data bus 74LVT245 TS transceiver, OE*-BRDSEL_N, T/R-BWRITE* 74LVT245 A inout DTACK* Data acknowledge SN74F38D OK output BOARD_DS from U71 WRITE* Write 74LVT245 TS transceiver, output - BWRITE* 74LVT574 outputs (for U71, U70, U68) SYSRESET* System reset 74LVT245 TS transceiver, output - SYS_RESET* 74LVT245 output to U71 only GA0,4-6 Geographical backplane directly from backplane VAT daughter card external signals: VME-- backplane (1): -------------------- VME signal # Dir Buffer CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- 12 in jumpers MODULE_ID_B MODID* MODID_L 4 in backplane GEOADD GEOADDR GEOADDR A 23 in 74LVT574 VMEA VMEADDR VMEADDR DS0* 1 in 74LVT245 DS0_INT* VMEDS0* VMEDS_L WRITE* 1 in 74LVT245 BWRITE* VMEWR* VMEWR_L SYSRESET* 1 in 74LVT245 SYS_RESET* VMERST* VMERST_L D 16 inout 74LVT245 VMED VMEDATA VMEDATA DTACK* 1 out SN74F38D BOARD_DS BRDDS BRDDS DTACK* generation 1 out BRDSEL_N BRDSEL* BRDSEL_L data transceivers -- Total: 60 XILINX System ACE CF controller (2): ------------------------------------ Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- 20 MHz clock 1 in ACE ACE_CLK ACECLK ACECLK also goes to ACE MPU Ready 1 in ACE MPU_BRDY_B MPBRDY MPBRDY MPU IRQ 1 in ACE MPU_IRQ_B MPIRQ MPIRQ MPU data 16 inout ACE MPU_DATA MPDATA MPDATA MPU address 7 out ACE MPU_ADDR MPADDR MPADDR MPU write 1 out ACE MPU_WE_B MPWE MPWE MPU ce 1 out ACE MPU_CE_B MPCE MPCE MPU oe 1 out ACE MPU_OE MPOE MPOE CFG addr 3 out ACE CFG_ADDR CFGADDR CFGADDR CFG mode 1 out ACE CFG_MODE_PIN CFGMODE CFGMODE All done 1 out ACE ALL_DONE ALLDONE ALLDONE LED only ACE reset 1 out ACE ACE_RESET* ACERST* ACERST_L -- Total: 35 TTC card (3): ------------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- TTC_BRCST 6 in TTC card TTC_BRCST TTCBRCST TTCBRCST TTC_BRCSTSTR1 1 in TTC card TTC_BRCSTSTR1 TTCBSTR1 TTCBSTR1 TTC_BRCSTSTR2 1 in TTC card TTC_BRCSTSTR2 TTCBSTR2 TTCBSTR2 TTC_DOUT 8 in TTC card TTC_DOUT TTCDOUT TTCDOUT TTC_DOUTSTR 1 in TTC card TTC_DOUTSTR TTCDOSTR TTCDOSTR TTC_DQ 4 in TTC card BUFDQ TTCDQ TTCDQ TTC_SUBADDR 8 in TTC card TTC_SUBADDR TTCSADDR TTCSADDR TTC_READY_BUF 1 in TTC card TTC_READY_BUF TTCRDY TTCRDY TTC_SDA 1 inout TTC card TTC_SDA TTCSDA TTCSDA TTC_SCL 1 out TTC card TTC_SCL TTCSCL TTCSCL TTC_PD 1 out TTC card TTC_PD TTCPD TTCPD TTC_CLKSEL 1 out TTC card TTC_CLKSEL TTCCLKSE TTCCLKSE TTC_RESET* 1 out TTC card TTC_RESET* TTCRST* TTCRST_L TTC_RESET_XTD* for TTC card -- Total: 35 CANbus (4): ----------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- CANbus reset 1 out CANbus VMECANRESET* CANRST* CANRST_L CANbus read 1 out CANbus CAN_BUF_EN* CABRD* CANRD_L CANbus IRQ 4 out CANbus CAN_IRQ<0-3> -- Total: 6 Main FPGAs (5): --------------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- ? 1 in main FPFAs CMM_PEC_NZERO CMMPECNZ CMMPECNZ ? 1 in main FPGAs CMM_DONE CMMDONE CMMDONE configuration ? 1 in main FPGAs CMMS_DONE CMMSDONE CMMSDONE configuration DLL locked 1 in main FPGAs CMM_LOCKED_DLL CMMLDLL CMMLDLL DLLS locked 1 in main FPGAs CMMS_LOCKED_DLL CMMSLDLL CMMSLDLL status2_Bus 8 in main FPGAs ..FIFO.. Board reset 1 out main FPGAs BOARD_RESET* BRDRST* BRDRST_L DLL reset 1 out main FPGAs DLL_RESET* DLLRST* DLLRST_L Playback 1 out main FPGAs PLYBK_EN PLYBKEN PLYBKEN ? 1 out main FPGAs CLRPE CLRPE CLRPE ? 2 out main FPGAs SP_CORE SPCORE SPCORE ? 2 out main FPGAs SP_SERVICE SPSERV SPSERV -- Total: 21 GLink (6): ---------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- GL DAQ ready 1 in GLink GDAQ_LINKRDY GLDRDY GLDRDY GL ROI ready 1 in GLink GROI_LINKRDY GLRRDY GLRRDY GL DAQ reset 1 out GLink GDAQ_RESET* GLDRST* GLDRST_L GL ROI reset 1 out GLink GROI_RESET* GLRRST* GLRRST_L GL DAQ laser 1 out GLink LASER_DIS_DAQ LASDDIS LASDDIS GL ROI laser 1 out GLink LASER_DIS_ROI LASRDIS LASRDIS -- Total: 6 GEN signals (7): ---------------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- 40 MHz clock 1 in CLK40_XTL_VME CLK40 CLK40 use Clock40Des1 from TTCDec or XTL clock PON reset 1 in PON_RESET PONRST PONRST -- Total: 2 JTAG (not in VHDL file): ------------------------ Signal # Dir PCB signal ----------- -- --- ------ ---------- TDI, TCK, TMS 3 in VATTDI, TCK, TMS TDO 1 out VATTDO -- Total: 4 Grand Total: 60 + 35 + 35 + 6 + 21 + 6 + 2 + 4 = 169 (3 connectors x 60 pins?) VAT daughter card internal signals: ----------------------------------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- i2c_done 1 - TTC FPGA I2C_DONE TTCDONE TTCDONE i2c_ttc FPGA configuration done n_i2c_en 1 - I2C_ENABLE* TTCI2CE TTCI2CE U71-U68 (CMX_CPLD - CMX_TTC) n_reset_i2c 1 - I2C_RESET* TTCI2CR TTCI2CR U71-U68 (CMX_CPLD - CMX_TTC) CMX_CPLD internal signals: -------------------------- Signal # Dir CMM signal DC signal VHDL signal Comment ---------- -- --- ------ ---------- --------- ----------- ------- flashs_en 1 - FLASHS_EN* FLASHSEN U71-U70 n_fls_rlalgo 1 - FLS_RLALGO FLSRLALG U71-U70 int_geoadd_0 1 - INT_GEOADD0 INGEOAD0 U71-U70 int_geoadd 3 - INT_GEOADD6-4 INGEOAD U71-U70 2.2. Merging VME and ACE CPLDs in the new CPLD (CoolRunner-II) -------------------------------------------------------------- CMX_CPLD VHDL design (U71+U70): VHDL top file: cmx_cpld.vhd (vme_interface_struct.vhd + cmm_ace_interface_struct.vhd) entity CMX_CPLD is port ( -- Name PCB signal -- VME-- backplane (60 signals) MODID_L: in std_logic_vector(11 downto 0); -- Module ID MODID_L GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR VMEADDR: in std_logic_vector(23 downto 1); -- Address bus VMEADDR VMEDS_L: in std_logic; -- DS strobe VMEDS0_L VMEWR_L: in std_logic; -- Write VMEWR_L VMERST_L: in std_logic; -- System reset VMERST_L VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA BRDDS: out std_logic; -- (Data ack) BRDDS BRDSEL_L: out std_logic; -- Board select BRDSEL_L -- XILINX System ACE CF controller (35 signals) ACECLK: in std_logic; -- ACE clock ACECLK MPBRDY: in std_logic; -- Data ready MPBRDY MPIRQ: in std_logic; -- Int req MPIRQ MPDATA: inout std_logic_vector(15 downto 0); -- MP data MPDATA MPADDR: out std_logic_vector(6 downto 0); -- MP address MPADDR MPWE: out std_logic; -- Write enable MPWE MPCE: out std_logic; -- Chip enable MPCE MPOE: out std_logic; -- Output enable MPOE CFGADDR: out std_logic_vector(2 downto 0); -- Conf address CFGADDR CFGMODE: out std_logic; -- Conf mode pin CFGMODE ALLDONE: out std_logic; -- All conf done ALLDONE ACERST_L: out std_logic; -- ACE reset ACERST_L -- CANbus (6 signals) CANRST_L: out std_logic; -- CANbus reset CANRST_L CANRD_L: out std_logic; -- CANbus read CABRD_L CANIRQ: out std_logic_vector(3 downto 0); -- CANbus req CANIRQ -- TTC FPGA (7 signals) TTCDONE: in std_logic; -- TTC conf done TTCDONE TTCRDY: in std_logic; -- TTC ready TTCRDY TTCI2CE: out std_logic; -- TTC I2C enabl TTCI2CE TTCI2CR: out std_logic; -- TTC I2C reset TTCI2CR TTCPD: out std_logic; -- Mode select TTCPD TTCCLKSE: out std_logic; -- Clock select TTCCLKSE TTCRST_L: out std_logic; -- TTC reset TTCRST_L -- Main FPGAs (21 signal) CMMPECNZ: in std_logic; -- CMM PEC NZERO CMMPECNZ CMMDONE: in std_logic; -- CMM done CMMDONE CMMSDONE: in std_logic; -- CMMS done CMMSDONE CMMLDLL: in std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: in std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: in std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: in std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: in std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: in std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: in std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: in std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: in std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: in std_logic; -- CMMS ROI FFF CMMSRFFF BRDRST_L: out std_logic; -- Board reset BRDRST_L DLLRST_L: out std_logic; -- DLL reset DLLRST_L PLYBKEN: out std_logic; -- Playback en PLYBKEN CLRPE: out std_logic; -- ? CLRPE SPCORE: out std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: out std_logic_vector(1 downto 0); -- ? SPSERV -- GLink (6 signals) GLDRDY: in std_logic; -- GL DAQ ready GLDRDY GLRRDY: in std_logic; -- GL ROI ready GLRRDY GLDRST_L: out std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: out std_logic; -- GL ROI reset GLRRST_L LASDDIS: out std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: out std_logic; -- Laser ROI dis LASRDIS -- GEN (2 signals) CLK40: in std_logic; -- 40MHz Clk CLK40 PONRST: in std_logic -- Power ON rst PONRST ); end CMX_CPLD; Estimate: -> Number of macrocells: 101 + 74 = ~175 Macrocells -> Number of I/O: 60 + 35 + 6 + 7 + 21 + 6 + 2 = 137 Implementation of the new design in XILINX ISE: CoolRunner-II CPLD Macrocells 256 384 512 Max I/O 184 240 270 PQ208 IO: 173 173 173 <- Cadence CERN XC2C512 lib:cnpld FT256 IO: 184 212 212 FG324 IO: - 240 270 CoolRunner-II CPLD in PQ208 package can be used with up to 512 macrocells. CoolRunner-II CPLD: XC2C256-6-PQ208 : VCC=1.8V ISE 13.1 report (Mon 7. Nov) Macrocells Pterms Registers Pins FunctionBlockInputs Max. Clock Frequency 160/256(63%) 374/896(42%) 125/256(49%) 137/173(80%) 469/640(74%) 83.333 MHz Spartan-3AN FPGA 200 400 700 1400 Slices 1792 3584 5888 11264 Max I/O 195 311 372 502 FT256: 195 195 FG400: 195 311 FG484: 372 375 FG676: 502 Spartan-3AN FPGA XC3S200AN-FTG256 ISE 13.1 report (Sun Dec.11) Slices Pins 143/1792(7%) 137/195(70%) 2.3. Merging VME and ACE CPLDs and TTC FPGA in the new FPGA (Spartan-3AN) ------------------------------------------------------------------------- CMX_VME VHDL design (U71+U70+U68): VHDL top file: cmx_vme.vhd (vme_interface_struct.vhd + cmm_ace_interface_struct.vhd + i2c_ttc_struct.vhd) entity CMX_VME is <-- initial entity port ( -- Name PCB signal -- VME-- backplane (60 signals) MODID_L: in std_logic_vector(11 downto 0); -- Module ID MODID_L GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR VMEADDR: in std_logic_vector(23 downto 1); -- Address bus VMEADDR VMEDS_L: in std_logic; -- DS strobe VMEDS0_L VMEWR_L: in std_logic; -- Write VMEWR_L VMERST_L: in std_logic; -- System reset VMERST_L VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA BRDDS: out std_logic; -- (Data ack) BRDDS BRDSEL_L: out std_logic; -- Board select BRDSEL_L -- XILINX System ACE CF controller (35 signals) ACECLK: in std_logic; -- ACE clock ACECLK MPBRDY: in std_logic; -- Data ready MPBRDY MPIRQ: in std_logic; -- Int req MPIRQ MPDATA: inout std_logic_vector(15 downto 0); -- MP data MPDATA MPADDR: out std_logic_vector(6 downto 0); -- MP address MPADDR MPWE_L: out std_logic; -- Write enable MPWE_L MPCE_L: out std_logic; -- Chip enable MPCE_L MPOE_L: out std_logic; -- Output enable MPOE_L CFGADDR: out std_logic_vector(2 downto 0); -- Conf address CFGADDR CFGMODE: out std_logic; -- Conf mode pin CFGMODE ALLDONE: out std_logic; -- All conf done ALLDONE ACERST_L: out std_logic; -- ACE reset ACERST_L -- TTCDec card (35 signals) TTCRDY: in std_logic; -- TTC ready TTCRDY TTCBRCST: in std_logic_vector(7 downto 2); -- TTC broadcast TTCBRCST TTCBSTR1: in std_logic; -- TTC BC str1 TTCBSTR1 TTCBSTR2: in std_logic; -- TTC BC str2 TTCBSTR2 TTCDOUT: in std_logic_vector(7 downto 0); -- TTC data out TTCDOUT TTCDOSTR: in std_logic; -- TTC data str TTCDOSTR TTCDQ: in std_logic_vector(3 downto 0); -- TTC DQ TTCDQ TTCSADDR: in std_logic_vector(7 downto 0); -- TTC subaddr TTCSADDR TTCSDA: inout std_logic; -- TTC SDA TTCSDA TTCSCL: out std_logic; -- TTC SCL TTCSCL TTCPD: out std_logic; -- Mode select TTCPD TTCCLKSE: out std_logic; -- Clock select TTCCLKSE TTCRST_L: out std_logic; -- TTC reset TTCRST_L -- CANbus (6 signals) CANRST_L: out std_logic; -- CANbus reset CANRST_L CANRD_L: out std_logic; -- CANbus read CABRD_L CANIRQ: out std_logic_vector(3 downto 0); -- CANbus req CANIRQ -- Main FPGAs (21 signal) CMMPECNZ: in std_logic; -- CMM PEC NZERO CMMPECNZ CMMDONE: in std_logic; -- CMM done CMMDONE CMMSDONE: in std_logic; -- CMMS done CMMSDONE CMMLDLL: in std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: in std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: in std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: in std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: in std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: in std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: in std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: in std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: in std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: in std_logic; -- CMMS ROI FFF CMMSRFFF BRDRST_L: out std_logic; -- Board reset BRDRST_L DLLRST_L: out std_logic; -- DLL reset DLLRST_L PLYBKEN: out std_logic; -- Playback en PLYBKEN CLRPE: out std_logic; -- ? CLRPE SPCORE: out std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: out std_logic_vector(1 downto 0); -- ? SPSERV -- GLink (6 signals) GLDRDY: in std_logic; -- GL DAQ ready GLDRDY GLRRDY: in std_logic; -- GL ROI ready GLRRDY GLDRST_L: out std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: out std_logic; -- GL ROI reset GLRRST_L LASDDIS: out std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: out std_logic; -- Laser ROI dis LASRDIS -- CMX board (2 signals) CLK40: in std_logic; -- 40MHz Clk CLK40 PONRST: in std_logic -- Power ON rst PONRST ); end CMX_VME; Estimate: -> Number of I/O: 60(VME)+35(ACE)+35(TTC)+6(CAN)+21(MAIN)+6(GLK)+2(CMX) = 165 ISE 13.1 report (Sun Dec.11) - synthesis error due to the ibufg_ipb and bufg_ipb -> remove buffers, Synthesis OK Slices Pins 286/1792(15%) 165/195(84%) ----------- Final implementation: entity CMX_VAT is <-- entity is modifid, compare to the initial test port ( -- Name PCB signal -- 60 VME-- backplane signals MODID_L: in std_logic_vector(11 downto 0); -- Module ID MODID_L GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 2V5 input GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR 2V5 input VMEADDR: in std_logic_vector(23 downto 1); -- Address bus VMEADDR VMEDS_L: in std_logic; -- DS strobe VMEDS0_L VMEWR_L: in std_logic; -- VME Write VMEWR_L VMERST_L: in std_logic; -- System reset VMERST_L VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA Bank 2 VCCO=3V3 BRDDS: out std_logic; -- (Data ack) BRDDS Bank 2 VCCO=3V3 BRDSEL_L: out std_logic; -- Board select BRDSEL_L Bank 2 VCCO=3V3 -- 35 TTCDec card signals TTCRDY: in std_logic; -- TTC ready TTCRDY TTCBRCST: in std_logic_vector(7 downto 2); -- TTC broadcast TTCBRCST TTCBSTR1: in std_logic; -- TTC BC str1 TTCBSTR1 TTCBSTR2: in std_logic; -- TTC BC str2 TTCBSTR2 TTCDOUT: in std_logic_vector(7 downto 0); -- TTC data out TTCDOUT TTCDOSTR: in std_logic; -- TTC data str TTCDOSTR TTCDQ: in std_logic_vector(3 downto 0); -- TTC DQ TTCDQ TTCSADDR: in std_logic_vector(7 downto 0); -- TTC subaddr TTCSADDR TTCSDA: inout std_logic; -- TTC SDA TTCSDA Bank 2 VCCO=3V3 TTCSCL: out std_logic; -- TTC SCL TTCSCL Bank 2 VCCO=3V3 TTCPD: out std_logic; -- Mode select TTCPD Bank 2 VCCO=3V3 TTCCLKSE: out std_logic; -- Clock select TTCCLKSE Bank 2 VCCO=3V3 TTCRST_L: out std_logic; -- TTC reset TTCRST_L Bank 2 VCCO=3V3 -- 35 XILINX System ACE CF controller signals (2V5 IO) ACECLK: in std_logic; -- ACE clock ACECLK MPBRDY: in std_logic; -- Data ready MPBRDY MPIRQ: in std_logic; -- Int req MPIRQ MPDATA: inout std_logic_vector(15 downto 0); -- MP data MPDATA MPADDR: out std_logic_vector(6 downto 0); -- MP address MPADDR MPWE_L: out std_logic; -- Write enable MPWE_L MPCE_L: out std_logic; -- Chip enable MPCE_L MPOE_L: out std_logic; -- Output enable MPOE_L CFGADDR: out std_logic_vector(2 downto 0); -- Conf address CFGADDR CFGMODE: out std_logic; -- Conf mode pin CFGMODE ALLDONE: out std_logic; -- All conf done ALLDONE ACERST_L: out std_logic; -- ACE reset ACERST_L -- 21 ALG FPGAs signals from VAT card for V6 ALG FPGA (2V5 IO bank) CMMPECNZ: in std_logic; -- CMM PEC NZERO CMMPECNZ CMMDONE: in std_logic; -- CMM done CMMDONE config CMMSDONE: in std_logic; -- CMMS done CMMSDONE config CMMLDLL: in std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: in std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: in std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: in std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: in std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: in std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: in std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: in std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: in std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: in std_logic; -- CMMS ROI FFF CMMSRFFF BRDRST_L: out std_logic; -- Board reset BRDRST_L DLLRST_L: out std_logic; -- DLL reset DLLRST_L PLYBKEN: out std_logic; -- Playback en PLYBKEN CLRPE: out std_logic; -- ? CLRPE SPCORE: out std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: out std_logic_vector(1 downto 0); -- ? SPSERV -- 6 GLink signals from VAT card for V6 ALG FPGA (2V5 IO bank) GLDRDY: in std_logic; -- GL DAQ ready GLDRDY GLRRDY: in std_logic; -- GL ROI ready GLRRDY GLDRST_L: out std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: out std_logic; -- GL ROI reset GLRRST_L LASDDIS: out std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: out std_logic; -- Laser ROI dis LASRDIS -- 6 CANbus signals CANRST_L: out std_logic; -- CANbus reset CANRST_L Bank 2 VCCO=3V3 CANRD_L: out std_logic; -- CANbus read CABRD_L Bank 2 VCCO=3V3 CANIRQ: out std_logic_vector(3 downto 0); -- CANbus req CANIRQ Bank 2 VCCO=3V3 -- 18 spare signals from VAT card to V6 ALG FPGA (2V5 IO bank) SP2V5IO: inout std_logic_vector(4 downto 0); -- spare inouts SP2V5IO 2V5 inouts from ALG FPGA SP2V5IN: in std_logic_vector(12 downto 0); -- spare inputs SP2V5IN 2V5 inputs from ALG FPGA -- VAT indicators LEDS: out std_logic_vector(3 downto 0); -- 3V3 out LEDS -- 2 GEN signals CLK40: in std_logic; -- 40MHz Clk CLK40 PONRST: in std_logic -- PowerON reset PONRST ); end CMX_VAT; Estimate: -> Number of I/O: 60(VME)+35(TTC)+35(ACE)+21(ALG)+6(GLK)+6(CAN+2(GEN)+18(spares)+4(LEDS) = 187 Implementation of the new design in XILINX ISE: Spartan-3AN FPGA 200 400 700 1400 Slices 1792 3584 5888 11264 Max I/O 195 311 372 502 FT256: 195 -195- FG400: 195 311 FG484: 372 375 FG676: 502 Spartan-3AN FPGA XC3S200AN-FTG256 2.4. VME/ACE/TTC (VAT) daughter card implementation --------------------------------------------------- Spartan-3AN FPGA XC3S200AN-4FTG256C (17x17 mm2) -> use XC3S400AN-4FTG256C (more logic, same pinout) Package VCCINT VCCAUX VCCO GND I/O INPUT DUAL VREF CLK N.C. FTG256 6 4 16 28 69 21 52 21 32 0 = 249 + 4(JTAG) +2(CONFIG) +1(SUSPEND) = 256 Edge Bank MaxiIO IO IN DUAL VREF CLK Free DUAL pins for configuration Internal Master SPI Flash mode Top 0 47 27 6 1 5 8(G) 46 PUDC_B Right 1 50 1 6 30 5 8 50 Bottom 2 48 11 2 21 6 8(G) 41 M[2:0], VS[2:0], INIt_B <== use VCCO=3V3 Left 3 50 30 7 0 5 8 50 Total 195 69 21 52 21 32 -->187<-- All pins Vin max = 4.6V There are 2 power domains: 3V3 -> 4(JTAG)+1(PROG_B) = 5 (VCCAUX bank) 3V3 -> 60(VME)+35(TTC)+2(GEN)+3(3V3 spares SP3V3_0 - SP3V3_2) = 100 (bank1+3) VAT1 & VAT2 2V5 -> 35(ACE)+6(CAN)+21(ALG)+6(GLK)+19(2V5 spares SP2V5<18..0>) = 87 (Bank0+2) VAT3 & VAT4 CMX_VME (Spartan-3AN) configuration (3V3 power domain) - starts on power-on: - Initial configuration on power-on from internal In-System Flash (ISF) memory - The VCCAUX supply input must be 3.3V. - Mode Pin Settings M[2:0] = <0:1:1> (Internal Master SPI) - single configuration image independent on GeoAddr? (CMX position in the system) - INIT_B during configuration indicates the occurrence of a configuration data error - DONE goes High when FPGA successfully completes configuration. - any low-going pulse on PROG_B, lasting 500 ns or longer, restarts the configuration process. - Re-configuration via JTAG port - is always available any time the FPGA is powered and !!! regardless of the mode pin settings !!! A Spartan-3AN FPGA is programmed using JTAG and iMPACT software in the same way described for other FPGA families in “Programming an FPGA Using JTAG” in Chapter 9. The iMPACT software only requires associating a bitstream with the FPGA, and will automatically generate the PROM file for the In-System Flash, program the Flash in the Spartan-3AN FPGA, and then configure the Spartan-3AN FPGA from the In-System Flash. See “Mode Pin Considerations when Programming a Spartan-3AN FPGA via JTAG using iMPACT” in Chapter 9. - 2 CONFIG pins (PROG_B and DONE) - what to do with them? - DONE - connect to LED (as ALL_DONE) - PROG_B - use to restart programming??? - connect to CANbus connector VAT daughter card components (version with Spartan-3AN FPGA only): - 60-pin VAT card connectors - Spartan-3AN FPGA XC3S200AN-FTG256 - JTAG signals - DONE - connect to LED - 3V3 VCCO for for all 3V3 out and inout on the 6U VME test card - 2V5 VCCO IO banks for V6 - testpoints on the top side of the card for: GND, ... Power requirements (Imax) for XC3S200A: Quiescent current: VCCINT=1V2(50mA) VCCAUX=3V3(12mA) VCCO=3V3(2mA) !!! VCCO=2.5V for V6 signal http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=34821 Power Requirements for XC3S200A: Pin Name Voltage(V) Imax* (mA) Core Vccint 1V2 350 s3 Starter Kit - LP3906 1V2/1A5; use TI tlv1117lv12 1A from 2V5 I/O Vccaux 3V3 100? I/O Vcco 3V3/2V5 3000 4 banks ~0.75A/bank Power from 6U card: 3V3: Vccaux+Vcco = 0.10+0.75 = 0.85A 2V5: Vcco = 2.25A 1V2: Vccint = 0.35 http://www.ti.com/lsds/ti/analog/powermanagement/power_portal.page Cadence PCB design: vat_fpga C:\My Docs\Work\MSU\Upgrade\CMX\cmx_vat daughter card\cadence\cmx_vat.cpm Page 1: ------- 60-pin VAT card connectors (metal plane to GND): ------------------------------------------------ VAT1: 60(VME) = 60 VAT2: 35(TTC)+4(JTAG)+1(VATPROG_B)+2(GLK40,PONRST)+10(NC) +8(3V3) = 60 VAT3: 21(ALG)+6(GLK)+12(SP2V5IN)+6(SP2V5IO)+7(N.C.) +8(2V5) = 60 VAT4: 35(ACE)+6(CAN)+19(ALG not connected on VAT) = 60 ~70 ----------------------------- view fron the top of the VAT card | VAT4 VAT3 VAT2 VAT1 | connectors on the bottom side | 1||2 1||2 1||2 1||2 | | || || || || | | || || || || |~35 | || || || || | | || || || || | |59||60 59||60 59||60 59||60| ----------------------------- 2V5 3V3 Bank 0 & 1 Bank 2 & 3 Component Type / Package CERN Cadence library Supplier # -------------------- ---------------------- ------------------------- ----------- -- 60-pin connectors Samtec QTH-030-01-L-D-A cnconnector: con60p F 1667904 4 Page 2: ------- Configuration and power bank Component Type / Package CERN Cadence library Supplier # -------------------- ---------------------- ------------------------- ----------- -- Spartan-3AN FPGA XC3S200AN-4FTG256C cnpld: xc3s200a Avnet 1 Inv w/ST NC7SZ14 SOT23-5 cncmos NC7S14 F 1417664 1 SMD Green LED Avago HSMG-C170 0805 cndiscrete: LED F 5790852 1 Page 3: ------ Bank 0: (VCCO=2V5) 46 pins - 42 VME signals + CMMDONE + CMMSDONE + CLK40(Global Clock) + ACECLK(Global Clock) = 46 7 input pins MODID_L: in std_logic_vector(11 downto 0); -- Module ID MODID_L GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR 2V5 input GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 2V5 input CLK40: in std_logic; -- 40MHz Clk CLK40 Global Clock ACECLK: in std_logic; -- ACE clock ACECLK Global Clock CMMDONE: in std_logic; -- CMM done CMMDONE config CMMSDONE: in std_logic; -- CMMS done CMMSDONE config VMEDS_L: in std_logic; -- DS strobe VMEDS0_L VMEWR_L: in std_logic; -- VME Write VMEWR_L VMERST_L: in std_logic; -- System reset VMERST_L VMEADDR: in std_logic_vector(23 downto 1); -- Address bus VMEADDR PUDC_B (Pull-Up During Configuration control input) - test point Page 4: ------ Bank 1: (VCCO=2V5) 50 pins - 1 SP2V5IO + 30 TTC signals + 19 ALG FPGAs signals = 50 10 input pins SP2V5IO: inout std_logic_vector(0 downto 0); -- spare inouts SP2V5IO 2V5 inouts from ALG FPGA CMMPECNZ: in std_logic; -- CMM PEC NZERO CMMPECNZ CMMLDLL: in std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: in std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: in std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: in std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: in std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: in std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: in std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: in std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: in std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: in std_logic; -- CMMS ROI FFF CMMSRFFF BRDRST_L: out std_logic; -- Board reset BRDRST_L DLLRST_L: out std_logic; -- DLL reset DLLRST_L PLYBKEN: out std_logic; -- Playback en PLYBKEN CLRPE: out std_logic; -- ? CLRPE SPCORE: out std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: out std_logic_vector(1 downto 0); -- ? SPSERV TTCRDY: in std_logic; -- TTC ready TTCRDY TTCBSTR1: in std_logic; -- TTC BC str1 TTCBSTR1 TTCBSTR2: in std_logic; -- TTC BC str2 TTCBSTR2 TTCDOSTR: in std_logic; -- TTC data str TTCDOSTR TTCBRCST: in std_logic_vector(7 downto 2); -- TTC broadcast TTCBRCST TTCDOUT: in std_logic_vector(7 downto 0); -- TTC data out TTCDOUT TTCDQ: in std_logic_vector(3 downto 0); -- TTC DQ TTCDQ TTCSADDR: in std_logic_vector(7 downto 0); -- TTC subaddr TTCSADDR SUSPEND - to GND Page 5: ------ Bank 2: (VCCO=3V3 or 2V5 - jumper) 41 pins - 18 VME + 5 TTC + 6 CANbus + 8 SV2V5IN + 4 LEDs = 41 This bank is for all 3V3 out and inout on the 6U VME test card 8 input pins BRDDS: out std_logic; -- (Data ack) BRDDS Bank 2 VCCO=3V3 BRDSEL_L: out std_logic; -- Board select BRDSEL_L Bank 2 VCCO=3V3 VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA Bank 2 VCCO=3V3 TTCSDA: inout std_logic; -- TTC SDA TTCSDA Bank 2 VCCO=3V3 TTCSCL: out std_logic; -- TTC SCL TTCSCL Bank 2 VCCO=3V3 TTCPD: out std_logic; -- Mode select TTCPD Bank 2 VCCO=3V3 TTCCLKSE: out std_logic; -- Clock select TTCCLKSE Bank 2 VCCO=3V3 TTCRST_L: out std_logic; -- TTC reset TTCRST_L Bank 2 VCCO=3V3 CANRD_L: out std_logic; -- CANbus read CABRD_L Bank 2 VCCO=3V3 CANIRQ: out std_logic_vector(3 downto 0); -- CANbus req CANIRQ Bank 2 VCCO=3V3 CANRST_L: out std_logic; -- CANbus reset CANRST_L Bank 2 VCCO=3V3 LEDS: out std_logic_vector(3 downto 0); -- 3V3 out LEDS SP2V5IN: in std_logic_vector(7 downto 0); -- spare inputs SP2V5IN 2V5 inputs from ALG FPGA Dedicated configuration pins: Mode Pin Settings M[2:0] = <0:1:1> (Internal Master SPI) Variant Select Pins VS[2:0] = <1:1:1> Furthermore, the VS[2:0] pins have dedicated pull-up resistors that are active, regardless of the PUDC_B pin, whenever the M[2:0] mode-select pins are set for Internal Master SPI mode. INIt_B - test point Jumper to select VCCO_2 (3V3 or 2V5) - for test Component Type / Package CERN Cadence library Supplier # -------------------- ---------------------- ------------------------- ----------- -- 1 Inv w/ST NC7SZ14 SOT23-5 cncmos NC7S14 F 1417664 4 SMD Yellow LED Avago HSMY-C170 0805 cndiscrete: LED F 5790876 4 3-pin jumper cnconnector: CON3P C Page 6: ------- Bank 3: (VCCO=2V5) 50 pins - 35 ACE + 6 GLK + 4 SV2V5IN + 4 SP2V5IO = 50 10 input pins MPDATA: inout std_logic_vector(15 downto 0); -- MP data MPDATA MPADDR: out std_logic_vector(6 downto 0); -- MP address MPADDR CFGADDR: out std_logic_vector(2 downto 0); -- Conf address CFGADDR MPWE_L: out std_logic; -- Write enable MPWE_L MPCE_L: out std_logic; -- Chip enable MPCE_L MPOE_L: out std_logic; -- Output enable MPOE_L CFGMODE: out std_logic; -- Conf mode pin CFGMODE ALLDONE: out std_logic; -- All conf done ALLDONE ACERST_L: out std_logic; -- ACE reset ACERST_L GLDRST_L: out std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: out std_logic; -- GL ROI reset GLRRST_L LASDDIS: out std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: out std_logic; -- Laser ROI dis LASRDIS MPBRDY: in std_logic; -- Data ready MPBRDY MPIRQ: in std_logic; -- Int req MPIRQ GLDRDY: in std_logic; -- GL DAQ ready GLDRDY GLRRDY: in std_logic; -- GL ROI ready GLRRDY PONRST: in std_logic -- PowerON reset PONRST SP2V5IN: in std_logic_vector(12 downto 8); -- spare inputs SP2V5IN 2V5 inputs from ALG FPGA SP2V5IO: inout std_logic_vector(4 downto 1); -- spare inouts SP2V5IO 2V5 inouts from ALG FPGA --- Total on 4 banks = 46+50+29+41 = 165 3. 6U VME test card for the VAT daughter card ============================================= In order to test the daughter card the 6U VME card will be designed. It will contain the following parts: . VMM module logic for VME to VME-- conversion . VME bus: buffers, logic, delay lines, GeoAddr switch, 12 MODULE_ID jumpers . connectors for the TTC daughter card, TTC components . JTAG connector + buffer + jumpers . XILINX System ACE controller and Compact Flash card (CF card on the VME board) . connectors for the VAT daughter card . Virtex 6 FPGA (XC6VLX240T-1FFG784C) to test FPGA configuration process (CMX_ALG) . configuration interface (System ACE VCCL=2V5) . VME-- interface to main FPGA (2V5 IO - level translators?) . VAT interface to main FPGA (VCCO=2.5V for V6 signals IO on VAT card) . Indicators (LEDs), test points . CANbus interface connector for CANbus controller DC (possible common development with GOLD) . VAT card . 5V0 to 3V3, 2V5, 1V2, 1V0 power regulators . decouplings . draft layout of PCB and VAT card - connector for spare pins of CMX_ALG FPGA (FMC connector???) - I don’t think we will use it ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard FMC carrier cards, which support the high-pin count connector, shall use connector type: CC-HPC-10 : Samtec Part Number ASP-134486-01 or equivalent FMC XM105 Debug Card User: The XM105 uses Samtec FMC HPC connector part number ASP-134488-01. The XM105 connector mates with a FMC LPC connector or an FMC HPC connector on Xilinx boards. There are 3 power domains - 5V0 (VME connector), 3V3 (VME--, TTC, CF card), 2V5 (Virtex6 CMX_ALG) Cadence PCB design: cmx_vme C:\My Docs\Work\MSU\Upgrade\CMX\cmx_vme test board\cadence\cmx_vme.cpm 3.1. VMM module logic for VME to VME-- conversion and VME-- logic (5V0 and 3V3 power domain) -------------------------------------------------------------------------------------------- Page 1: ------- VME J1/P1 connector, address buffer, data trancievers (3V3, 5V0 input tolerant) Test points: DS0*, DS1*, AS*, WRITE*, DTACK*, BERR*, SYSRESET*; BRDSEL_L, VMEDS GND jumpers for probe Component Type / Package CERN Cadence library Supplie -------------------- ---------------------- ------------------------- ----------- VME 5x32 Rt-Ang Plug Harting 02-01-160-2101 cnconnector: CON160ABCDZ: F 1339830 RS 235-6406 VME address buffer 74LVT574 TSSOP interface: LVT575 F 1013797 VME data/cntl buffer 74LVT245 SOIC20 interface: LVT245 F 1013795 Jumper cnpassive: JUMPER C 07.88.24.516.1 Page 2: ------- GEOADDR and MODID jumpers (3V3) Logic to emulate VMM module to generate VME-- signals and generate BERR* (use NC7SZ, 1.65V to 5.5V VCC operating range. Inputs tolerate voltages up to 6V independent of VCC operating voltage) DS* is generated by an “OR” gate ORing DS0* and DS1* from 6U VME This signal is delayed in 5x5ns delay line --> VMEDS signal for VME address buffer The SBC is capable of generating VME cycles with a variety of address and data bus widths (A16, A24, A32, D8, D16, and D32). The VME-- backplane supports only A24D16 cycles. To prevent inadvertent use of other address modes, the VMM includes logic to check the VME address modifier (AM) code. The only permitted AM codes are 39 (A24 non-privileged data access) and 3D (A24 supervisory data access). The permitted D16 data width corresponds to DS0*=DS1*=0, LWORD*=1. If the VMM detects any other VME cycle type being attempted, it terminates the cycle by asserting BERR* to the 6U SBC. In this case, the DS* signal is not propagated to the VME-- backplane, and no VME-- cycle occurs. quartz oscillator, XTL clock selector (CLK40) PON reset generated by TPS3825-50DBVT from P5V Test points: VMEDS_L, BRDDS, CLOCK40DES1, PONRST Component Type / Package CERN Cadence library Supplier # -------------------- ---------------------- ------------------------- ----------- -- 1 2-input NAND NC7SZ00 SOT23-5 cncmos NC7SZ00 F 1417656 2 6V input tolerance 3V 5x5ns delay line DS1100LZ-25+ SO8 - (delay 5 tap) M 700-DS1100LZ-25 3? 6 inverters SN74F04DR SOIC14 fast: F04 M 595-SN74F04DR 1 8 input NAND SN74F30DR SOIC14 fast: F30 M 595-SN74F30DR 1 2 flip-flops SN74F74DR SOIC14 fast: F74 M 595-SN74F74DR 1 2 input NAND O.C. SN74F38 SOIC14 fast: F38 M 595-SN74F38DR 1 Osc 40MHz 3V3 SG-310 SCF C cndiscrete: qz_sg310 F 1278069 LV 2-Input Mux 74LCX157 SOIC16 hcmos: HC157 F 1013779 Tactile Switch OMRON B3SN-3012 cnpassive: SW-... F 1713006 3V3 voltage monitor TPS3825-33DBVT SOT23-5 cnlinear: TPS3825 M 595-TPS3825-33DBVT 1 Terminal strip 2x20 PIN BAR male/male cnpassive: JUMPER2P C 07.88.26 Short sircuit shunt COMATEL 1730 00040 2 cnpassive: JUMPER2P C 09.55.10.950.1 15 3.2. TTCDec daughter card and clock distribution (3V3 power domain + 5V0 optical receiever) ------------------------------------------------------------------------------------------- Page 3: ------- TTC optical receiver, PECL tp LVPECL converter, TTCDec connectors, clock buffer, TTC reset generation Test points: Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- TTC optical receiver HP HFBR-2119T cninterface: HFBR2119T F 1247648 M 630-HFBR-2119TZ Triple PECL to LVPECL MC100LVEL92 SOIC20 cninterface: MC100LVEL92 F 1155551 M 863-MC100LVEL92DWG Ferrite bead 330ohm Murata BLM21P 0805 cndiscrete: FERRITE F 1515663 BLM21PG331SN1D 60-pin connectors Samtec QSH-030-01-L-D-A cnconnector: CON60P F 1667876 2 LVT buffer 74LVT245 SOIC20 interface: LVT245 F 1013795 1 Multivibrator w/Rst 74LS123 SOIC16 lsttl: LS123 F 1105904 1 2-input AND NC7SZ08 SOT23-5 cncmos NC7SZ08 F 1013807 1 6V input tolerance SMD XR7 ceramic cap 100nF/16V 0603 cnpassive: CAPCERSMDCL2 F SMD XR7 ceramic cap 10uF/25V 1210 cnpassive: CAPCERSMDCL2 F Page 4: ------- TTC signal buffers, hardwired ID and mastermode bits after reset Test points: TTCRDY, TTCBCR, TTCL1A Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- LVT buffer 74LVT245 SOIC20 interface: LVT245 F 1013795 4 Buffer with TS out 74LVT244 SOIC20 interface: LVT244A F 1013793 2 3.3. Configuration ------------------ There are two FPGAs on the board - CMX_VME (Spartan-3AN) and CMX_ALG (Virtex-6) FPGA configuration starts on power-on CMX_ALG (Virtex-6) configuration using XILINX System ACE (2V5 power domain): ---------------------------------------------------------------------------- - Initial configuration on power-on from CF card by System ACE via CFGJTAG port using CMX_ALG JTAG port CF card can be re-programmed from System ACE MPU interface (connected to VME--) From Ian: In theory, the ACE micro-processor interface can be used to access in the Flash card from VME. However, I’ve never done this and don’t have software for it. Bruce might have. The general principle behind this interface is the same as the JEM, but I know the details are different. - CMX_ALG can be configured from System ACE MPU interface (connected to VME--) using CMX_ALG JTAG port To be investigated - CMX_ALG can be configured from System ACE TSTJTAG port (connected to IMPACT) using CMX_ALG JTAG port To be investigated Compact Flash Socket Molex 55358-5029 cnconnector: COMPACTFLASH_SOCKET50P F 1211009 M 538-55358-5029 Eject Mechanism Molex 55356-0011 M 538-55356-0011 System ACE CF Contr XILINX XCCACE-TQG144I cninterface: XCCACE Digikey Osc 20MHz 3V3 SG-310 SCF C cndiscrete: qz_sg310 F 1278064 Primary JTAG chain: JTAG connecor -> buffer -> Spartan-3AN (on VAT card) -> System ACE Jumpers are provided to exclude from the chain Spartan-3AN OR System ACE (3V3) 3AN+ACE 3AN only ACE only J1 J6 + + + - - + J2 J7 + + + - - + J3 J8 + + + - - + J4 J9 + + + - - + J5 J10 - - - + + - 3.4. VAT DC connectors ---------------------- Page 6: ------- Test points: CMMDONE, CMMSDONE, BRDRST_L, MPWE_L, MPCE_L, MPOE_L, MPBRDY 60-pin VAT card connectors (metal plane to GND): ------------------------------------------------ VAT1: 60(VME) = 60 VAT2: 35(TTC)+4(JTAG)+1(VATPROG_B)+2(GLK40,PONRST)+2(NC) +8(VCCINT)+8(3V3) = 60 VAT3: 21(ALG)+6(GLK)+12(SP2V5IN)+6(SP2V5IO)+7(N.C.) +8(2V5) = 60 VAT4: 35(ACE)+6(CAN)+19(ALG not connected on VAT) = 60 ~50 ----------------------------- view fron the top of the VAT card | VAT4 VAT3 VAT2 VAT1 | connectors on the bottom side | 1||2 1||2 1||2 1||2 | | || || || || | | || || || || |~30 | || || || || | | || || || || | |59||60 59||60 59||60 59||60| ----------------------------- 2V5 3V3 Bank 0 & 1 Bank 2 & 3 Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- 60-pin connectors Samtec QSH-030-01-L-D-A cnconnector: CON60P F 1667876 3 Page 7: ------- Indicators: System Name Type Color Comment Label on PCB ------ ---- ---- ----- ------- ------------ * VME BERR_LED* Pulse Red 5V5 BERR * BRDDS Pulse Yellow 3V3 BRDS * TTC CLK40 Pulse Green 3V3 CL40 ? TTCL1A Pulse Yellow 3V3 * (TTCDec) TTCRDY Level Green 3V3 * STATUS2 Level Green 3V3 STAT * ACE STATLED_L Level Green 2V5 AST * ERRLED_L Level Red 2V5 AER * ALLDONE Level Green 2V5 ALL Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- Multivibrator w/Rst 74LS123 SOIC16 lsttl: LS123 F 1105904 1 2-input AND NC7SZ08 SOT23-5 cncmos NC7SZ08 F 1013807 1 Inv w/ST NC7SZ14 SOT23-5 cncmos NC7S14 F 1417664 SMD Red LED Avago HSMS-C170 0805 cndiscrete: LED F 5790839 SMD Green LED Avago HSMG-C170 0805 cndiscrete: LED F 5790852 SMD Yellow LED Avago HSMY-C170 0805 cndiscrete: LED F 5790876 3.5. Main FPGA - XILINX Virtex 6 (CMX_ALG) ------------------------------------------ Virtex6 XC6VLX240T-1FFG784C (or XC6VLX75T-1FFG784C): VCCINT=1V0 VCCAUX=2V5 VCCO=2V5 Page 8: ------- VME address signals level shifter from 3V3 to 2V5 Virtex 6 IO banks 25(GClock) + 26 Test points: CMX_ALG VHDL design (a la U61 XCV1000E crate FPGA): VHDL top file: cmx_alg.vhd Initial design: port ( -- Name PCB signal -- 4 GeoAddr signals 2V5 GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 2V5 input GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR 2V5 input -- 44 VME-- level shifted signals from level shifter for V6 ALG FPGA (3V3 to 2V5) 25 V6_VA: in std_logic_vector(23 downto 1); -- Address bus V6_VA 25 V6_VD: inout std_logic_vector(15 downto 0); -- Data bus V6_VD V6_VW_L: in std_logic; -- VME Write V6_VW_L V6_BDS: in std_logic; -- (Data ack) V6_BDS V6_BS_L: in std_logic; -- Board select V6_BS_L V6_L1A: in std_logic; -- TTC L1 Accept V6_L1A V6_BCR: in std_logic; -- TTC BC Reset V6_BCR -- 19 ALG FPGAs signals to/from VAT card for V6 ALG FPGA (2V5 IO bank) CMMPECNZ: out std_logic; -- CMM PEC NZERO CMMPECNZ CMMLDLL: out std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: out std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: out std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: out std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: out std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: out std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: out std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: out std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: out std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: out std_logic; -- CMMS ROI FFF CMMSRFFF BRDRST_L: in std_logic; -- Board reset BRDRST_L DLLRST_L: in std_logic; -- DLL reset DLLRST_L PLYBKEN: in std_logic; -- Playback en PLYBKEN CLRPE: in std_logic; -- ? CLRPE SPCORE: in std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: in std_logic_vector(1 downto 0); -- ? SPSERV -- 6 GLink signals from VAT card for V6 ALG FPGA (2V5 IO bank) GLDRDY: out std_logic; -- GL DAQ ready GLDRDY GLRRDY: out std_logic; -- GL ROI ready GLRRDY GLDRST_L: in std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: in std_logic; -- GL ROI reset GLRRST_L LASDDIS: in std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: in std_logic; -- Laser ROI dis LASRDIS -- 1 GEN level shifted signal from level shifter (3V3 to 2V5) 25 V6_CLK: in std_logic; -- V6_CLK v6_CLK CLK40 -- spare connections to VAT card and to Spartan-3AN FPGA 35 SP2V5IN: out std_logic_vector(11 downto 0); -- VAT spares IN SP2V5IN 35 SP2V5IO: inout std_logic_vector(5 downto 0); -- VAT spares IO SP2V5IO -- TTC clocks 35 CLK1: in std_logic; -- Des Clk 1 CLK1 CLK40DES1 35 CLK2: in std_logic -- Des Clk 2 CLK2 CLK40DES2 ); CANbus outputs from VAT card are not connected to CMX_ALG IO= 4 + 44 + 19 + 6 + 1 = 74 (2 IO banks, 25(GC) + 26, 80 IO) IO bank = 40 pins (IO) Clocks • Every bank has four clock-capable (CC) pin pairs driving four BUFIOs and/or four BUFRs (including inner columns). • Inner-column CCs can also drive MMCMs in the same region. This is the highest performance connection. • The eight global clock (GC) pin pairs are marked as with a •. • There are two GC pairs each in banks 24, 25, 34, 35. • GCs can connect to all MMCMs and BUFGs Bank 25 (40 signals): - V6_VA<23..1> -- 23 VME-- level shifted signals from level shifter for V6 ALG FPGA (3V3 to 2V5) - V6_VD<15..0> -- 16 VME-- level shifted signals from level shifter for V6 ALG FPGA (3V3 to 2V5) - V6_CLK -- 1 GEN level shifted signal from level shifter (3V3 to 2V5) Bank 26 (40 signals): - 9 VME-- signals - 4 GEOAD + 5 - 19 ALG FPGAs signals to/from VAT card for V6 ALG FPGA (2V5 IO bank) - 6 GLink signals from VAT card for V6 ALG FPGA (2V5 IO bank) - 6 not connected Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- 3V3 to 2V5 shifter TI SN74CB3T16211DGGR cninterface: SN74CBTD16211 M 595-SN74CB3T16211DGG Page 9: ------- Bank 35 (GClock) - 19 spare signals from VAT card for future extention (not connected on VAT to the Spartan-3AN FPGA) - 12 spare Spartan-3AN input pins (2V5 IO bank) for for V6 ALG FPGA (SP2V5IN<11..0>) - 6 spare Spartan-3AN inout pins (2V5 IO bank) for for V6 ALG FPGA (SP2V5IO<5..0>) - 2 Globl Clocks (CLK1 and CLK2) - level shifted signals from level shifter (3V3 to 2V5) CANbus controller interface: The CMM uses a Fujitsu MB90F591 microcontroller as an interface to the CANbus in the processing crate to pass voltage and temperature information via the TCM module in the crate to the ATLAS DCS. CAN based monitoring might be required on TP as well (tbd). A CANbus daughter module might in this case be a common item. Please note that there are architectural differences between the UK approach and the JEM scheme. While the UK modules are trying to make use of the Fujitsu analogue resources (I believe) the JEM is using the Fujitsu basically as a CAN to I2C bridge only, with all monitoring done via I2C sensors. This scheme requires just a very small number of lines to be routed between a daughter card and the main board. -->> under investigation (possible common development with GOLD) CANbus interface connector (IO - to the CANbus card): Pin name: IO: Pin # PCB signal: Comment: --------- --- ----- ----------- -------- VATPROG_B OUT 1 VATPROG_B 3V3 restart VAT card configuration ? GEOADDR0 IN 1 GEOADDR0 2V5 (use LVT244 on the CANbus card) GEOADDR1-3 IN 3 GEOADDR 3V3 (use LVT244 on the CANbus card) GEOADDR<6..4> IN 3 GEOADDR 2V5 (use LVT244 on the CANbus card) VMEDATA<7..0> INOUT 8 GEOADDR 3V3 (use LVT245 on the CANbus card) - OE* -> CANRD_L CANIRQ<3..0> IN 4 CANIRQ 2V5 (use LVT244 on the CANbus card) CANRD_L IN 1 CANRD_L 2V5 read MB90F594 data to VME (OE for LVT245) CANRST_L IN 1 CANRST_L 2V5 DXP_Q, DXN_Q, IN 2 DXP_Q, DXN_Q, temperature sense lines 5V0 1 3V3 1 GND 4 ---- CMX_ALG configuration (Bank 0)- config via JTAG from System ACE (VCCL=2V5) Pin name: IO: Pin # PCB signal: Comment: --------- --- ----- ----------- -------- INIT_B_0 OUT CFGINIT_L to system ACE pullup 4K7 DONE_0 OUT CMM_DONE to VAT card (CMX_VME FPGA) pullup 330 1% M[2:0] IN pullup/down JTAG mode M[2:0]=101 HSWAPEN IN GND PROGRAM_B IN pullup 4K7 AVSS_0 analog ground see ug370 ferrite bead 10-1000 MHz BLM18HK102SN1D AVDD_0 analog power see ug370 VP_0 sense AVSS_0 analog sense line (use test point?) VREFP_0 ref AVSS_0 VN_0 sense AVSS_0 analog sense line (use test point?) VREFN_0 ref AVSS_0 DXP_0 sense DXP temperature sense line DXN_0 sense DXN temperature sense line VBATT_0 power GND the encryption keys retaining battery DIN_0 not connected RDWR_B_0 not connected CSI_B_0 not connected DOUT_BUSY_0 not connected CCLK_0 not connected TDO_0 OUT CFGTDI System ACE TCK_0 IN CFGTCK System ACE TMS_0 IN CFGTMS System ACE + pullup TDI_0 IN CFGTDO System ACE + pullup VFS_0 power GND When not programming eFUSE, connect VFS to GND Power Supplies Required for Configuration: VCCINT Internal core voltage (1V0) VBATT Encryption Key battery supply (GND) VCCO_0 Configuration bank supply voltage (2V5) VCCAUX Auxiliary power input for configuration logic and other FPGA functions (2V5) ? VCCO_24 Dual-mode configuration pin output supply voltage. ? VCCO_34 Standard I/O voltage levels supported for configuration are 1.8V and 2.5V. Managing Unused GTX Transceivers: http://www.xilinx.com/support/documentation/user_guides/ug366.pdf If the GTX transceiver will never be used, the transceiver bank can be unpowered (page 276) Quad Pin or Pin Pair of the Unused Column Connection (page 279) MGTAVCC GND MGTAVTT GND MGTREFCLKP/MGTREFCLKN FLOAT Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- Virtex 6 FPGA XC6VLX75T-1FFG784C cnpld: XC6VLX75T_FF784 Use XC6VLX75T-1FFG784C Ferrite bead 1K Murata BLM18HK102SN1D cndiscrete: FERRITE F 1515734 30-pin female conn ERNI C/3 30-F-ABC cnconnector CON30ABC C 09.61.35.055.0 Page 10: -------- Spare banks 14, 15, 16, 23, 24, 34, 35 - VCCO=2V5 Page 11: -------- VME J2/P2 connector (5V0 and GND only) Power regulators with fuses Test points: 5V0, 3V3, 2V5 http://www.ti.com/lsds/ti/analog/powermanagement/power_portal.page http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=34821 Power Requirements for XC3S200A: XC3S400A: Pin Name Voltage(V) Imax*(mA) Imax*(mA) Core Vccint 1V2 350 600 OK I/O Vccaux 3V3 100 150 OK I/O Vcco 3V3/2V5 3000 (4 banks ~0.75A/bank) 4000 (4 banks ~1.0A/bank) OK http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=65246 Power Requirements for XC6VLX240T XC6VLX75T Pin Name Voltage(V) Imax* Core Vccint 1V0 10000 (10W) | 3700 (3.7W) I/O Vcco 2V5 6000 (15W) | --> max 30W 3000 (7.5W) --> ~15W I/O Vccaux 2V5 1500 ( 4W) | 1500 (3.7W) --> Use pin compatible XC6VLX75T-1FFG784C (less power) VME --> 5V0 3 pins max2A --> 30W max (--> use second VME connector?) Power requirements estimation: 3V3: = 1.00 A PTH05050W (RSET = 698 O Vo = 3.3 V) 2V5: = 6.80 A PTH05050W (RSET = 2.21 kO Vo = 2.5 V) - 4.5A for Virtex6 PTH05050W (RSET = 2.21 kO Vo = 2.5 V) - 2.3A for VAT card VCCO (3.0A for XC3S400A) 1V2: = 0.35 A PTH05050W (RSET = 17.4 kO Vo = 1.2 V) or (RSET = 5.49 kO Vo = 1.8 V) - for VAT card VCCINT 1V0: = 3.70 A PTH05050W (RSET = 36.5 kO Vo = 1.0 V) - for Virtex6 core PTH05050W (5V Input Voltage, 0.8V to 3.6V Output Voltage Adjust, up to 6A Output Current) Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- VME 5x32 Rt-Ang Plug Harting 02-01-160-2101 cnconnector: CON160ABCDZ F 1339830 RS 235-6406 6A adj power module PTH05050W cnlinear: PTH05050W F Fuse 1A with holder Littelfuse 154.001.DR cnpassive: FUSE-HOLDER F Fuse 2A with holder Littelfuse 154.002.DR cnpassive: FUSE-HOLDER F Fuse 3A with holder Littelfuse 154.003.DR cnpassive: FUSE-HOLDER F Fuse 5A with holder Littelfuse 154.005.DR cnpassive: FUSE-HOLDER F 9943668 RESISTOR, 0603, 698R 1%, 0.1W PANASONIC ERJ3EKF6980V 0603 F 2059321 RESISTOR, 0603, 15KR 1% CRCW060315K0FKEA 0603 F 1469758 -- not used 3V3 7A volt reg LT1584CT-3.3 TO-220 cnlinear: LT1584 F 1273601 2V5 7A volt reg LT1584CT adj TO-220 cnlinear: LT1584 F Heat Sink F 707351 1V2 1.0A volt reg TI tlv1117lv12 SOT223 not 1V2 1.0A volt reg NX1117CE <--? not in library F 2057277 1V2 0.2A volt reg TLV70012 cnlinear: TLV700XX M 595-TLV70012DDCT 4. Merging 6U VME test card and VAT daughter card ================================================= Page 1: ------- Component Type / Package CERN Cadence library Supplie -------------------- ---------------------- ------------------------- ----------- VME 5x32 Rt-Ang Plug Harting 02-01-160-2101 cnconnector: CONVME64XP1 F 1339830 RS 235-6406 VME address buffer 74LVT574WM SOIC20 cncmos: 74HC574 F 1013797 VME data/cntl buffer 74LVT245WM SOIC20 cncmos: 74245 F 1013795 Page 2: ------- Component Type / Package CERN Cadence library Supplier -------------------- ---------------------- ------------------------- ----------- 6 inverters SN74F04DR SOIC14 cncmos: 7404 M 595-SN74F04DR 8 input NAND SN74F30DR SOIC14 cncmos: 74HC30 M 595-SN74F30DR 2 flip-flops SN74F74DR SOIC14 cncmos: 7474 M 595-SN74F74DR 2 input NAND O.C. SN74F38 SOIC14 cncmos: 7438 M 595-SN74F38DR LV 2-Input Mux 74LCX157 SOIC16 cncmos: 74157 F 1013779 Page 3: ------- Component Type / Package CERN Cadence library Supplier -------------------- --------------------- ------------------------- ----------- LVT buffer 74LVT245WM SOIC20 cncmos: 74245 F 1013795 Multivibrator w/Rst 74LS123 SOIC16 cncmos: 74123 F 1105904 Page 4: ------- Component Type / Package CERN Cadence library Supplier -------------------- --------------------- ------------------------- ----------- LVT buffer 74LVT245WM SOIC20 cncmos: 74245 F 1013795 Buffer with TS out 74LVT244WM SOIC20 cncmos: LVT244A F 1013793 Page 5: ------- Component Type / Package CERN Cadence library Supplier -------------------- --------------------- ------------------------- ----------- LVT buffer 74LVT245WM SOIC20 cncmos: 74245 F 1013795 Page 6 (VAT connectors) ----------------------- removed, added pages 2-6 from VAT daughter card) - new pages 6-10 Page 11 (old page 7): --------------------- Component Type / Package CERN Cadence library Supplier -------------------- --------------------- ------------------------- ----------- Multivibrator w/Rst 74LS123 SOIC16 cncmos: 74123 F 1105904 Page 13 (old page 9): --------------------- Removed ALG<18..0> from V6 bank 35 Page 15 (old page 11): --------------------- Component Type / Package CERN Cadence library Supplie -------------------- ---------------------- ------------------------- ----------- VME 5x32 Rt-Ang Plug Harting 02-01-160-2101 cnconnector: CONVME64XP2 4.1 PCB layout check -------------------- - check TTC card connectors - Pin allocation for Spartan-3AN using PlanAhed - clock CLK40 termination - and also CLK1, CLK2, CLK40DES1 and CLK40DES2 - check pin swapping in FPGA - check decoupling capacitors: Page 13: http://www.xilinx.com/support/documentation/user_guides/ug373.pdf (page 13-16) A simple PCB-decoupling network for each Virtex-6 device is listed in Table 2-1 through Table 2-3. Virtex-6 devices require few PCB capacitors because high-frequency ceramic capacitors are already present inside the device package (mounted on the package substrate). Component Type / Package CERN Cadence library Supplier # -------------------- --------------------- ------------------------- ----------- -- 330UF 2.5V KEMET T520V337M2R5ATE025 cnpassive: elcaptan F 1838781 ESR: 0.025ohm 330UF 2.5V KEMET T520C337M2R5ATE015 F 1358519 ESR: 0.015ohm 330UF 2.5V AVX TAJD337K002RNJ F 1658173 ESR: 0.3ohm - Correct errors: 1. If possible, move the TTC connector (IC40) a bit up - away from CF card, 2. Page 3: - On PCB - locate resistors R26/R27 and R30/R31 close to IC19 (end of traces CLK40DES1 and CLK40DES2), 3. Page 6: - On schematics and PCB - add 4 decoupling capacitors 100 NF to VCCAUX, - On schematics - rename signal VCCINT to S3_VCCINT, - On schematics - rename signals VCCAUX to S3_VCCAUX, 4. Page 7: - On schematics - rename signal VCCO to S3_VCCO, 5. Page 8: - On schematics - change bus width SP2V5IO<5..0> to SP2V5IO<4..0>, - On schematics - rename signal VCCO to S3_VCCO, 6. Page 9: - On schematics - change bus width SP2V5IN<11..0> to SP2V5IN<12..0>, - On schematics - rename signals VCCAUX to S3_VCCAUX, - On schematics - rename signal VCCO to S3_VCCO, 7. Page 10: - On schematics - change bus width SP2V5IO<5..0> to SP2V5IO<4..0> and disconnect IC13-F4 from former SP2V5IO<5>, - On schematics - change bus width SP2V5IN<11..0> to SP2V5IN<12..0> and connect SP2V5IN<12> to IC13-F4, - On schematics and PCB - swap signals MPIRQ (E1) and LASRDIS (G5), (LASRDIS is output signal, not input – my mistake - and must be connected to IO pin, and MPIRQ is input signal and can be connected to IP pin), - On schematics - rename signal VCCO to S3_VCCO, 8. Page 12: - On schematics: move resistors R19/R20 (CLK40) to page 7, on PCB - try to locate them closer to Spartan FPGA (IC13-B8), - On schematics - change bus width SP2V5IO<5..0> to SP2V5IO<4..0> and disconnect IC14-E13 from former SP2V5IO<5>, - On schematics - change bus width SP2V5IN<11..0> to SP2V5IN<12..0> and connect SP2V5IN<12> to IC14-E13 - On schematics - move resistors R19/R20 from page 12 to page 7 on schematics, - On schematics and PCB - remove decoupling capacitors from VCCO_25 and VCCO_26 (PCB design guide, attached, page 13-16), - On schematics and PCB – add resistors 82(P2V5) and 130(GND) to CLK1 and CLK2 at the end of traces (near IC14) 9. Page 13: - On schematics - change bus width SP2V5IO<5..0> to SP2V5IO<4..0>, - On schematics - change bus width SP2V5IN<11..0> to SP2V5IN<12..0>, - On schematics and PCB - remove decoupling capacitors from VCCAUX, VCCO and VCCINT (do not mount) - On schematics and PCB – add 1 bulk capacitor to VCCINT 330 µF 2.5V cnpassive: elcaptan T520V337M2R5ATE025, 10. Page 14: - On schematics and PCB - remove decoupling capacitors from VCCO_14 and VCCO_15 , 11. Page 15: - On schematics - rename signal VCCAUX to S3_VCCAUX, - On schematics - rename signal VCCO to S3_VCCO, - On schematics - rename signal VCCINT to S3_VCCINT, 4.2 CMX_ALG VHDL design after layout (pages 12-14) -------------------------------------------------- VHDL top file: cmx_alg.vhd entity CMX_ALG is port ( -- Name PCB signal -- VME-- backplane (46 signals) GEOADDR0: in std_logic; -- GeoAddr0 GEOADDR0 GEOADDR: in std_logic_vector(6 downto 4); -- GeoAddr GEOADDR V6_VA: in std_logic_vector(23 downto 1); -- Address bus V6_VA V6_VW_L: in std_logic; -- VME Write V6_VW_L V6_BDS: in std_logic; -- (Data ack) V6_BDS V6_BS_L: in std_logic; -- Board select V6_BS_L V6_VD: inout std_logic_vector(15 downto 0); -- Data bus V6_VD -- TTCDec card (2 signals) CLK1: in std_logic; -- CLK40DES1 CLK1 CLK2: in std_logic: -- CLK40DES2 CLK2 V6_L1A: in std_logic; -- TTC L1 Accept V6_L1A V6_BCR: in std_logic; -- TTC BC Reset V6_BCR -- CMX_VAT FPGA (19 signals) BRDRST_L: in std_logic; -- Board reset BRDRST_L DLLRST_L: in std_logic; -- DLL reset DLLRST_L PLYBKEN: in std_logic; -- Playback en PLYBKEN CLRPE: in std_logic; -- ? CLRPE SPCORE: in std_logic_vector(2 downto 1); -- ? SPCORE SPSERV: in std_logic_vector(1 downto 0); -- ? SPSERV CMMPECNZ: out std_logic; -- CMM PEC NZERO CMMPECNZ CMMLDLL: out std_logic; -- CMM DLL lock CMMDLL CMMSLDLL: out std_logic; -- CMMS DLL lock CMMSDLL CMMDFEF: out std_logic; -- CMM DAQ FEF CMMDFEF CMMSDFEF: out std_logic; -- CMMS DAQ FEF CMMSDFEF CMMRFEF: out std_logic; -- CMM ROI FEF CMMRFEF CMMSRFEF: out std_logic; -- CMMS ROI FEF CMMSRFEF CMMDFFF: out std_logic; -- CMM DAQ FFF CMMDFFF CMMSDFFF: out std_logic; -- CMMS DAQ FFF CMMSDFFF CMMRFFF: out std_logic; -- CMM ROI FFF CMMRFFF CMMSRFFF: out std_logic; -- CMMS ROI FFF CMMSRFFF -- CMX_VAT FPGA spare IO (18 signals) SP2V5IN: out std_logic_vector(12 downto 0); -- VAT spares IN SP2V5IN SP2V5IO: inout std_logic_vector(4 downto 0); -- VAT spares IO SP2V5IO -- GLink (6 signals) GLDRST_L: in std_logic; -- GL DAQ reset GLDRST_L GLRRST_L: in std_logic; -- GL ROI reset GLRRST_L LASDDIS: in std_logic; -- Laser DAQ dis LASDDIS LAsRDIS: in std_logic; -- Laser ROI dis LASRDIS GLDRDY: out std_logic; -- GL DAQ ready GLDRDY GLRRDY: out std_logic; -- GL ROI ready GLRRDY -- Jumpers (10 signals) ST: inout std_logic_vector(5 downto 1); -- jumpers IO ST TS: inout std_logic_vector(5 downto 1); -- jumpers IO TS -- CMX board (1 signal) V6_CLK: in std_logic -- V6_CLK v6_CLK ); end CMX_ALG; 5. Standalone tests =================== 5.1 6U VME crate preparation (Bruce, Markus, Murrough -> Seth) -------------------------------------------------------------- Bruce: There should be information about how Murrough has sets up a standard environment a la L1Calo T/DAQ at: https://twiki.cern.ch/twiki/bin/viewauth/Atlas/LevelOneCaloOnlineSoftware That would give you, at least, hdmc which with the help of a cmm-like "parts" file you will be able to access your 6U board. Then more (thank hdmc) if you need to build a bigger test system. - 6U VME crate + TTC modules from Bld.104 to Bld.32 - Power cable accembled, crate powered - 6U VME SBC (CONCURRENT - VP315/022-96U) http://www.cct.co.uk/sheets/VP/datasheet/vp31502x-u.pdf - TTC modules (TTCvi, TTCex and LTP) to emulate the CTP (L1Accept) and the TTC system. - TTCvi: https://edms.cern.ch/file/110746/2/writeup_mk2.pdf - TTCvx: https://edms.cern.ch/file/292649/1/manual.pdf) - LTP: https://edms.cern.ch/document/374560 - 15.06.2012 - SBC registration, network address, booting etc. (Markus + ATLAS sysadmins) - name:SBCCMX00 outlet:0032-SB-0003/05 OS:LINUX/SLC5 - direct SBC access from my PC: via PuTTY - VME test extension card for 6U VME crate - borrowed from Markus Jooos - Oscilloscope, multimeter, soldering tool, toolbox, ... . setup L1Calo environement on the SBC and the Linux PC, try to access TTC modules from VME - Seth 5.2 6U VME test card preparation -------------------------------- - XILINX Platform Cable USB II http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm - request sent to Schneider, Romana (Avnet) - quote: $225 -> asked MSU - received - 2GB Compact Flash card - ordered 2 4GB CF cards from Distrelec (MAG 4982814) - received - 6U VME test board powering from power supply (PS) - power supply Dr.K.Witmer IC 35/8 - set to 5V0 output - remove fuses (FH1=3A, FH2=1A, FH3=5A, FH4=5A, FH5=2A) - put jumpers ST68, ST30(3-2, XC3S400AN-4FTG256C Bank 2: VCCO_2=3V3) - J2 VME connector with 5V0 and GND pins connected to power supply - powered the board from PS, check the output voltages of PHT05050 - all OK - insert all fuses and power the board from PS - no smoke! - check the output voltages of PHT05050 with the multimeter - all OK - total power consumption from PS - 5V/0.75A = 3.75W -> look at the output voltages with the oscilloscope - After power-on LD12 (AST, green) and LD11 (AER, red) are on --> No Ext. Pull-up on STATLED_L and ERRLRD_L !!! forgot :-( in CMM - 1K to 3V3 -> fixed - jumpers setting - put clock selection jumper (ST65) -> board XTL clock -> LED LD9 (CLK40) is ON - JTAG chain (put J1, J2, J3, J4, J10 -> Spartan3AN only) Primary JTAG chain: JTAG connecor -> buffer -> Spartan-3AN -> System ACE(+Virtex6) Jumpers are provided to exclude from the chain Spartan-3AN OR System ACE (3V3) 3AN+ACE 3AN only ACE only J1(ST17) J6(ST22) + + + - - + J2(ST18) J7(ST23) + + + - - + J3(ST19) J8(ST24) + + + - - + J4(ST20) J9(ST25) + + + - - + J5(ST21) J10(ST26) - - - + + - 5.3 Spartan3AN configuration using JTAG and iMPACT software ----------------------------------------------------------- JTAG chain (put J1, J2, J3, J4 + J10 -> Spartan3AN only) Test design for Spartan-3AN (XC3S400AN-4FTG256C) - to light the LED "DONE" (LD5) and the LEDs LD1-LD4 - create test design CMX_VAT_TEST - File name: cmx_vat_test.vhd C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_vat_test\cmx_vat_test_sources\cmx_vat_test.vhd - create new XILINX project: cmx_vat_test - add source file cmx_vat_test.vhd to the project and implement the design - create cmx_vat_test.ucf constraint file: Project > New Source > Implementation Constraints File. - after synthesis create pin locations and IO standards in cmx_vat_test.ucf file by Plan Ahead - Generate Programming File cmx_vat_test.bit - Configuration options: Set the ConfigRate option for 33 MHz (default - 25) - Startup options: keep CCLK; check the Drive Done Pin High - ? (is it necessary???) - connect Platform Cable USB II to portable and 6U VME test card - Programming a Spartan-3AN FPGA Using JTAG: - Configure Target Device -> open iMPACT - select Boundary-Scan and add device - Program Flash and Load FPGA - Switch OFF the board power and switch ON again - FPGA is programmed from internal flash! - OK for few LED values! 5.4 Virtex6 configuration using JTAG and iMPACT software -------------------------------------------------------- Test design for Virtex6 (XC6VLX75T-1FFG784C) - to drive the pin T26 (TS<1>) '0' and '1' - create test design CMX_ALG_TEST - File name: cmx_alg_test.vhd C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test\cmx_alg_test_sources\cmx_alg_test.vhd use pin T26 (TS<1>) of Virtex6 as output, for the test call T26 as "DONE" and set to "HIGH" - create new XILINX project: cmx_alg_test - add source file cmx_alg_test.vhd to the project and implement the design - create cmx_alg_test.ucf constraint file: Project > New Source > Implementation Constraints File. - after synthesis create pin locations and IO standards in cmx_alg_test.ucf file by Plan Ahead Users Constrains > I/O Pin Planning (Plan Ahesd) - Post Synthesis "DONE" - pin T26 (TS<1>) Bank 14 --> save, result in cmx_alg_test.ucf file: # PlanAhead Generated physical constraints NET "DONE" LOC = T26; - Generate Programming File cmx_alg_test.bit - Configuration options: Set the ConfigRate option for 2 MHz (default - 2)! 04.10.12 - set to 33 MHz From SystemACE_DS.pdf: Test JTAG Interface (TSTJTAG) - This interface can also be used to program the target FPGA chain on the CFGJTAG port, using Xilinx or third-party JTAG programming tools. The maximum clock operating frequency is either 16.7 MHz or the maximum JTAG TCK clock speed dictated by the devices in the JTAG chain and/or the board design. The lowest of these values should be used. - Startup options: keep CCLK; check the Drive Done Pin High - ? (is it necessary???) Configuration from System ACE TSTJTAG port (connected to iMPACT) JTAFG chain (put J6, J7, J8, J9 + J5 -> ACE only) - connect Platform Cable USB II to portable and 6U VME test card - Programming Virtex6 FPGA via iMPACT Using JTAG: - Configure Target Device -> open iMPACT - select Boundary-Scan - Cable Setup... (Platform Cable USB/II) - Initilize Chain - Assigne configuration files (YES): XCCACE - bypass; Virtex - C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test -> cmx_alg_test.bit - Attach SPI or BPI PROM -> NO - Click on Virtex6 - Program -> program succeeded -> pin T26 is LOW ???? -> TS label on the board for TS<5..1> is in fact for ST -> Change "DONE" to pin M28 (ST<1>) - now works! 5.5 Chain configuration (Spartan + Virtex6) via JTAG ---------------------------------------------------- JTAG chain (put J1, J2, J3, J4, J6, J7, J8, J9 -> Spartan3AN + ACE(+Virtex6) In file browser - go to C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_vat_test_impact - Run stanalone iMPACT, automatically create and save project - Configure devices uses Boundary-Scan (JTAG) -> Automatically connect to a cable and identify Boundary-Scan chain - Continue and assign configuration files: -> Spartan-3AN (XC3S400AN) C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_vat_test\cmx_vat_test.bit -> XCCACE - bypass -> Virtex6 (XC6VLX75T) C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test\cmx_alg_test.bit - Attach SPI or BPI PROM -> NO - Devices programming properties - File - Save Project As... C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_vat_test_impact\cmx_alg_vat_test_impact.ipf --> Program individual devices - Exit 5.6 Virtex6 configuration on power-on from CF card by System ACE ---------------------------------------------------------------- Test design - in Spartan-3AN cmx_vat_test.vhd added signals: -- XILINX System ACE CF controller (35 signals) ALLDONE: out std_logic; -- All conf done ALLDONE -- CMX_ALG FPGA (21 signal) CMMDONE: in std_logic; -- CMM done CMMDONE in cmx_vat_test.ucf added: NET "CMMDONE" LOC = B15; NET "ALLDONE" LOC = N2; remove signals CLK40 and PONRST from cmx_vat_test.vhd and cmx_vat_test.ucf add ALLDONE <= CMMDONE; Start XILINX ISE, open project cmx_vat_test and generate programming file Run stanalone iMPACT, Program Flash and load Spartan-3AN FPGA, program Virtex6 --> ALLDONE LED (LD6) is ON! Prepare CF card - CF card programming via IMPACT and CF card writer - in XILINX ISE open project cmx_alg_test.vhd - Generate Programming File - Manage Configuration Project (iMPACT) - select System ACE: -> Prepare System ACE files: -> Novice -> System ACE CF size: -> Generic -> System ACE Name and Location: Name->alg (collection name); Location-> C:/My Docs/Work/MSU/Upgrade/CMX firmware/cmx_test/cmx_alg_test -> System ACE Configuration address and Design: Configuration address 0 (test) -> Finish -> Now start assigning device file to Config Address 0 -> cmx_alg_test.bit -> Would you like to add another divice file to Config Address 0 -> NO -> Available operations -> Generate File... -> OK Creating Ace File C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test/alg/test/test.ace... - Connect SONY USB multicard reader/writer MRW62E to PC and insert CF card (Kingston, 8GB) -> Copy from C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test\ to the CF card (Disk I:) file: xilinx.sys and directory: alg -> On CF card (max 2GB ?) -> File: xilinx.sys + Directory: alg File: xilinx.sys #Automatically generated. PLEASE DO NOT MODIFY. dir = alg; cfgaddr0 = test; Directory: alg -> file: xilinx.sys + directory: test (with file test.ace) -> Remove CF card from reader/writer and insert into the CF socket on the 6U VME test card -> power ON the card --->>> NO FPGA programming -> Copy only test.ace file to the CF card, power ON the 6U board --->>> NO FPGA programming (programming via JTAG still works) -> 8GB CF card has FAT32 file system -> need FAT16 or FAT12 -> sectors-per-cluster size greater than 1 (UnitSize greater than 512)(one sector - 512 bytes) -> one reserved sector in the Partition Boot Record. -> on WindowsXP formatting utility (such as mkdosfs, available from http://www1.mager.org/mkdosfs) must be used. -> Use 2GB CF card from BLT (alredy formatted and worked in BLT) - same result... -> format 4GB CF card on WindowsXP using "mkdosfs" from http://www1.mager.org/mkdosfs/mkdosfs/mkdosfs.exe C:\Documents and Settings\ermoline>C:\mkdosfs -v -F 16 -R 1 E: mkdosfs 2.11 (12 Mar 2005) Win32 port by Jens-Uwe Mager \\.\E: has 255 heads and 63 sectors per track, logical sector size is 512, using 0xf8 media descriptor, with 7798832 sectors; file system has 2 16-bit FATs and 128 sectors per cluster. FAT size is 238 sectors, and provides 60924 clusters. Root directory contains 512 slots. Volume ID is 5037cc39, no volume label. -> Copy from C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test\ to the CF card xilinx.sys and alg; -> power ON the card --->>> NO FPGA programming - Check the hardware connection for System ACE - POR_BYPASS set to '1', -> set it to '0' (Built-in POR circuit is used to reset the device) - RESET* pin of the System ACE CF Controller (pin 33) -> set in cmx_vat_test.vhd output ACERST_L <= '1'; and in cmx_vat_test.ucf NET "ACERST_L" LOC = P2; DRIVER <= "0000"; -> Program Flash and load Spartan-3AN FPGA, OFF and On the power -> after some time red AER LED (LD11) is ON -> an error occurred Table 1: System ACE CF Controller Status Indicators STATLED • When on, the Status LED indicates that configuration is DONE. • When blinking, this LED indicates that configuration is still in progress. • When off this LED indicates that configuration is in an IDLE state. ERRLED • When on, the ERROR LED indicates that an error occurred. • When blinking, this LED indicates that no CompactFlash device was found when the CompactFlash for the Configuration JTAG interface was enabled. • When off, this LED indicates that no errors are detected. -> Remove the CF card and ON the board - AER LED - CFGMODEPIN pin of the System ACE CF Controller (pin 89): Configuration mode pin: • When 0, this pin instructs the System ACE CF controller to start the configuration process when the CFGSTART bit is set in the CONTROLREG register in the MPU interface. • When 1, this pin instructs the System ACE CF controller to start the configuration process immediately following reset. -> set in cmx_vat_test.vhd CFGADDR <= "000"; and CFGMODE <= '1'; and in cmx_vat_test.ucf pin locations DRIVER <= "0001"; - Check the CF card header layout - problem with CF header: On the CADENCE library component used in schematics header pins are numbered: 50 49 48 47 … 4 3 2 1 On the drawing of header: 50 25 49 24 … 27 2 26 1 Wrong pin numbering of the CADENCE library component COMPACTFLASH_SOCKET50P) -> need an adapter Compact Flash Socket Molex 55358-5029 CompactFlash Card Receptacle Molex 67799-0007 (or Molex 67799-0004) available from Mouser http://www.molex.com/webdocs/datasheets/pdf/en-us/0677990007_MEMORY_CARD_SOCKET.pdf http://www.molex.com/molex/products/listview.jsp?query=67799&path=cHome%23%23-1%23%23-1%7E%7EncMEMORYCARDSOCKET %23%230%23%234&offset=0&autoNav=1&sType=s&filter=&fs=&channel=Products -> William to make an adapter -> got it on 27.09.12 -> check CF card connections - OK - Configuration from CF card: - power ON the 6U VME card without CF card -> ERRLED blinking - Format 2GB CF card on WindowsXP using "mkdosfs", wrote xilinx.sys and alg directory on the CF card -> power ON the 6U VME card --->>> NO FPGA programming, ERRLED is immediately ON! - Possible errors: - incorrect CF card formatting and writing System ACE files on the CF card? -> test 2GB CG card with BLT -> BLT configure OK (STATLED blinking few times then ON) -> more tests with BLT: 2GB CF card (EMTEC - E) and 4GB CF card (Kingston - K) - format both CF on on WindowsXP using "mkdosfs" C:\>mkdosfs E: - Copy xilinx.sys and blt to both CF cards; Works with E, not with K - to be uinvestigated!!! - incorrect System ACE files? -> look at BLT project - Generate Programming File -> Process Properties -> set same as in BLT -> (unchecked Enable Internal Done Pipe and Drive Done Pin High in Startup Options) -> same results - System ACE control from Spartan-3AN: CFGADDR, CFGMODE, ACERST_L; from Virtex-6: CFGINIT_L -> on CMM: from CPLD (U70) XCR3384XL-10FT256C CPLD (ACE) -> on BLT: from XC2C128_TQ144 (CoolRunner-II CPLD) -> CFGINIT_L: Configuration JTAG INIT pin (active LOW); this pin is used to sense when all devices are ready to be (pin 78) programmed (i.e., INIT = 1 indicates target device(s) are ready to receive configuration data and INIT = 0 indicates that the target device(s) are being cleared and are not ready to be configured) INIT_B_0: From power-on reset or PROGRAM_B reset, INIT_B is driven Low, indicating that the FPGA (pin M6) is initializing (clearing) its configuration memory. Before the Mode pins are sampled, INIT_B is an open-drain, active-Low input and can be held Low to delay configuration. After the Mode pins are sampled, the INIT_B output indicates if a CRC error occurred during configuration or a readback CRC error occurred after configuration (when enabled): 0 = CRC or IDCODE error (DONE is Low) or Readback CRC Error (DONE is High and Readback CRC is enabled). 1 = No CRC error, housecleaning is complete (needs an external pull-up resistor). When the SEU detection function is enabled, INIT_B is optionally driven Low when a readback CRC error is detected. -> Try to keep System ACE pin 78 (CFGINIT_L) low during power ON, then release -> no effect! -> incorrect timing between Spartan-3AN and System ACE? ? Connect pin T15 (DONE) of Spartan-3AN to CFGINIT_L of System ACE? - Check ACE signals: - ACE clock? source: QZ2 (20.00 MHz) powered from 3V3, pin 3 ACECLK 3V3 -> change power to 2V5!!! - POR_BYPASS (IC44-108) set to '0' (ST66 inserted), Built-in POR circuit is used to reset the device -> if POR_BYPASS set to '1', ERRLED is still ON; pressing PONRST -> ERRLED goes OFF, after PONRST release -> ON - set in cmx_vat_test.vhd: MPWE_L <= '1'; MPCE_L <= '1'; MPOE_L <= '1'; CFGADDR <= "000"; -- use System ACE Configuration address 0 (test) CFGMODE <= '1'; ALLDONE <= CMMDONE; ACERST_L <= '1'; - cut CFGADDR and CFGMODE from Spartan-3AN: (in Spartan set CFGADDR <= "111" CFGMODE <= '0'; - to check on the board cut) CFGADDR: Int. Pull-down (-> "000"); CFGMODEPIN: Int. Pull-up (-> '1'); - cut ACERST_L, MPWE_L, MPCE_L (Int. Pull-up) -> '1' - Again CF card formatting: - Use 2GB CF card from BLT and format on WindowsXP using "mkdosfs" C:\>mkdosfs -v E: - write BLt rev0.ace file to CF card an test BLT configuration -> OK - format again, write test.ace file to CF card an test 6UVME configuration -> NO!!! - format with C:\>mkdosfs -v -F 16 -R 1 E: -> NO!!! BLT comparison study: on test card: - signal CF card - ACE: CE1* 7 - 119 square pulses 1 us pulses, soon stop REG* 44 - 3 '1' '1' CE2* 32 - 138 square pulses 1 us pulses, soon stop WE* 36 - 131 3 pulses in the middle 3 pulses in the middle WAIT* 42 - 140 '1' '1' OE* 9 - 123 square pulses 1 us pulses, soon stop CD1* 26 - 103 '0' - check! short pulse initially CD2* 25 - 13 short pulse initially short pulse initially TSTTDI 102 '1' TSTTCK 101 '1' TSTTMS 98 '1' TSTTDO 97 activity CFGTDI 81 activity no activity CFGTCK 80 pulses no pulses CFGTMS 85 activity '1' ??? CFGTDO 82 activity no activity CFGADDR<2..0> = "000" CFGMODEPIN = '1' CFGINIT_L = low then high POR_BYPASS = '0' POR_RESET = '0' --> ACE starts to read the CF card, but not start the CFG_JTAG cut POR_BYPASS from R94 and PONRST Table 12: ERRORREG Register Bit Descriptions 9 CFGINITERR 1 means that the CFGINIT pin did not go HIGH within 500 ms of the start of configuration ??? XILINX SystemACE chip replacement, check for shorts - GND clip on adapter connector!!! (pin 2 grounded!) Remove clip --> Works!!!!!!!!!!!!!!!!!!!!!!!! Restore connections ?: --> may be left cutted CFGADDR: 86, 87, 88 Int. Pull-down (-> "000"); CFGMODEPIN: 89 Int. Pull-up (-> '1'); start the configuration immediately after reset --> need to be restored to control SystemACE chip from Spartan FRGA ACERST_L: 33 Int. Pull-up (-> '1'); from Spartan MPWE_L: 76 Int. Pull-up (-> '1'); from Spartan MPCE_L: 42 Int. Pull-up (-> '1'); from Spartan 5.7 CMX power consumption ------------------------- CMX current limit on 5V Prototype Processor Backplane, Version 1.1, May 2, 2005 2.4.8 Power distribution The processor crates supply regulated +5V and +3.3V power to high-current bus bars, which in turn provide power to each module in the crate. Other voltages needed by a module may be derived locally from the +5V supply. Each module is supplied with three high-current power pins that carry +5V, +3.3V and ground return from the local bus bars. Each backplane power pin is rated at up to 40A, providing a substantial safety margin for all modules in the system. 3.6 Power distribution The prototype processor crates distributed 5V and 3.3V power to all modules in the crate using 1 cm2 horizontal copper bus bars mounted by insulating holders to the sides of the card cage. The power pins in each slot were connected to the bus bars using short AWG8 cables. This configuration provided excellent current carrying capabilities, but make backplane removal or power pin replacement extremely difficult. A new power distribution scheme (Section 2.4.8) has been adopted for the production crates. The bus bars have even larger cross sections, and are mounted to the backplane support ribs (Appendix I). The wires between the bus bars and the power pins are thinner (2.5 mm2), but can be made less than 5cm long. The resistance of these connections at high currents (up to 24A) was measured to be ~1.3 mO, which will result in minimal power drops between the bus bars and the modules (less than 25 mV on the CPM). Voltage fluctuations at the module power inputs due to changing load conditions should be negligible. Appendix E: Design checklist for manufacturer Connectors A power connector with three DIN cavities (ERNI 140-147 or equivalent) at the bottom of each position provides +5V, 3.3V and power ground, with a capacity of up to 40A per pin. The power pins are connected to bus bars mounted behind the backplane. Connector 9 2 +3.3V 6 Power GND 10 +5.0V VME Mount Module, Version: 2.4, 24 November 2005 3.1.10 Power Requirements The 6U SBC requires +5V. Onboard terminations and buffers require +3.3V. In addition, +12V and -12V may also be needed by PMC cards on the 6U SBC. +5V supply is directly available from 9U backplane. The +5V power supply to the 6U SBC should stay within the range of 4.875V to 5.25V. Low drop power distribution, preferably solid PCB planes, should be used. No fuse should be used in this power distribution path. A linear regulator is used to generate +3.3V. Two DC-DC converters are used to generate +12V and -12V. At present no DC-DC converters will be assembled on the VMM since +/-12 V are not currently used. The total current required from +5V supply is estimated to be ~ 8A. Common Merger Module, Version 1.8, 18-Jul-2008 5.6 Power Requirements The crate backplane provides +3.3V and +5V supplies. However, the 3.3V supply is reserved exclusively for power-sensitive components such as the LVDS transceivers, and is not used on the CMM. Supplies of +1.8V, +2.5V and +3.3V for other devices are generated on-board from the +5V supply. The total current drawn at +5V may be up to 10A. Cluster Processor Module, Version: 2.03, 18 October 2006 3.8.3 Power supplies All of the Xilinx Virtex-E family of devices require a 1.8V supply for the core logic. From a conservative estimate of the power requirements of the Serialisers and CP chips this leads to rather high currents at this low voltage. The FPGA I/O drivers and backplane terminations will be powered from 2.5Vand so require a large amount of power. The LVDS receivers will be supplied separately from a dedicated “quiet” supply at 3.3V to avoid noise problems leading to serial data errors, which have been experienced in tests. Some of the on-board logic also require 3.3V. The VME interface for the prototype is powered from 3.3V using 5V tolerant parts. The G-links transmitters are also supplied at 5V and are quite power-hungry, but since there are only two per CPM, this is not a great contribution to the overall module power consumption. The detailed power requirements of the principal devices on the CPM are listed below in Table 7: There are only three high-current dedicated power pins available from the backplane. One of these is GND return, one will carry the 5V ‘mains’, and one will be the dedicated quiet 3.3V supply for the LVDS receivers. The AMP power connector is rated at 40A per pin, but, somewhat strangely, the rightangle connection onto the module is only rated to 20A. Three converters are used, for 1.8V, 2.5V and 3.3V. Filter chokes and Re-settable fuses will be used at the supply inputs to the module. The inputs to the onboard supply voltage converters will have additional filtering to prevent noise being generated back onto the 5V crate supply. Care has been taken to avoid over-stressing the Power Modules from excessive ringing spikes on the input supply. The total (non-LVDS) power required from the 5V supply is ~56 W, which means a current of 11 A if assuming perfect efficiency in the conversion process, or ~70 W if assuming a conservative conversion efficiency of 80%. This is within the power connector maximum current rating, although the GND return will be approaching this limit when the current contribution from the LVDS supply and the conversion inefficiencies are taken into account. Power connections are placed at the bottom edge of the module in order not to interrupt the module hit-count signals, which run diagonally across the backplane. Jet / Energy Processor Module, Version 1.2d (post PRR), 15 February 2008 3.8 Signal levels and supply voltages The JEM is a mixed signal level environment. Particular consideration of signal level compatibility and system noise issues is required so as to make the system work reliably. Differential signalling is employed for the trigger input signals (LVDS, 400Mb/s), TTC input signal distribution (3.3V PECL, 160 Mb/s) and CAN (100kb/s). All differential signals are routed on differential matched impedance micro strip lines only. Single ended signals are CMOS 5V (CAN microcontroller), 3.3V (JTAG, VME, readout links, deserialisers, CPLDs and buffers), 2.5V (merger lines) and 1.5V (FIO, processor-to-processor). FIO signals are sensed using CMOS or HSTL thresholds. To that end an external reference voltage of 0.75V is provided to the jet processor. This voltage is generated on the module by resistive division of the operating voltage of 1.5V. 5V CAN logic levels require the use of level shifters on all signal lines, including the SMB bus. Input lines into the CAN controller are protected by series resistors. The analogue and PLL VCC pins of the LVDS de-serialisers are supplied from the 3.3V high current connector on the rear edge of the module. The 5V high current pin directly supplies the CAN circuitry only. The supply voltages of 3.3V and below are generated from +5V by step-down regulators. A separate linear regulator supplies the operating voltage (3.3V) to the VME buffers. All FPGA supply voltages are generated such that the startup ramp on power-on is within the specifications for Virtex-II (200µs – 10ms). Datel modules with 7ms maximum ramp have been chosen. They are linked together in a chain connecting status and control lines, such that the Xilinx recommended power-up sequence is generated. This reduces inrush currents to a minimum. Maximum current at power-up has been measured to be 8 A, during configuration the current is below 5A. In full operation with stress patterns delivered to all LVDS inputs, a JEM consumes less than 9A at 5V plus 3A at 3.3V. Total power dissipation is below 60W. Timing Control Module, Version 1.0.5, 12-September-2006 5.6 Power Requirements All power required by the module is derived from the +5V supply. The 3.3V supply on TCM-CP/JEP backplanes is reserved for LVDS signalling devices, so an internal regulator is used to generate the 3.3v supply. The total current drawn at +5V may be up to 5A. L1Calo Modules power consumption in the crate from 5V power supply: ------------------------------------------------------------------- VMM CMM CPM*14 CMM TCM Total: 8 10 14*14 10 5 229 VMM CMM JEM*16 CMM TCM Total: 8 10 9*16 10 5 177 L1Calo Wiener Power-Supply 9U (+3.3V/200A, +5V/300A, +-12V/10A) CMM connector AMP 100752-1 http://www.te.com/catalog/pn/en/100752-1 >> Hello Sam, >> We've started to look into CMX powering - so, would like your comments/advice. >> The CPM/JEM crates use water-cooled power supplies with +5V/300A. >> Looking into L1Calo modules description I compiled a list of current requirements for the CPM/JEM crates: >> L1Calo Modules power consumption in the crate from 5V power supply: >> ------------------------------------------------------------------- >> VMM CMM CPM*14 CMM TCM Total: >> 8 10 14*14 10 5 229 >> VMM CMM JEM*16 CMM TCM Total: >> 8 10 9*16 10 5 177 >> Therefore, from the papers it looks like there is some spare current capacity available. >> From your backplane spec, the power pin is rated for 40A (Richard >> mentioned 20A limit for the right-angle connector on the module - AMP 100752-1 on CMM). >> So, it looks like we can draw 20A from the 5V power supply? > > Yes, you can safely draw 20 amps from the +5v supply. If Richard's > figure of 20A on the PCB side is correct, then this is the limiting > factor. The limit on the backplane side is higher than this (minimum > 25A, maybe up to 40. I would have to go back and reread the specs for > the exact parts used on the production backplane) > > OK, if you can figure out the current limit on the backplane side it will be useful. > In the spec for the AMP 100752-1 used on CMM, which I found on the web: http://www.te.com/catalog/pn/en/100752-1 > I didn't find a current rating... May be Richard still keep the spec where 20A limit is specified? After a little digging, I managed to find the original drawings for the parts used in the production backplane. The +5V and +3V are AMP/Tyco part 100069-1. This has a rated current of 40A. We weren't able to get the first-make/break-last ground pin from AMP/Tyco at a reasonable cost, so instead I special-ordered the equivalent part from FCI (RM12PIE91ERP). The part is no longer in the FCI catalog (Even then they had to do a special production run with MOQ of 1000 pieces…), but I still have the product drawing that the FCI representative sent me. The version used on the backplane is for AWG12 wire, and is thus rated at 20A. So the rated current limit for the board is set by the 20A ground-return pin. Sam 6U VME test card power consumption measurements from power supply ----------------------------------------------------------------- PTH05050W (5V Input Voltage, 0.8V to 3.6V Output Voltage Adjust, up to 6A Output Current) http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=34821 http://www.ti.com/analog/docs/refdesignovw.tsp?familyId=64&contentType=2&genContentId=65246 Power Requirements for XC3S400A: Pin Name Voltage(V) Imax*(mA) - estimation Ireal(mA) Core Vccint 1V2 600 (0.72W) disconnect FH2 and measure current on S3_VCCINT I/O Vccaux 3V3 150 (0.5W) disconnect ST68 and measure current on S3_VCCAUX I/O Vcco 3V3/2V5 4000 (10W) 4 banks ~1.0A/bank disconnect FH1 and measure current on S3_VCCO (bank 2 - use ST30 to measure 3V3 consumption) Power Requirements for XC6VLX75T: Pin Name Voltage(V) Imax* Ireal(mA) Core Vccint 1V0 3700 (3.7W) disconnect FH4 and measure current on P1V0 I/O Vcco 2V5 3000 (7.5W) disconnect FH3 and measure current on P2V5 I/O Vccaux 2V5 1500 (3.7W) for both - Vcco and Vccaux Power requirements estimation: 3V3: = 1.00 A 3W0 PTH05050W (RSET = 698 O Vo = 3.3 V) 2V5: = 6.80 A 17W0 PTH05050W (RSET = 2.21 kO Vo = 2.5 V) - 4.5A for Virtex6 PTH05050W (RSET = 2.21 kO Vo = 2.5 V) - 2.3A for VAT card VCCO (3.0A for XC3S400A) 1V2: = 0.60 A 0W7 PTH05050W (RSET = 17.4 kO Vo = 1.2 V) or (RSET = 5.49 kO Vo = 1.8 V) - for VAT card VCCINT 1V0: = 3.70 A 3W7 PTH05050W (RSET = 36.5 kO Vo = 1.0 V) - for Virtex6 core Vccint Total: 24W4 (~4.9A at 5V0) -> Initial power consumption from PS - 5V0/0.75A = 3.75W (FPGAs are not configured, no CF card) Loading Spartan-3AN with compiled Ian’s design doesn’t increase the power consumption. Mesurement of 6U test card power consumption in the 6U VME crate ---------------------------------------------------------------- Use fan tray current measurements before and aftre 6U VME test mudule insertion 6. VME tests ============ 6.1 Preparation for the VME tests --------------------------------- Get optical cable -> 1.5 m TTC optical cable ordered -> received Get TTXDec card -> asked Bruce -> got 2 cards (20DACTTDE00001 and 20DACTTDE00014) Study Spartan-3AN CMX_VAT VHDL design: VHDL top file: cmx_vat.vhd 11.09.12: Implement design: No errors, 117 warnings (5 new), all signals routed, all constrains met, <10% utilisation Understanding warnings: Delays in L1Calo modules: VMM: DS* (U8-6, L01) 30 ns CMM: DS0_INT* (DL2-5, SB31) 5ns VMEDTACK* (DL1-5, SB15) 5ns Jumpers: VME delays: ----------- VMEDS (ST54-ST50) - VME address buffer : (insert ST54(TAP1) - 5 ns) 11/02/13 - change to ST50(TAP5) - 25 ns VMEDS_L (ST59-ST55) - VAT FPGA : insert ST59(TAP1) - 5 ns DTACK* (ST60-ST64) - from BRDDS : insert ST60(TAP1) - 5 ns MODID<11..0>: ------------- 2-bytes VME registers (addresses decoded by CMM_VMEdecoder): ByteAddress(hex) RegisterType RegisterName Size(bytes) Description 00000 RO ModuleIdA 2 Module ID Register A 00002 RO ModuleIdB 2 Module ID Register B Module ID Register A All bit fields are outputs from card Bit DescriptiveName SignalName 0-15 ModuleID RALNo - unique 8-bit number for each module type, set to 2417 for the CMM in FW Module ID Register B All bit fields are outputs from card Bit DescriptiveName SignalName 0-7 ModuleSerialNumber SerNo - unique 8-bit number for each module, starting at 1 and set by solder jumpers 8-11 HardwareRevisionNumber RevNo - four-bit revision number starting at 1 and set by solder jumpers 12-15 null - MODID<15..12> are not used ? MODID<11..0> set to <1001_1010_0101> (09a5) - inserted jumper = '0' GEOADDR<6..0>: -------------- Processor Backplane: Three bussed address lines GEOADDR<6..4> with switches are needed to identify the system (CP/JEP) and crate number (up to 4 crates). Each module requires up to four additional pins GEOADDR<3..0> to uniquely identify its position within the crate. The geographic address pins are specified as active high. CMM: Crate GEOADD(6:4) GEOADD(0) Module Function 0-2 111,110,101 0 (Left) τ Crate-CMM 3 100 0 τ System-CMM 0-2 111,110,101 1 (Right) e/γ Crate-CMM 3 100 1 e/γ System-CMM 4 011 0 Energy Crate-CMM 4 011 1 Jet Crate-CMM 5 010 0 Energy System-CMM 5 010 1 Jet System-CMM 6-7 001,000 Any Reserved The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x00700000-0x0077FFFE 20 CMM1 0x00780000-0x007FFFFE GEOADD(6:4) and GEOADD(0) set to <111><1> -> e/γ Crate-CMM CMM1 in slot 20 0x780000-0x7FFFFE CANBus Interface: ----------------- Port 7 of the microcontroller is connected to the geographical address input pins from the backplane (GEOADDR<6..0>). From this input, delays are calculated to prevent two microcontrollers on the same bus transmitting at the same time, thus preventing bus contention. 6.2 Connecting to SBC in the 6U VME crate in the test rig: ---------------------------------------------------------- Use PuTTY to connect to sbccmx00.cern.ch (source LVL1/l1calo/scripts/login/.lxplus_bashrc - old, now use below:) source /afs/cern.ch/work/l/laughron/public/l1calo/scripts/login/.lxplus_bashrc Test card address: 0x780000-0x7FFFFE Test board Registers: vme_interface ------------- 2-bytes VME registers (addresses decoded by CMM_VMEdecoder): 00000 RO ModuleIdA Module ID Register A -> ReadOnly_Reg (RALNo set to 2417 in FW) 00002 RO ModuleIdB Module ID Register B -> ReadOnly_Reg (0fff) 00004 RW ControlModeReg Control Mode Register -> ControlGeo? (001e) 00006 RW ControlPulseReg Control Pulse Register -> gen_rlalgo + pulse_reg_a? ??? - copy of 04? 00008 RO StatusReg Status Register -> ReadOnly_Reg (0f11) 0000A RO FifoStatusReg FIFO Status Register -> ReadOnly_Reg (00ff) 00054 RO I2CId I2C FPFA irmware version -> ReadOnly_Reg 00056 RO VmeId VME CPLD firmware version -> ReadOnly_Reg ( 00058 RO SystemAceVMEIf System Ace VME Interface -> not implemented in vme_interface CPLD, implemented in cmm_ace_interface 0005C RW CanAccessA CAN Access Register A -> not implemented in vme_interface CPLD 0005E RW CanAccessB CAN Access Register B -> RW_Reg 001FA RW TtcI2Cid TtcI2cId Register -> not implemented in vme_interface CPLD cmm_ace_interface ----------------- 2-bytes VME registers (addresses decoded by vme_inreg and vme_outreg) 00058 RO SystemAceVMEIf System Ace VME Interface 00300 RW ia_ace_ctrl 00302 RW ia_ace_d_msb 00304 RW ia_ace_rst 00306 RO ia_ace_out 00308 RO ia_ace_stats i2c_ttc ------- 2-bytes VME registers (addresses decoded by ) RW ia_ttc_dqram -->> to be added VME commands: vme scan; vme dump (Read from VME); vme edit (Write to VME) sbccmx00.cern.ch> vme scan Installing SIGBUS handler. Scanning from $0 to $ffffff in steps of $1000 TundraFactory Creating single map tundra mapper SingleMapper uses 18 bits, ff000000 as mask, and ffffff as offset mask Region 0: 780000 to 7fffff Region 1: c00000 to c00fff Region 2: d00000 to d00fff sbccmx00.cern.ch> sbccmx00.cern.ch> vme dump 0x780000 0x7801ff Installing SIGBUS handler. Dumping from $780000 to $7801ff TundraFactory Creating single map tundra mapper SingleMapper uses 18 bits, ff000000 as mask, and ffffff as offset mask 00780000: 2417 0fff 001e 001e 0f11 00ff 00fc ffff 00780010: ffff ffff ffff ffff ffff ffff ffff ffff 00780020: ffff ffff ffff ffff ffff ffff ffff ffff 00780030: ffff ffff ffff ffff ffff ffff ffff ffff 00780040: 0000 0000 0001 0001 ffff ffff ffff ffff 00780050: ffff ffff 0007 000b 0003 0003 ffff 0000 00780060: 0000 ffff ffff ffff ffff ffff ffff ffff 00780070: ffff ffff ffff ffff ffff ffff ffff ffff 00780080: ffff ffff ffff ffff ffff ffff ffff ffff 00780090: ffff ffff ffff ffff ffff ffff ffff ffff 007800a0: ffff ffff ffff ffff ffff ffff ffff ffff 007800b0: ffff ffff ffff ffff ffff ffff ffff ffff 007800c0: ffff ffff ffff ffff ffff ffff ffff ffff 007800d0: ffff ffff ffff ffff ffff ffff ffff ffff 007800e0: ffff ffff ffff ffff ffff ffff ffff ffff 007800f0: ffff ffff ffff ffff ffff ffff ffff ffff 00780100: ffff ffff ffff ffff ffff ffff ffff ffff 00780110: ffff ffff ffff ffff ffff ffff ffff ffff 00780120: ffff ffff ffff ffff ffff ffff ffff ffff 00780130: ffff ffff ffff ffff ffff ffff ffff ffff 00780140: ffff ffff ffff ffff ffff ffff ffff ffff 00780150: ffff ffff ffff ffff ffff ffff ffff ffff 00780160: ffff ffff ffff ffff ffff ffff ffff ffff 00780170: ffff ffff ffff ffff ffff ffff ffff ffff 00780180: ffff ffff ffff ffff ffff ffff ffff ffff 00780190: ffff ffff ffff ffff ffff ffff ffff ffff 007801a0: ffff ffff ffff ffff ffff ffff ffff ffff 007801b0: ffff ffff ffff ffff ffff ffff ffff ffff 007801c0: ffff ffff ffff ffff ffff ffff ffff ffff 007801d0: ffff ffff ffff ffff ffff ffff ffff ffff 007801e0: ffff ffff ffff ffff ffff ffff ffff ffff 007801f0: ffff ffff ffff ffff ffff 0008 00fc 0000 sbccmx00.cern.ch> sbccmx00.cern.ch> vme edit 0x780004 Installing SIGBUS handler. Editing from $780004 to $ffffff TundraFactory Creating single map tundra mapper SingleMapper uses 18 bits, ff000000 as mask, and ffffff as offset mask 00780004: 001e> 1 00780006: 0001> type "^C" to exit sbccmx00.cern.ch> sbccmx00.cern.ch> vme dump 0x780000 0x78000f Installing SIGBUS handler. Dumping from $780000 to $78000f TundraFactory Creating single map tundra mapper SingleMapper uses 18 bits, ff000000 as mask, and ffffff as offset mask 00780000: 2417 0fff 0001 0001 0f11 00ff 00fc ffff sbccmx00.cern.ch> ---- ???? -> During vme dump reg 00006 keep the data from reg 00004 -> If dump from reg 00006, then it read correctly - all zeroes sbccmx00.cern.ch> vme dump 0x780006 0x78000f Installing SIGBUS handler. Dumping from $780006 to $78000f TundraFactory Creating single map tundra mapper SingleMapper uses 18 bits, ff000000 as mask, and ffffff as offset mask 00780006: 0000 0030 0000 0000 0000 sbccmx00.cern.ch> Bus error in the 6U VME crate generated by the test card: - disconnect the IC24-8 (BERR*) from the VME connector (C11) - add 1K3 resistor to the net IC24-8 - IC23-2 6.3 Connecting to XILINX iMPACT on ASTRA ---------------------------------------- Use X-Win32 to connect to ASTRA File "astra.xw32": false ssh astra (GNOME) never /usr/bin/gnome-session astra.cern.ch true false single Transfer bit files for FPGAs progrfmming to ASTRA (lxplus) using WinSCP ASTRA -> /afs/cern.ch/user/e/ermoline Spartan3 -> C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_vat\cmx_vat.bit Virtex6 -> C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_alg_test\cmx_alg_test.bit open terminal on ASTRA and: source impact.sh File "impact.sh" # Setup for iPMACT # cd /scratch/work/ISE14.2/14.2/ISE_DS . settings64.sh . exp_env_vars cd cd impact/ /afs/cern.ch/user/e/ermoline/impact - project directory bash-3.2$ impact Assign new configuration file to Spartan3 -> /afs/cern.ch/user/e/ermoline/cmx_vat.bit Assign new configuration file to Virtex6 -> /afs/cern.ch/user/e/ermoline/cmx_alg_test.bit sbccmx00.cern.ch> vme dump 0x780000 0x78000f 00780000: 2417 0fff 001e 001e 0f11 00ff 00fc ffff ---- Program FPGAs sbccmx00.cern.ch> vme dump 0x780000 0x78000f 00780000: 2417 0fff 001e 001e 0030 0000 0000 0000 ---- 6.4 Study CMX_VAT VHDL: ----------------------- 26.01.2013 - remove files ibufg_ipb_xlx.vhd and bufg_ipb_xlx.vhd from project cmx_vat They are used in i2c_ttc: -> ibufg_ipb_xlx.vhd -- error during XST synthesis (?) ERROR:Xst:2035 - Port has illegal connections. This port is connected to an input buffer and other components. Input Buffer: Port of node (IBUFG) in unit -> bufg_ipb_xlx.vhd -- error during PAR (?) ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site . The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "CLK40" CLOCK_DEDICATED_ROUTE = FALSE; > Test bench cmx_vat_vmeif_tb.vhd for VME interface in cmx_vat.vhd ---------------------------------------------------------------- --Used files from Ian simulation directory: C:\My Docs\Work\MSU\Upgrade\CMM\CMM FW\Ian_vhdl\cmm_main_test_hdl\hdl --"te_vme" (file: te_vme_test.vhd) - added to the project directory only for reference - --how to use procedures from "vme_drivers" (files: vme_drivers.vhd and vme_drivers_body.vhd) -> --New "vme_drivers_pkg" (vme_drivers.vhd and vme_drivers_body.vhd in one file) placed to the project directory: --C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_vat\cmx_vat_sources\vme_drivers_pkg.vhd --> looks like there are old files for very initial simulations... - ISE: To create your own test bench file in Project Navigator, select Project > New Source, and select VHDL Test Bench in the New Source Wizard. An empty stimulus file is added to your project. You must define the test bench in a text editor. -> Create cmx_vat_vmeif_tb.vhd - test bench for CMX_VAT_VMEIF ("vme_interface" in file vme_interface_struct.vhd.vhd) - Specifying Simulation Properties: In the Processes pane, expand ISim Simulator, right-click Simulate Behavioral Model and select Process Properties. -> Simulation Run Time: -> Custom Waveform Configuration File: C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_vat\cmx_vat_vmeif_tb.wcfg - set initial values for signals: MODID<11..0> set to <1001_0101_1010> (095a) - inserted jumper = '0' GEOADD(6:4) and GEOADD(0) set to <111><1> -> e/γ Crate-CMM CMM1 in slot 20 0x780000-0x7FFFFE -------------------- -- read register 00000 RO ModuleIdA Module ID Register A -> ReadOnly_Reg (RALNo set to 2417 in FW) -- word VME address (23 DOWNTO 1): 0x780000 -> "0111_1000_0000_0000_0000_000x" -------------------- vme_address <= "01111000000000000000000"; -- n_ds0_int <= '1'; n_write <= '1'; wait for clk40_period; n_ds0_int <= '0'; -- assert DS wait for clk40_period * 4; -- DS lenght n_ds0_int <= '1'; -- remove DS - Can read register 00000 via test behch Study CMX_VAT VHDL ------------------ vme_interface ------------- Design structure: - vme_interface (vme_interface_struct.vhd) <- package - vme_cmm (vme_cmm.vhd) - CMM_Board_Select (cmm_board_select_rtl.vhd) - CMM_VMEdecoder (cmm_vmedecoder_rtl.vhd_ - Registers (registers_fullstruct.vhd) - ControlGeo (controlgeo_rtl.vhd) - RW_Reg (rw_reg_rtl.vhd) - ReadOnly_Reg (readonly_reg_rtl.vhd) - gen_nds (gen_nds_rtl.vhd) - gen_rlalgo (gen_rlalgo_fsm.vhd) <- package vme_cmm (vme_cmm.vhd) - input_latch (input_latch_rtl.vhd) - pulse_reg_a (pulse_reg_a_fsm.vhd) 2-bytes VME registers (addresses decoded by CMM_VMEdecoder): 00000 RO ModuleIdA Module ID Register A -> ReadOnly_Reg 00002 RO ModuleIdB Module ID Register B -> ReadOnly_Reg 00004 RW ControlModeReg Control Mode Register -> ControlGeo? 00006 RW ControlPulseReg Control Pulse Register -> gen_rlalgo + pulse_reg_a? 00008 RO StatusReg Status Register -> ReadOnly_Reg 0000A RO FifoStatusReg FIFO Status Register -> ReadOnly_Reg 00054 RO I2CId I2C FPFA irmware version -> ReadOnly_Reg (n_i2c_en -- comes to TTC but not used in VHDL) 00056 RO VmeId VME CPLD firmware version -> ReadOnly_Reg 00058 RO SystemAceVMEIf System Ace VME Interface -> not implemented in vme_interface, implemented in cmm_ace_interface 0005C RW CanAccessA CAN Access Register A -> not implemented in vme_interface 0005E RW CanAccessB CAN Access Register B -> RW_Reg - CMM_Board_Select: generates "board_select_n" signal The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x00700000-0x0077FFFE : VME address (23 DOWNTO 1): 0x700000 -> "0111_0000_0000_0000_0000_000x" 20 CMM1 0x00780000-0x007FFFFE : VME address (23 DOWNTO 1): 0x780000 -> "0111_1000_0000_0000_0000_000x" GEOADD(0) - 0 (Left) 1 (Right) if (addressbus(23 downto 20)="0111") and (addressbus(19)= geoaddr_0) then board_select_n <= '0'; - input_latch : to Latch VME inputs because some VME masters remove them before the cycle is over if (n_ds0_int = '1') then address_ltchd <= vme_address; n_write_ltchd <= n_write; - gen_nds : generates single-tick data strobe at beginning of n_ds0_int if (clk40'event and clk40 = '1') then n_ds0_old <= n_ds0_int; if (n_ds0_int = '0' and n_ds0_old = '1') then nds <= '0'; else nds <= '1'; - gen_rlalgo : generates fls_rlalgo used in ACE (ace_reset) - 60 clk cycles long - CMM_VMEdecoder : Implementing RW register "ye_rw80" at the address 16#0080# -> add constant to package vme_cmm.vhd : constant ye_rw80 : integer := 16#0080#; -- test RW register -> modify cmm_vmedecoder_rtl.vhd : add output "ye_rw80_en", comment all other outputs -> modify CMM_VMEdecoder instantiation in vme_interface_struct.vhd - Registers (registers_fullstruct.vhd) - ControlGeo (controlgeo_rtl.vhd) 00004 RW ControlModeReg - RW_Reg (rw_reg_rtl.vhd) - ReadOnly_Reg (readonly_reg_rtl.vhd) Test in VME crate: - Use X-Win32 to connect to ASTRA - Transfer bit files for FPGAs progrfmming to ASTRA (lxplus) using WinSCP ASTRA -> /afs/cern.ch/user/e/ermoline Spartan3 -> C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_vat\cmx_vat.bit Virtex6 -> C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_alg\cmx_alg_.bit - open terminal on ASTRA and: source impact.sh impact - Assign new configuration file to Spartan3 -> /afs/cern.ch/user/e/ermoline/cmx_vat.bit Assign new configuration file to Virtex6 -> /afs/cern.ch/user/e/ermoline/cmx_alg.bit - Use PuTTY to connect to sbccmx00.cern.ch source LVL1/l1calo/scripts/login/.lxplus_bashrc sbccmx00.cern.ch> vme scan Region 0: 780000 to 7fffff Region 1: c00000 to c00fff Region 2: d00000 to d00fff sbccmx00.cern.ch> vme dump 0x780000 0x78000f 00780000: 2417 0fff 001e 001e 0f11 00ff 00fc ffff - Program FPGAs using iMPACT ---- sbccmx00.cern.ch> vme dump 0x780000 0x78000f 00780000: 2417 0fff 001e 001e 0030 0000 0000 0000 ---- - sbccmx00.cern.ch> vme edit 0x780080 6.5 Study CMX_ALG VHDL: ----------------------- Check level shifters - pass the data from Spartan to V6 via shifters and then from V6 to Spartan LEDs. Spartan: VMEDATA <= MODID_L; Virtex6: SP2V5IO <= V6_VD; Spartan: DRIVER <= SP2V5IO; A simple VME interface in Virtex6 - RO and RW registers based on i2c_ttc_struct.vhd abd i2c_vme_struct.vhd Create cmx_alg.vhd and instantiate vme_outreg ("ye_ro84" = "abcd") and vme_inreg ("ye_rw86") WORKS! Only V6_BDS -> BRDDS out from CMX_VAT is used (board_ds in vme_interface) board_ds <= n_board_select_int nor n_ds0_int; -- n_ds0_int -> DS strobe VMEDS0_L -- n_board_select_int -> board_select_n from CMM_Board_Select: if (addressbus(23 downto 20)="0111") and (addressbus(19)= geoaddr_0) then -- CMM base address and slot number board_select_n <= '0'; VMEDS (ST54-ST50) - VME address buffer : 11/02/13 - change to ST50(TAP5) - 25 ns Program CMX_VAT from on-chip flash memory sbccmx00.cern.ch> source LVL1/l1calo/scripts/login/.lxplus_bashrc sbccmx00.cern.ch> vme dump 0x780000 0x780100 00780000: 2417 095a 001e 001e 0f11 00ff 00ff ffff 00780040: 0000 0000 0001 0001 ffff ffff ffff ffff 00780050: ffff ffff 0007 002b 0003 0003 ffff 0000 00780080: 0000 0000 0000 ffff ffff ffff ffff ffff sbccmx00.cern.ch> vme edit 0x780080 00780080: 0000> a5a5 00780082: 0000> 5a5a 00780084: 5a5a> sbccmx00.cern.ch> vme dump 0x780000 0x780100 00780080: a5a5 5a5a 5a5a ffff ffff ffff ffff ffff sbccmx00.cern.ch> vme edit 0x780080 00780080: a5a5> 1234 00780082: 5a5a> 5678 00780084: 5678> sbccmx00.cern.ch> vme dump 0x780000 0x780100 00780080: 1234 5678 5678 ffff ffff ffff ffff ffff Program CMX_ALG sbccmx00.cern.ch> vme dump 0x780000 0x780100 00780000: 2417 095a 001e 001e 0030 0000 0000 0400 00780040: 0000 0000 0001 0001 0401 0401 0401 0401 00780050: 0401 0401 0007 002b 0003 0003 0403 0000 00780080: 1234 5678 abcd 0000 0000 0000 0000 0000 6.6 Study TTCDec card and TTC interface (i2c_ttc): -------------------------------------------------- - insert TTCDec card - insert TTC optical cable (connect to TTCvx output) - jumpers settings: - remove clock selection jumper (ST65): -> CLOCK40DES1 from IC43-8 (CLK40DES1P1 from TTCDec card - TTCDECS2/J4-16) -> On VAT: LED LD9 (CLK40) is ON -> On VAT: LED LD10 (STATUS2) if OFF - XTAL as clock source -> On TTCDec card: LED DS1 (TTCREADY) is ON Clock selection scheme on the TTCDec card: ------------------------------------------ There are two input control bits (P/D Mode select and ClkSel clock select) and two output status bits (S1 and S2). The two deskewed clocks from TTCrx, Clock40Des1 and Clock40Des2, are selected or deselected simultaneously. The detailed function is as below. - P/D = 1: Protected Mode (Normal Running Mode) - ClkSel = 1: Select TTCrx as clock source, S1=TTCReady, S2 =1 - ClkSel = 0: Select XTAL as clock source, S1=TTCReady, S2 =0 - P/D = 0: Debug Mode - ClkSel = 1: Clock source automatic changeover - TTCReady = 1: Select TTCrx as clock source, S1 =1, S2 = 1 - TTCReady = 0: Select XTAL as clock source, S1 =0, S2 = 0 - ClkSel = 0: Select XTAL as clock source, S1=TTCReady, S2=0 STATUS2 = '1' when TTCrx clock In VAT FPGA, in 00004 RW ControlModeReg Control Mode Register -> vme_interface -> Registers -> ControlGeo bit 5 - TTC Clock Enable (TTCCLKSEL - ClkSel) -> '1' - TTCrx clock bit 6 - TTC Protect (TTCPD - P/d) -> '1' - Protected Mode (Normal Running Mode) initially set to '0' Read from 00004 RW ControlModeReg "001e" - "0000_0000_0001_1110") Set both bits to '1' (write to 00004 RW ControlModeReg "007e" - "0000_0000_0111_1110") -> On VAT: LED LD9 (CLK40) is ON - clock is running -> On VAT: LED LD10 (STATUS2) if ON - TTCrx as clock source -> On TTCDec card: LED DS1 (TTCREADY) is ON - TTC ready bit TTC Ready (7) set in the 00008 RO StatusReg Status Register -> ReadOnly_Reg sbccmx00.cern.ch> vme dump 0x780000 0x7800ff 00780000: 2417 095a 007e 007e 0f91 00ff 00ff ffff TTCrx Hardwired ID and MasterMode bits after the reset: ------------------------------------------------------- After a reset, the TTCrx reads in the 14-bit value of its ID, encoded with connected resistors, as seen in Figure 9. During a reset, the output drivers on the SubAddr<7:0>, Data<7:0> buses are deactivated. Resistors, which connect the different pins of the bus to either VDD or GND, encode a 16 bit value, which pull the values on SubAddr<7:0>, Data<7:0> to a logic zero or one. On CMM: ------- Data<7:0> -> TTC_DOUT - TTC_DOUT<5..0> -> set by jumpers (SB56-55 - SB66-65) to "000100" (in VAT - ST8-ST13) - ST11 set to '1' others to '0' - TTC_DOUT<7..6> -> set by jumpers GEOADDR1(SB54-53, in VAT - ST16) and GEOADDR0(backplane, in VAT set to '1') to "01" Therefore Data<7:0> = "0100_0100" (44 hex) SubAddr<7:0> -> TTC_SUBADDR - TTC_SUBADDR<0> -> set by jumpers GEOADDR2(SB52-51, in VAT - ST15) to '0' - TTC_SUBADDR<1> -> set by jumpers GEOADDR3(SB50-49, in VAT - ST14) to '0' - TTC_SUBADDR<2> -> GEOADDR4 (backplane, in VAT set to '1') - TTC_SUBADDR<3> -> GEOADDR5 (backplane, in VAT set to '1') - TTC_SUBADDR<4> -> GEOADDR6 (backplane, in VAT set to '1') - TTC_SUBADDR<7..5> -> set by jumpers (SB44-43 - SB48-47, in VAT 0 ST7-5) to "000" Therefore SubAddr<7:0> = "0001_1100" (1C hex) The two uppermost bits of SubAddr<7:0> are not used for the ID. They define the “MasterMode<1:0>” bits. These bits are crucial for the operation of the TTCrx, since they encode the basic mode of operation, and were therefore included in the hard-wired initialisation procedure. For choosing the standard mode of operation, SubAddr<6> and <7> must be resistor-connected to GND. This number is then latched at the rising edge of the Reset_b signal. - Reset_b signal is generated on the TTCDes card on power-on and by the RESET_B_IN input from TTCDECS1/J3-29) - RESET_B_IN (RESET_B on VAT generated by extending in IC17 TTCRST_L from Spartan IC13-N7 After the latching, the output drivers are switched on again, and SubAddr<7:0>, Data<7:0> act as outputs. By this, the serial PROM, which was the unique option to set the chip ID in early versions, is not necessary any more. The TTCrx Chip_ID<13..0> = SubAddr<5..0>Data<7..0> : 14-bit value = "01_1100_0100_0100" (1C44 hex) I2C_ID<5..0> = Data<5..0> = "00_0100" (04 hex) On TTCDec card: --------------- 3.10 Configuration No EPROM is needed. EnProm/PromReset pin is connected to GND via a 100k resistor. SubAddr<7:6> are connected to GND via 100k resistors. I2C_ID and Chip_ID addresses are set initially by resistors on SubAddr<5:0> and Dout<7:0> upon reset. Dout<5:0> are connected to GND via 100k resistors, Dout<7:6> and SubAddr<5:0> are connected to VCC via 100k resistors. So the initial the initial TTC chip address (Chip_ID) is 3FC0h "0011_1111_1100_0000" -> ? and TTC chip I2C address I2C_ID<5..0> = Data<5..0> = "00_0000" (00 hex) -> ? The TTCrx can be configured through I2C interface. Two pull-up resistors on the TTCDec connect SCL and SDA to VCC for correct operation. If JTAG signals are not used, the JTGATCK, JTAGTDI, JTAGTMS and JTAGTRST_b signals (CMOS inputs) should be fixed to logic 0 on the 9U motherboards. A solder link is also provided for JTAGTRST_b signal on the TTCDec to fix it to ground if needed. -- There is a TTCDec card on CMX (and on CMM). The TTCrx chip on the TTCDec card reads 14-bit hardwired ID and 2-bit MasterMode bits after reset. These bits are set by resistors, connected to power or GND. But these resistors are used on both - TTCDec card and the CMM board, and set different values. Q: How do you deal with this? "01_1100_0100_0100" (1C44 hex) -> it looks like this ID is used by the TTCrx chip "11_1111_1100_0000" (3FC0 hex) TTC interface (i2c_ttc): ------------------------ VHDL top file: i2c_ttc_struct.vhd Design structure: (just parts, related to VME) i2c_ttc (i2c_ttc_struct.vhd) <- package vme_cmm (vme_cmm.vhd) i2c_vme (i2c_vme_struct.vhd) ff_e (ff_e_rtl.vhd) i2c_trigger (i2c_trigger_rtl.vhd) reg_e (reg_e_rtl.vhd) vme_inreg (vme_inreg_rtl.vhd) vme_inreg_init (vme_inreg_init_rtl.vhd) vme_outreg (vme_outreg_rtl.vhd) ttc_dump (ttc_dump_struct.vhd) reg_e (reg_e_rtl.vhd) ttc_dump_ram (ttc_dump_ram_struct.vhd) dpr256x16 (dr256x16_xcore1.vhd) dpr256x16_xc - XILINX CoreGenerator (not available for CoolRunner-II CPLD !!!) vme_dqram (vme_dqram_rtl.vhd) vme_outreg (vme_outreg_rtl.vhd) vme_outreg (vme_outreg_rtl.vhd) ENTITY i2c_vme IS PORT( addr_vme : IN std_logic_vector (16 DOWNTO 1); -- Address bus VMEADDR data_to_vme : IN std_logic_vector (7 DOWNTO 0); ds : IN std_logic ; -- (Data ack) BRDDS iclk40 : IN std_logic ; -- 40MHz Clk CLK40 ncs : IN std_logic ; -- ncs <= '0'; -- bypass the VME_CPLD decoding.... rd_nwr : IN std_logic ; -- VME Write VMEWR_L revision_id : IN std_logic_vector (15 DOWNTO 0); set_vme_status : IN std_logic ; data_vme : INOUT std_logic_vector (15 DOWNTO 0) -- Data bus VMEDATA ); 2-bytes VME registers: 0040 RW TTC control reg -> i2c_ttc -> i2c_vme -> vme_inreg 0042 RO TTC status reg -> i2c_ttc -> i2c_vme -> vme_outreg 0044 RO TtcNotReady ? -> i2c_ttc -> vme_outreg 0054 RO I2CId I2C FPFA irmware version -> i2c_ttc -> i2c_vme -> vme_outreg 01FA RW TtcI2Cid TtcI2cId Register -> i2c_ttc -> i2c_vme -> vme_inreg_init 01FC RO TtcBrcst TtcBrest Register -> i2c_ttc -> ttc_dump -> vme_outreg 01FE RO TtcDq TTC DQ Register -> i2c_ttc -> ttc_dump -> vme_outreg 0200 RO TtcDump 6.7 Study TTC_DUMP memory ------------------------- TTCrx Ref.Man. Ch.2 p.14 ------------------------ Individually-addressed commands/data frames are identified by a “1” in the header bit (FMT). This frame is used to address a single TTCrx in the system. Data sent to a particular TTCrx are output to the Dout<7:0> and SubAddr<7:0> buses. The Data Qualifier bits DQ<3:0> are set to “0” for indicating IAC data, and DoutStr validates the data bus content. TTCrx Ref.Man. Ch.4 p.21 ------------------------ Individually-addressed commands can be sent to the outside world, such that their net 16-bit data content appears on the Dout<7:0> and SubAddr<7:0> pins and DoutStr validates the signal. Secondly, IACs can be used to write internal registers of the TTCrx and execute internal commands. One bit in the IAC data frame (the “E” bit in Table 2) signals if the command is internal or external. The individually addressable space for each TTCrx is split into two: internal and external. The internal address space is used to write the TTCrx internal registers, while the external space allows commands and data to be transmitted to the detector electronics. When an individually-addressed command/data frame is received with the E bit equal to “0” the internal address space is assumed. A “1” received in the E bit indicates external addressing. Upon reception of an external command, the sub-address and data buses are set according to the data contents of the received command. TTCrx Ref.Man. Ch.9 p.37 ------------------------ DQ<3:0> - Data qualifier bits. This bus indicates the type of data present on the data bus register, corresponding to the table below. DQ<3:0> Data<7:0> bus content SubAddr<7:0> bus content 0000 Individually-addressed command data Individually-addressed command sub-address 0001 Single Bit Error Counter Low =4 (?) 0010 Single Bit Error Counter High =4 (?) 0011 Double Bit Error Counter Low =4 (?) 0100 SEU Error Counter =4 (?) 0101 Fine Delay register 1 =5 (?) 0110 Fine Delay register 2 =5 (?) 0111 Coarse Delay register =5 (?) 1000 Control register =5 (?) 1001 ID register <7:0> =5 (?) 1010 ID register <13:8> =5 (?) (See also “ERDUMP” and “CRDUMP” commands in Chapter 4). Implementation -------------- TTC_DUMP memory keep the outputs from the IAC - Individually-Addressed Commands/data frames. A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. -- I2C-FPGA RAM for testing the TTC: constant ia_ttc_dqram : integer := 16#0200#; -- SUBADDR & DOUT, ... to 16#21E# -> 32 bytes (16 words) ENTITY ttc_dump_ram IS GENERIC( ia_vmebase : integer := 0 -- not used??? ); PORT( addr_vme : IN std_logic_vector (15 DOWNTO 0); -- addr_vme:IN std_logic_vector(16 DOWNTO 1); from VMEADDR:in std_logic_vector(23 downto 1); din_a : IN std_logic_vector (15 DOWNTO 0); doutstr : IN std_logic; dq : IN std_logic_vector (3 DOWNTO 0); ds : IN std_logic; iclk40 : IN std_logic; ncs : IN std_logic; rd_nwr : IN std_logic; data_vme : INOUT std_logic_vector (15 DOWNTO 0) ); COMPONENT dpr256x16 PORT ( addra : IN std_logic_vector (7 DOWNTO 0); addrb : IN std_logic_vector (7 DOWNTO 0); clka : IN std_logic ; clkb : IN std_logic ; dia : IN std_logic_vector (15 DOWNTO 0); dib : IN std_logic_vector (15 DOWNTO 0); wea : IN std_logic ; web : IN std_logic ; doa : OUT std_logic_vector (15 DOWNTO 0); dob : OUT std_logic_vector (15 DOWNTO 0) ); COMPONENT vme_dqram PORT ( addr_vme : IN std_logic_vector (15 DOWNTO 0); dout_vme : IN std_logic_vector (15 DOWNTO 0); dq : IN std_logic_vector (3 DOWNTO 0); ds : IN std_logic ; iclk40 : IN std_logic ; ncs : IN std_logic ; rd_nwr : IN std_logic ; addr_a : OUT std_logic_vector (7 DOWNTO 0); addr_b : OUT std_logic_vector (7 DOWNTO 0); web : OUT std_logic ; data_vme : INOUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; I2 : dpr256x16 PORT MAP ( addra => addr_a, addrb => addr_b, clka => iclk40, clkb => iclk40, dia => din_a, dib => data_vme, wea => doutstr, web => web, doa => unused, dob => dout_vme ); I1 : vme_dqram PORT MAP ( addr_vme => addr_vme, dout_vme => dout_vme, dq => dq, ds => ds, iclk40 => iclk40, ncs => ncs, rd_nwr => rd_nwr, addr_a => addr_a, addr_b => addr_b, web => web, data_vme => data_vme ); architecture rtl of vme_dqram is signal ren: std_logic; -- vme read enable signal wen: std_logic; -- vme write enable signal vme_base: std_logic_vector(15 downto 0); signal ds_dbounce: std_logic; -- ds clocked by local clk signal ds_dly_1 : std_logic; -- delayed version of above signal ds_dly_2 : std_logic; -- delayed version of above begin addr_a <= "0000" & dq; -- addr_b <= "0000" & addr_vme(3 downto 0); -- word address -- VME access... -- ia_vmebase must be multiple of 16#20# . -- RAM occupies (VME byte) addresses 0-1E above it. vme_base <= addr_vme(15 downto 4) & "0000"; -- ren <= vme_ren (ia_ttc_dqram, vme_base, ncs, rd_nwr, ds); -- constant ia_ttc_dqram : integer := 16#0200#; -- to 16#21E# -> 32 bytes (16 words) wen <= vme_wen (ia_ttc_dqram, vme_base, ncs, rd_nwr, ds); vme_datr_proc: process (ren, dout_vme) -- VME read... begin if (ren = '1') then data_vme <= dout_vme; else data_vme <= "ZZZZZZZZZZZZZZZZ"; end if; end process; webproc: process (iclk40, ds, ds_dbounce, ds_dly_1, ds_dly_2) -- VME write... -- generates web: short, synchronous VME write-enable signal begin if (iclk40'event and iclk40 = '0') then ds_dbounce <= ds; ds_dly_1 <= ds_dbounce; ds_dly_2 <= ds_dly_1; -- web <= wen and ds_dly_1 and not ds_dly_2; end if; end process; function vme_ren ( ia_vme: integer; -- VME location -- ia_ttc_dqram : integer := 16#0200#; -- to 16#21E# addr_vme: std_logic_vector (15 downto 0); -- VME address bus -- vme_base <= addr_vme(15 downto 4) & "0000"; ncs: std_logic; -- chip select, active low rd_nwr: std_logic; -- 1=read, 0=write ds: std_logic ) -- strobe, active high return std_logic is -- read enable for location ia_vme variable iaddr_vme: integer range 0 to 65535; -- 16-bit address begin iaddr_vme := to_integer(unsigned(addr_vme)); if (iaddr_vme = ia_vme/2) and (ncs = '0') and (rd_nwr = '1') then return '1'; else return '0'; end if; end vme_ren; function vme_wen ( ia_vme: integer; -- VME location addr_vme: std_logic_vector (15 downto 0); -- VME address bus ncs: std_logic; -- chip select, active low rd_nwr: std_logic; -- 1=read, 0=write ds: std_logic ) -- strobe, active high return std_logic is -- write enable for location ia_vme variable iaddr_vme: integer range 0 to 65535; -- 16-bit address begin iaddr_vme := to_integer(unsigned(addr_vme)); if (iaddr_vme = ia_vme/2) and (ncs = '0') and (rd_nwr = '0') then return '1'; else return '0'; end if; end vme_wen; See also next chapter (6.8 - 00200 RO TtcDump TTC Dump RAM) 6.8 Study VAT registers: ------------------------ write "007e" to 00004 RW ControlModeReg - set TTC Clock Enable & TTC Protect config ALG and read 00B0 from 00008 RO StatusReg write "0020" to 00006 RW ControlPulseReg - Reset I2C controller (also reset 00044 RO TtcNotReady) repeat - write "0000" to 00040 RW TtcrxControl and read 00042 RO TtcrxStatus, look at I2C Error (0000) 00000 RO ModuleIdA Module ID Register A -> vme_interface -> Registers -> ReadOnly_Reg (I0) - 16 bit number, set to "2417" in firmware (in vme_interface, module_id_a <= X"2417";) 00002 RO ModuleIdB Module ID Register B -> vme_interface -> Registers -> ReadOnly_Reg (I2) - bits 7-0 Module Serial number, bits 11-8 Hardware Revision Number -> set in VAT to "095a" by jumpers 00004 RW ControlModeReg Control Mode Register -> vme_interface -> Registers -> ControlGeo (I9) - after power-on read "001e" - GEOADD(0) (bit 1) and GEOADD(6:4) (bits 4-2) are set to '1' on VAT card - bit 5 - TTC Clock Enable (TTCCLKSEL - ClkSel) -> '1' - TTCrx clock When this bit is set, the CMM uses the TTC clocks. When this bit is cleared, the CMM uses the on-board 40 MHz oscillator. Trying to set this bit when the TTC is not ready has no effect (the bit remains cleared). (TTC Ready - bit 7 in 00008 RO StatusReg) - bit 6 - TTC Protect (TTCPD - P/d) -> '1' - Protected Mode (Normal Running Mode) This bit controls the TTC Decoder protection scheme described in the TTCDec specification, which determines the clock behaviour when the TTC clock is lost. When this bit is cleared (Debug mode), the TTCDec automatically switches to use a crystal clock if the TTC signal is lost. When the bit is set (Protected mode), the TTCDec does not switch automatically. This prevents a TTC problem being concealed by the automatic switchover. - Set both bits 5 and 6 to '1' (write "007e" to 00004 RW ControlModeReg - "0000_0000_0111_1110") -> On VAT: LED LD10 (STATUS2) if ON - TTCrx as clock source 00006 RW ControlPulseReg Control Pulse Register -> vme_interface -> gen_rlalgo + pulse_reg_a? - All bit fields are inputs to card. All bits read back as zero, and writing a zero to a bit has no effect. - bit 0 Reset Module BRDRST_L : vme_interface -> pulse_reg_a -> n_reset0 - goes TO CMX_ALG FPGA - bit 1 Reset TTC TTCRST_L : generates RESET_B for TTCDec card (TTCrx chip reset) - bit 5 Reset I2C controller : generated but not used ? - see explanation in 00044 -> corrected on 24.04.2013 - bit 10 - Writing a 1 to this bit reloads the Crate-summing FPGA with firmware corresponding to the module geographical address specified in the Geoadd Bypass field in the Control Mode Register. implemented in vme_interface -> gen_rlalgo -> fls_rlalgo <= '1'; n_fls_rlalgo -> FLSRLALG -> comes to ACE interface n_ace_reset <= n_fls_rlalgo; -> output ACERST_L (ACE chip reset) The entire System ACE CF controller device can be reset by asserting the RESET pin of the System ACE CF Controller. System ACE CF controller reset (active Low; needs to be active for three clock cycles). -> does it reloads both - Crate and System - FPGAs from XILINX SystemACE controller? - bit 11 - Writing a 1 to this bit reloads the System-summing FPGA ??????? implemented in vme_interface -> pulse_reg_a -> n_reset11 => n_rst_rt_ctrs -> sp_service(1) <= not n_rst_rt_ctrs; sp_core(2) <= not n_rst_rt_ctrs; -> looks like Bit 12 - Writing a 1 to this bit sets all rate meter counters and the normalisation counter to zero 00008 RO StatusReg Status Register -> vme_interface -> Registers -> ReadOnly_Reg (I3) - bit 0 When this bit is set, a parity error has been detected on one or more of the incoming backplane or cable links since the last error reset. The bit is cleared by the error-reset bit in the Control Pulse Register (bit 9 CLRE) in VAT connected to CMX_ALG FPGA (may be reas as '1' when CMX_ALG FPGA is not configured) - bits 1-3 are not connected on the CMM board, in VAT firmware they are set to '0' -> bit 1 (in spec: This bit is set if all FPGA configurations have loaded successfully) - use DONE from Spartan? - bit 4 I2C FPGA loaded (in VAT set to '1' TTCDONE <= '1'; -> TTC FPGA merged now with VME CPLD and ACE CPLD in Spartan) - bit 5 Crate FPGA loaded CMMDONE in VAT connected to CMX_ALD DONE_0 (IC14-L6) - bit 6 System FPGA loaded CMMSDONE in VAT not connected (onlt test point) - bit 7 TTC Ready in VAT connected to STATUS1 from TTCDec (TTCReady from TTCrx chip) - bits 8-11 in VAT connected to CMX_ALG FPGA (may be reas as '1' when CMX_ALG FPGA is not configured) - bits 12-15 in VAT set to '0' in firmware - after power-on read as 0f11 (TTC optical fibre is not connected) 0f91 (TTC optical fibre is connected, TTC Ready) after CMX_ALF config: 00B0 (TTC optical fibre is connected) - bits 4,5,7 are set, bits 1,8,9,10,11 are cleared 0000A RO FifoStatusReg FIFO Status Register -> vme_interface -> Registers -> ReadOnly_Reg (I4) - Bits 0–7 Empty and full flags for all of the readout FIFOs on the module - after power-on read as 00ff (CMX_ALG is not configured) or 0000 (CMX_ALG is configured) 00040 RW TtcrxControl TTCrx control reg -> i2c_ttc -> i2c_vme -> vme_inreg (I1) - provide access to the 20 useraccessible internal registers of the TTCrx chip. - All bit fields are inputs to card. Power-up condition initially sets all bits to 0. A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy (see TTC Status register below). An I2C operation is aborted if the reset bit is set. - Bits 0-7 This 8-bit field contains data to be written to the TTCrx chip. - Bits 8-12 Specify the TTCrx register number to be read or written - Bit 13 When set to 1, defines the operation as a write to TTCrx. When set to 0, the operation is a read. - Bit 15 When set to 1, resets the TTC controller logic and aborts any I2C operation in progress. - Writing to TTCrx control reg 00040 all zeroes -> read reg 0 of TTC sbccmx00.cern.ch> vme edit 0x780040 00780040: 0000> 0000 - Reading the TTCrx status reg 00042 sbccmx00.cern.ch> vme dump 0x780042 0x780044 00780042: 0000 - !!!!! in CMM spec in table 3 on page 50 "Offset" is not correct !!!!!! look in TTCrx spec v3.11 page 15 and convert I2C reg. address dec to hex 00042 RO TtcrxStatus TTCrx status reg -> i2c_ttc -> i2c_vme -> vme_outreg (I4) - All bit fields are outputs from card. Power-up condition initially sets all bits to 0 - Bits 0-7 This 8-bit field contains data read from the TTCrx chip. - Bit 13 When set to 1, indicates that an I2C transaction is underway - Bit 14 When set to 1, indicates that an I2C error has occurred i2c_err comes to i2c_vme from i2c_ttc_engine -> i2c_err_int generated in error state of FSM write "0300" to 00040 RW TtcrxControl and read 00042 RO TtcrxStatus, look at data (0093) write "1000" to 00040 RW TtcrxControl and read 00042 RO TtcrxStatus, look at data (0044) write "1100" to 00040 RW TtcrxControl and read 00042 RO TtcrxStatus, look at data (001c) write "1200" to 00040 RW TtcrxControl and read 00042 RO TtcrxStatus, look at data (0004) 00044 RO TtcNotReady ? -> i2c_ttc -> vme_outreg (I3) - not described in the CMM specification, not in vme_cmm package - --bug fix... some PCBs have i2c_rst line broken: latchproc: process (ttc_ready_buf, i2c_rst) begin if (i2c_rst = '1') then ttc_not_ready_latched <= "0"; elsif (ttc_ready_buf = '0') then ttc_not_ready_latched <= "1"; end if; end process; --i2c_rst <= not n_i2c_rst; --bug fix... some PCBs have i2c_rst line broken: i2c_rst <= not sp_i2c(1); --sp_i2c(1) is now active low reset CMX_VAT_TTCIF : I2C_TTC port map ( sp_i2c => "1", -- bug fix for PCBs with n_reset_i2c broken !!!!! restore n_reset_i2c between vme_interface and i2c_ttc -> corrected on 24.04.2013 00054 RO I2CId I2C FPFA irmware version -> i2c_ttc -> i2c_vme -> vme_outreg - decoded in CMM_VMEdecoder -> n_i2c_en -- comes to i2c_ttc not used in VHDL - in i2c_ttc -> i2c_vme (I2) use constant ia_i2cid : integer := 16#0054#; -- I2C FPGA f/w version reg - This register contains the version number of the I2C FPGA controlling the TTCrx chip. This is a 16-bit value. The first version is number 1. - in i2c_ttc -> revision_id <= "0000000000000111"; -- 16#7# -> set to 7 00056 RO VmeId VME CPLD firmware version -> vme_interface -> Registers -> ReadOnly_Reg (I5) - This register contains the version number of the FPGA providing the interface to VME--. This is a 16-bit value; the first version is number 1. - fw_rev_big <= "00000000" & fw_rev; fw_rev <= X"0B"; -> initial IPB version - fw_rev <= X"2B"; -- YE version with added RW registers "ye_rw80" and "ye_rw82" at the addresses 16#0080# and 16#0082# 00058 RO SystemAceVMEIf System Ace VME Interface -> not implemented in vme_interface, implemented in cmm_ace_interface - This register is reserved for VME control of the System Ace device (firmware version) - decoded in CMM_VMEdecoder -> n_sysace_en, but not used - implemented in cmm_ace_interface -> I10 : vme_outreg ; fw_rev <= "00000011"; set to 3 - !!!now impemented in vme_interface (for new ACE interface from Uli) 0005C RW CanAccessA CAN Access Register A -> not implemented - in vme_interface -> CMM_VMEdecoder generates n_can_reg1_en => CANRD_L (in VAT goes on CANbus connector) 0005E RW CanAccessB CAN Access Register B -> vme_interface -> Registers -> RW_Reg (I8) - in vme_interface -> CMM_VMEdecoder generates n_can_reg2_en - Bits 0-3 Writing a 1 to one of these bits causes an interrupt request to the CANBus processor at the corresponding priority. Writing a zero has no effect. --> These bits always read as zero. <-- 001FA RW TtcI2Cid TtcI2cId Register -> i2c_ttc -> i2c_vme -> vme_inreg_init (I7) - Bits 0-5 This register contains the TTC base ID used by the I2C FPGA to communicate with the TTCrx, which is set up as the module resets. It matches the content of the TTCrx base address register I2C_ID (0:5), and should always contain the value 4. - after power-on read as 0008 (shall be 0004) - --init_val => "000100" -- looks like it shall be "001000" init_val => "001000" -- YE - corrected in VHDL !!!!! 24.04.2013 001FC RO TtcBrcst TtcBrest Register -> i2c_ttc -> ttc_dump -> vme_outreg (I11) - All bit fields are outputs from card. - Bits 0-1 These bits read as zero - Bits 2-5 The most recent value of BRCST data bits (2:5) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR1). - Bits 6-7 The most recent value of BRCST data bits (6:7) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR2). 001FE RO TtcDq TTC DQ Register -> i2c_ttc -> ttc_dump -> vme_outreg (I10) - All bit fields are outputs from card. - Bits 0-3 The most recent DQ value output from the TTCrx (that was qualified by the TTC strobe DOUTSTR). 00200 RO TtcDump TTC Dump RAM -> i2c_ttc -> ttc_dump -> ttc_dump_ram (I0) - All bit fields are outputs from card. - Bits 0-7 A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. - !!!!!!!!!!!!!!!! check the RAM It looks like the TTC Dump RAM (DuaPort RAM) is implemented as RW from VME However, it seems that the write from VME doesn't work -bash-3.2$ vme dump 0x780200 0x78021f 00780200: 0000 0000 0000 0000 0000 0000 0000 0000 00780210: 0000 0000 0000 0000 0000 0000 0000 0000 -bash-3.2$ vme edit 0x780200 00780200: 0000> ffff ... 0078021e: 0000> ffff -bash-3.2$ vme dump 0x780200 0x78021f 00780200: 0000 0000 f49a ffff 0000 0000 0000 ffff 00780210: 0000 0000 ff10 ffff 0000 0000 0000 ffff -bash-3.2$ vme edit 0x780200 00780200: 0000> 5555 ... 0078021e: 0000> 5555 -bash-3.2$ vme dump 0x780200 0x78021f 00780200: 0000 0000 1ec8 5555 0000 0000 0000 5555 00780210: 0000 0000 364e 5555 0000 0000 eeac 5555 Was it ever tested and used (in on-line SW, for example)? -> it may work for only write from TTCrx side and read from VME side -> the EDIF (see 1.3) file may not work, need a new installation for Spartan 01.05.2013 ---------- The "partition master" PC is still called "astra" The names of SBCs changed: Old_name -> New_name sbccmx00 -> sbccmx-00 sbccmx01 -> sbccmx-01 Use PuTTY to connect to sbccmx-00.cern.ch source /afs/cern.ch/work/l/laughron/public/l1calo/scripts/login/.lxplus_bashrc vme scan vme dump 0x780000 0x7801ff vme edit 0x780040 vme dump 0x780040 0x780044 "ye_rw80" test RW register in CMX_VAT "ye_rw82" test RW register in CMX_VAT "ye_ro84" test RO register in CMX_ALG "1010101111001101", -- "abcd" "ye_rw86" test RW register in CMX_ALG vme edit 0x780080 7. Study ACE interface: ======================= 7.1 Ian ACE interface --------------------- ENTITY cmm_ace_interface IS -- PCB signal PCB component Description PORT( (1) addr_vme : IN std_logic_vector (16 DOWNTO 1); -- VMEA 74LVT574 buffered VME address (2) clk : IN std_logic; -- ACE_CLK U46 OSC 20 MHz XTL clock (5) cmm_done : IN std_logic; -- CMM_DONE U61 configuration done (5) cmms_done : IN std_logic; -- CMMS_DONE U44 configuration done (1) ds : IN std_logic; -- BOARD_DS U71 board DS (+) i2c_done : IN std_logic; -- I2C_DONE U68 i2c_ttc FPGA configuration done (+) int_geoadd : IN std_logic_vector (6 DOWNTO 4); -- INT_GEOADD6-4 U71 comes from U71 (+) int_geoadd_0 : IN std_logic; -- INT_GEOADD0 U71 comes from U71 (2) mpu_brdy_b : IN std_logic; -- MPU_BRDY_B U43 ACE System ACE Controller (2) mpu_irq_b : IN std_logic; -- MPU_IRQ_B U43 ACE System ACE Controller (+) n_fls_rlalgo : IN std_logic; -- FLS_RLALGO U71 comes from U71 (+) ncs : IN std_logic; -- FLASHS_EN* U71 comes from U71 (1) rd_nwr : IN std_logic; -- BWRITE* 74LVT245 VME buffer (2) all_done : OUT std_logic; -- ALL_DONE u19 LED (2) cfg_addr : OUT std_logic_vector (2 DOWNTO 0); -- CFG_ADDR U43 ACE System ACE Controller (2) cfg_mode_pin : OUT std_logic; -- CFG_MODE_PIN U43 ACE System ACE Controller (2) mpu_addr : OUT std_logic_vector (6 DOWNTO 0); -- MPU_ADDR U43 ACE System ACE Controller (2) mpu_ce_b : OUT std_logic; -- MPU_CE_B U43 ACE System ACE Controller (2) mpu_oe : OUT std_logic; -- MPU_OE U43 ACE System ACE Controller (2) mpu_we_b : OUT std_logic; -- MPU_WE_B U43 ACE System ACE Controller (2) n_ace_reset : OUT std_logic; -- ACE_RESET* U43 ACE System ACE Controller (1) data_vme : INOUT std_logic_vector (15 DOWNTO 0); -- VMED 74LVT245 buffered VME data (2) mpu_data : INOUT std_logic_vector (15 DOWNTO 0) -- MPU_DATA U43 ACE System ACE Controller ); VME interface: (1) data_vme : INOUT std_logic_vector (15 DOWNTO 0); -- VMED 74LVT245 buffered VME data (1) addr_vme : IN std_logic_vector (16 DOWNTO 1); -- VMEA 74LVT574 buffered VME address (+) int_geoadd : IN std_logic_vector (6 DOWNTO 4); -- INT_GEOADD6-4 U71 comes from U71 (+) int_geoadd_0 : IN std_logic; -- INT_GEOADD0 U71 comes from U71 (1) rd_nwr : IN std_logic; -- BWRITE* 74LVT245 VME buffer (1) ds : IN std_logic; -- BOARD_DS U71 board DS ACE interface: (2) mpu_addr : OUT std_logic_vector (6 DOWNTO 0); -- MPU_ADDR U43 ACE (2) mpu_data : INOUT std_logic_vector (15 DOWNTO 0) -- MPU_DATA U43 ACE (2) clk : IN std_logic; -- ACE_CLK U46 OSC 20 MHz XTL clock (2) n_ace_reset : OUT std_logic; -- ACE_RESET* U43 ACE (2) mpu_ce_b : OUT std_logic; -- MPU_CE_B U43 ACE (2) mpu_we_b : OUT std_logic; -- MPU_WE_B U43 ACE (2) mpu_oe : OUT std_logic; -- MPU_OE U43 ACE (2) mpu_irq_b : IN std_logic; -- MPU_IRQ_B U43 ACE (2) mpu_brdy_b : IN std_logic; -- MPU_BRDY_B U43 ACE (2) cfg_addr : OUT std_logic_vector (2 DOWNTO 0); -- CFG_ADDR U43 ACE (2) cfg_mode_pin : OUT std_logic; -- CFG_MODE_PIN U43 ACE Control from vme_interface: (+) n_fls_rlalgo : IN std_logic; -- FLS_RLALGO U71 comes from U71 (+) ncs : IN std_logic; -- FLASHS_EN* U71 comes from U71 Status from FPGA: (5) cmm_done : IN std_logic; -- CMM_DONE U61 configuration done (5) cmms_done : IN std_logic; -- CMMS_DONE U44 configuration done (+) i2c_done : IN std_logic; -- I2C_DONE U68 i2c_ttc FPGA configuration done Status to LED: (2) all_done : OUT std_logic; -- ALL_DONE u19 LED Signal generation: - all_done <= cmm_done and cmms_done and i2c_done; on VAT only all_done <= cmm_done; this signal is unrelated to the cmm_ace_interface as such... - n_ace_reset => ACERST_L (ACE chip reset pin 33 RESET*) The entire System ACE CF controller device can be reset by asserting the RESET* pin of the System ACE CF Controller. System ACE CF controller reset (active Low; needs to be active for three clock cycles) reloads FPGAs n_ace_reset <= n_fls_rlalgo; n_fls_rlalgo - from vme_interface vme_interface -> gen_rlalgo -> fls_rlalgo <= '1'; n_fls_rlalgo -> FLSRLALG -> comes to ACE interface n_fls_rlalgo fls_rlalgo <= '1'; generated by writing '1' to bit 10 of 00006 RW ControlPulseReg - ncs => FLASHSEN, generated in vme_interface flashs_en <= '0'; flashs_en => FLASHSEN, this is actually VME ncs for ACE CPLD. Hold active ('0') as that chip does it's own decoding. - cfg_mode_pin <= '1'; CFGMODEPIN: when '1' start the configuration immediately after reset - cfg_addr comes from geo_decode: GEOADD to CFG_ADDR conversion; now set to cfg_addr <= "000"; Design structure: - cmm_ace_interface (cmm_ace_interface_struct.vhd) <- package - vme_cmm (vme_cmm.vhd) - geo_decode (geo_decode_rtl.vhd) - GEOADD to CFG_ADDR conversion - mpi_ctrl (mpi_ctrl_fsm.vhd) - FSM (started by "go" from mpu_iface_go) - mpu_iface_go (mpu_iface_go_rtl.vhd) - Asserts 'go' when 'our_address' is written to from VME - transcvr (transcvr_rtl.vhd) - mpu_data tranciever - ff_e (ff_e_rtl.vhd) - flip-flop, async reset, clocked on rising edge. - reg_e (reg_e_rtl.vhd) - Register with async reset - vme_inreg (vme_inreg_rtl.vhd) - 00300, 00302, 00304 - vme_outreg (vme_outreg_rtl.vhd) - 00306, 00308 - geo_decode - suppose to conver the INT_GEOADD6-4 and INT_GEOADD0 to the CFG_ADDR geoadd <= int_geoadd_0 & int_geoadd; when "0000" => cfg_addr <= "000"; -- e/gamma crate when "0001" => cfg_addr <= "000"; -- e/gamma crate when "0010" => cfg_addr <= "000"; -- e/gamma crate when "0011" => cfg_addr <= "001"; -- e/gamma system when "1000" => cfg_addr <= "010"; -- tau crate when "1001" => cfg_addr <= "010"; -- tau crate when "1010" => cfg_addr <= "010"; -- tau crate when "1011" => cfg_addr <= "011"; -- tau system when "0100" => cfg_addr <= "100"; -- energy crate when "0101" => cfg_addr <= "101"; -- energy system when "1100" => cfg_addr <= "110"; -- jet-hit crate when "1101" => cfg_addr <= "111"; -- jet-hit system looks like the conversion table is not correct and is commented and the CFG_ADDR is set to 000 cfg_addr <= "000"; - mpi_ctrl - FSM (started by "go" from mpu_iface_go) nrst <= not rst_slv(0); from 00304 RW ia_ace_rst - mpu_iface_go - Asserts 'go' when 'our_address' is written to from VME (and statred mpi_ctrl) constant our_address: integer := ia_ace_ctrl; -- 0300 (ncs => FLASHSEN, in vme_interface: flashs_en => FLASHSEN, flashs_en <= '0';) Registers: 00300 RW ia_ace_ctrl 16-bit -> cmm_ace_interface -> vme_inreg (I6) - VME register, all bits are inputs to board (q) q => ctrl_1x, rdnwr_sel_unreg <= not ctrl_1x(15); -> n_mpwe10 mpa <= ctrl_1x(14 downto 8); mpd_out <= mpd_out_msb & ctrl_1x(7 downto 0); mpd_out_msb - q output of 8-bit 00302 RW ia_ace_d_msb 00302 RW ia_ace_d_msb 8-bit -> cmm_ace_interface -> vme_inreg (I7) - VME register, all bits are inputs to board (q) q => mpd_out_msb - for mpd_out 00304 RW ia_ace_rst 1-bit -> cmm_ace_interface -> vme_inreg (I8) - VME register, all bits are inputs to board (q) q => rst_slv nrst <= not rst_slv(0); - for mpi_ctrl FSM 00306 RO ia_ace_out 16-bit -> cmm_ace_interface -> vme_outreg (I4) - data_in => mpd_in_held, <- MPDATA from XILINX System ACE chip) 00308 RO ia_ace_stats 9-bit -> cmm_ace_interface -> vme_outreg (I5) - data_in => status, status <= mpirq & "0000000" & mpbrdy; mpirq <= mpu_irq_b; <- MPIRQ from XILINX System ACE chip mpbrdy <= mpu_brdy_b; <- MPBRDY from XILINX System ACE chip 00058 RO SystemAceVMEIf System Ace VME Interface -> not implemented in vme_interface, implemented in cmm_ace_interface - This register is reserved for VME control of the System Ace device (firmware version) - decoded in CMM_VMEdecoder -> n_sysace_en, but not used - implemented in cmm_ace_interface -> I10 : vme_outreg ; fw_rev <= "00000011"; set to 3 write "0200" to 00006 RW ControlPulseReg - Reset ACE chip vme dump 0x780300 0x78030a vme edit 0x780300 00f5 000a 7.2 JEM ACE interface (from Uli): --------------------------------- Test card address: 0x780000-0x7FFFFE GEOADD(6:4) and GEOADD(0) set to <111><1> -> e/γ Crate-CMM CMM1 in slot 20 0x00780000-0x007FFFFE The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x700000-0x77FFFE 20 CMM1 0x780000-0x7FFFFE 4 JEM 0 0x800000-0x87FFFE "1|000_0|000_000|0_0000_0000_000|0" 5 JEM 1 0x880000-0x8FFFFE ... ..... ... 18 JEM 14 0xF00000-0xF7FFFE 19 JEM 15 0xF80000-0xFFFFFE Implementing JEM ACE interface on VAT card ------------------------------------------ - source file "vme": http://www.staff.uni-mainz.de/uschaefe/browsable/_VHDL_Projects/Sources/control-13.vhd - package "jem_pkg": http://www.staff.uni-mainz.de/uschaefe/browsable/_VHDL_Projects/Sources/JEM/JemLib.vhd - Process "Check Syntax" completed successfully - Process "Synthesize - XST" completed successfully (warnings) - VME_CONTROL and ACE_CONTROL signals decription - understanding JEM-VAT PCB signal mapping - instantiate control-13.vhd into cmx_ace_test (use modified cmx_vat), finally Check Syntax is OK - Synthesize: ERROR:Xst:1706 - Unit : port > of logic node > has no source ERROR:Xst:1706 - Unit : port > of logic node > has no source ERROR:Xst:1847 - Design checking failed D: I followed the instructions given below, but it doesn't work ERROR:Xst:1706 - Unit : port of logic node <_n0000> has no source ERROR:Xst:1847 - Design checking failed To get around this error, you will have to change the XST FSM (Finite State Machine) options. Do this, right-click on “Synthesis-XST” in the center left panel in Project Navigator. Select “Properties”. Once in the “Process Properties” menu, select the “HDL Options” tab. Then, click on the drop-menu of “FSM Encoding Algorithm”. Change the value from “Auto” to “None”. For some reason, XST is too smart in “Auto” mode and optimizes out the logic that drives the step_pulse signal. -> errors due to "inout" pin declaration (canpt do pin assignment in instantiation) while they are "in" pins ACE_CONTROL(5) - MPBRDY CPLD_BUS(6) - - change these pins to explicitly "in" - Synthesizeed, implemented and generate programming file - Transfer bit files for FPGAs programming to ASTRA (lxplus) using WinSCP ASTRA -> /afs/cern.ch/user/e/ermoline/cmx_ace_test.bit Spartan3 -> C:\My Docs\Work\MSU\Upgrade\CMX firmware\cmx_test\cmx_ace_test\cmx_ace_test.bit - Use X-Win32 to connect to ASTRA - open terminal on ASTRA and: source impact.sh impact - Assign new configuration file to Spartan3 -> /afs/cern.ch/user/e/ermoline/cmx_ace_test.bit - Use PuTTY to connect to sbccmx00.cern.ch source /afs/cern.ch/work/l/laughron/public/l1calo/scripts/login/.lxplus_bashrc sbccmx00.cern.ch> vme scan Region 0: 800000 to 87ffff (this is JEM0 GEO_ADDR=>"00000", for VAT-CMM was Region 0: 780000 to 7fffff) Region 1: c00000 to c00fff Region 2: d00000 to d00fff - sbccmx00.cern.ch> vme dump 0x800000 0x80000f 00800000: 100e 1201 0005 0002 0000 0000 0000 0000 -- JEM VME registers: constant av_MODULE_ID_A_REG: integer:=0;--RO module type; IMODULE_A<="0001_0000_0000_1110"; "100e" constant av_MODULE_ID_B_REG: integer:=2;--RO revision number & serial number; board_revision:= x"12"; serial_number:= "0000_0001"; "1201" constant av_VERSION_REG: integer:=4;--RO firmware version number; IVERSION:=x"0005"; constant av_STATUS_REG: integer:=6;--RO status register (not implemented: TTC clock available & handling of DONE pins not yet know) chksum &MPBRDY&"00000"&CPLD_BUS_6&"0"; CPLD_BUS_6 set to '1'; x"0002" constant av_geo_REG: integer:=8;--RO geo add register; if IADDR_VME=av_geo_REG then rtmp:=x"00"&"000"&GEO_ADDR; end if; -- constant av_CFG_MASK_REG: integer:=16;--RW mask FPGAs for configuration x0010 constant av_FPGA_RESET_REG: integer:=18;--WO? reset FPGA(s) x0012 constant av_CFG_REG: integer:=20;--configuration register -> not implemented x0014 constant av_DONE_REG: integer:=32;--done register -> not implemented x0020 constant av_can_REG: integer:=40;--RW can register x0028 constant av_jtag_REG: integer:=64;-- -> not implemented x0040 constant av_jconf_REG: integer:=66;-- -> not implemented - test reg 40 - x0028 - av_can_reg bit 0 (CAN_RESET) and bit 1 (can_select_prog_b) CAN_RESET connected to CANRST_L on VAT card for test can_select_prog_b connected to CANRD_L on VAT card for test -bash-3.2$ vme edit 0x800028 00800028: 0000> ffff -bash-3.2$ vme dump 0x800000 0x8000ff 00800000: 100e 1201 0005 0002 0000 0000 0000 0000 00800010: 0000 0000 0000 0000 0000 0000 0000 0000 00800020: 0000 0000 0000 0000 0003 0000 0000 0000 | - test reg 16 - x0010 - av_CFG_MASK_REG conf_en:= vme_data(0); ? not used outside chip? encf:=vme_data(13); cpld_bus(cp_enab_conf)<=encf; CPLD_BUS(2) resall:=vme_data(14); ? not used outside chip? nenace:=vme_data(15); ? not used outside chip? -bash-3.2$ vme edit 0x800010 00800010: 0000> ffff -bash-3.2$ vme dump 0x800000 0x8000ff 00800000: 100e 1201 0005 0002 0000 0000 0000 0000 00800010: e001 0000 0000 0000 0000 0000 0000 0000 | | - Modification on the VAT card - ACECLK signal discinnectred from QZ2-3 on PCB, now only connected are Spartan(D8) and SystemACE(93) - in Spartan (CMX_ACE_TEST) ACE_CLK set as output (was input before) - System ACE address MPADDR(6 downto 0) and data MPDATA(15 downto 0) from Spartan: MPADDR <= VMEADDR(6 downto 1)&'0'; MPDATA <= VMEDATA; - Instal VAT, reload Spartan with new design, after power-on: - STATLED (LD12) off - configuration is in an IDLE state. - ERRLED (LD11) blinking - no CompactFlash device was found when the CompactFlash - STATUS2 (LD10) off - XTAL as clock source on the TTCDec card - CLK40 (LD9) on - clock is running - On TTCDec card: LED DS1 (TTCREADY) is OFF - Add TTCrx control signals in Spartan (CMX_ACE_TEST): TTCPD <= '1'; -- Mode select TTCPD P/D = 1: Protected Mode (Normal Running Mode) TTCCLKSE <= '1'; -- Clock select TTCCLKSE ClkSel = 1: Select TTCrx as clock source, S1=TTCReady, S2 =1 TTCRST_L <= '1'; -- TTC reset TTCRST_L - reload Spartan with new design, after power-on: - STATLED (LD12) OFF - configuration is in an IDLE state. - ERRLED (LD11) blinking - no CompactFlash device was found when the CompactFlash - STATUS2 (LD10) ON - TTCrx as clock source on the TTCDec card - CLK40 (LD9) ON - clock is running - On TTCDec card: LED DS1 (TTCREADY) is ON 7.3 Study ACE chip access ------------------------- JEM address decoding: -- JEM 0 0x800000-0x87FFFE "1|000_0|000_000|0_0000_0000_000|0" GEO_ADDR(4 downto 0) set to "00000" address_match:='0'; if ("1" & GEO_ADDR(3 downto 0))=vme_addr(23 downto 19) then address_match:='1'; end if; -- "1000_0" GEO_ADDR(4 downto 0) set to "00000" brdsel:=address_match and not vme_nds0; -- chipsel selects addresses "1|000_0|000_000|x" -> 0x800000-0x801FFE - internal board addresses, otherwise chipsel:='0' chipsel:=brdsel; if vme_addr(18 downto 13)/="000000" then chipsel:='0'; end if; -- "1000_0000_000x" -> 0x800000-0x801FFE -- cpld_bus(cp_acc_jtag)<='1' when "1|000_0|000_001x" -> 0x802000-0x803FFF -> JTAG access if vme_addr(18 downto 13)="000001" and brdsel ='1' then cpld_bus(cp_acc_jtag)<='1'; else cpld_bus(cp_acc_jtag)<='0';end if; IADDR_VME<=conv_integer(vme_addr(14 downto 1)&'0'); -- "1000_0000_0xxx_xxxx_xxxx_xxx0" ACE chip access decoding? if '1' & GEO_ADDR(3 downto 0)&"00001" /=vme_addr(23 downto 14) then acyc:=0; end if; -- "1|000_0|000_01|xx" 0x800000-0x801FFE -> internal board addresses 0x802000-0x803FFF -> JTAG access 0x804000-0x807FFF -> MPU access in System ACE ST66 inserted - POR_BYPASS (IC44-108) set to '0' (ST66 inserted), Built-in POR circuit is used to reset the device From: Yuri Ermoline Sent: 08 May 2013 17:51 To: Daniel Edmunds; Philippe Laurens; Raymond Brock; Seth Caughron; Wojtek Fedorko Subject: Registers Now, with Uli’s VHDL model adapted to the VAT card hardware and compiled in the Spartan FPGA on VAT card the following VME registers implemented in the Spartan FPGA are available: -bash-3.2$ vme dump 0x800000 0x8000ff 00800000: 100e 1201 0005 0002 0000 0000 0000 0000 00800010: 0000 0000 0000 0000 0000 0000 0000 0000 00800020: 0000 0000 0000 0000 0003 0000 0000 0000 Address 00: 16-bit RO module type: x "100e" Address 02: 16-bit RO revision number & serial number: x1201" Address 04: 16-bit RO firmware version number; x"0005" Address 06: 16-bit RO status register: x"0002" Address 28: 2-bit RW status register: x"0002" Above registers you may try to access from your software, running on the SBC in 6U crate. XILINX System ACE registers 00-2E (on page 20 and following of the System ACE manual) are mapped to the VME addressed staring from x”00804000”, but they are not yet accessible on the VAT hardware. Here is some explanation from Uli: …it is directly mapped into VME space. Registers as documented in the ACE manual, word wide access used, however due to even addressing scheme of VME bus you'll have to use the addresses as specified for byte wide access in the ACE manual... From: Yuri Ermoline Sent: 09 May 2013 18:56 To: Daniel Edmunds; Philippe Laurens; Raymond Brock; Seth Caughron; Wojtek Fedorko Cc: 'Schäfer, Dr. Ulrich'; ian.brawn@stfc.ac.uk; Bruce M Barnett Subject: RE: Registers Finally I’ve succeeded to adapt the Uli’s FW to VAT card HW and can now access (read and write) the XILINX System ACE registers. System ACE registers 00-2E are mapped to the VME addressed staring from x”00804000”, In order to use WORD mode, you have to write x“0001” to BUSMODEREG Register at x00804000 Then you can read registers: -bash-3.2$ vme dump 0x804000 0x8040ff 00804000: 0001 0000 4200 0001 0000 0000 0000 0000 00804010: 0000 0000 0000 100c 0000 0000 0000 0000 00804020: 0000 0000 0000 0000 0000 0000 0000 0000 Here is an example of writing to MPULBAREG Register (x”00804010” and x”00804012”) and then reading from it: -bash-3.2$ vme edit 0x804010 00804010: 0000> 9876 00804012: 0000> 5432 00804014: 0000> -bash-3.2$ vme dump 0x804000 0x8040ff 00804000: 0001 0000 4200 0001 0000 0000 0000 0000 00804010: 9876 0432 0000 100c 0000 0000 0000 0000 00804020: 0000 0000 0000 0000 0000 0000 0000 0000 The 6U crate with the VAT card is ON and you can play with it. 7.4 Adapting Uli’s code to work with Ian CMM code ------------------------------------------------- - use Uli model for ACE (VME, control-13.vhd) instead of Ian model; - implement 00058 RO SystemAceVMEIf System Ace VME Interface (firmware version) - add to vme_interface - decoded in CMM_VMEdecoder -> n_sysace_en - add COMPONENT ReadOnly_Reg (I6) to vme_interface - reg 00058 RO SystemAceVMEIf - remove all unused VME registers from Uli model - remove av_MODULE_ID_A_REG RO module type x0000 - remove av_MODULE_ID_B_REG RO revision number & serial number x0002 - remove av_VERSION_REG RO firmware version number x0004 - remove av_STATUS_REG RO status register x0006 - remove av_geo_REG RO geoadd register x0008 - remove av_CFG_MASK_REG RW mask FPGAs for configuration x0010 - remove av_FPGA_RESET_REG WO? reset FPGA(s) x0012 - remove av_can_REG RW can register x0028 - change address_match generation Was: (in VME access, GEO_ADDR(4 downto 0) set to "00000") -- JEM 0 0x800000-0x87FFFE "1|000_0|000_000|0_0000_0000_000|0" GEO_ADDR(4 downto 0) set to "00000" if ("1"&geo_addr(3 downto 1)&geo_addr(0))=vme_addr(23 downto 19) then address_match:='1'; end if; -- "1000_0" (0x800000) Now: if ('0'&"111"&geo_addr(0))=vme_addr(23 downto 19) then address_match:='1'; end if; -- "0111_1" (0x78xxxx) -- Was: (in ace control, GEO_ADDR(4 downto 0) set to "00000") if '1'&geo_addr(3 downto 1)&geo_addr(0)&"00001" /=vme_addr(23 downto 14) then acyc:=0; end if; -- x804000-0x807FFF -> MPU access Now: if '0'&"111"&geo_addr(0)&"00001" /=vme_addr(23 downto 14) then acyc:=0; end if; -- "0111_1000_01" (0x784xxx) - in cmx_vat.vhd: BRDDS output from VAT card -> only BRDDSACE used now!!! -- BRDDSINT <= BRDDSVME or BRDDSACE; -- VME(BRDDSVME)and ACE(BRDDSACE) "out", TTC "in" (BRDDS) BRDDSINT <= BRDDSACE; -- VME(BRDDSVME)and ACE(BRDDSACE) "out", TTC "in" (BRDDS) BRDDS <= BRDDSINT; -- BRDDS output from VAT card - VME accesses -bash-3.2$ vme dump 0x780000 0x7800ff 00780000: 2417 095a 001e 001e 00b0 0000 0000 0000 00780010: 0000 0000 0000 0000 0000 0000 0000 0000 00780020: 0000 0000 0000 0000 0000 0000 0000 0000 00780030: 0000 0000 0000 0000 0000 0000 0000 0000 00780040: 0000 0000 0001 0001 0001 0001 0001 0001 00780050: 0001 0001 0007 002b 0003 0003 0003 0000 00780060: 0000 0000 0000 0000 0000 0000 0000 0000 00780070: 0000 0000 0000 0000 0000 0000 0000 0000 00780080: 0000 0000 abcd e6e6 e6e6 e6e6 e6e6 e6e6 -bash-3.2$ vme edit 0x780080 00780080: 0000> 1234 -- "ye_rw80" test RW register in CMX_VAT 00780082: 0000> 5678 -- "ye_rw82" test RW register in CMX_VAT 00780084: abcd> -- "ye_ro84" test RO register in CMX_ALG "1010101111001101", -- "abcd" -bash-3.2$ vme dump 0x780000 0x7800ff 00780000: 2417 095a 001e 001e 00b0 0000 0000 0000 00780010: 0000 0000 0000 0000 0000 0000 0000 0000 00780020: 0000 0000 0000 0000 0000 0000 0000 0000 00780030: 0000 0000 0000 0000 0000 0000 0000 0000 00780040: 0000 0000 0001 0001 0001 0001 0001 0001 00780050: 0001 0001 0007 002b 0003 0003 0003 0000 00780060: 0000 0000 0000 0000 0000 0000 0000 0000 00780070: 0000 0000 0000 0000 0000 0000 0000 0000 00780080: 1234 5678 abcd e6e6 e6e6 e6e6 e6e6 e6e6 -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0000 0000 0000 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 000c 0000 0000 0000 0000 00784020: 0000 0000 0000 0000 0000 0000 0000 0000 00784030: 0000 0000 0000 0000 0000 0000 0000 0000 00784040: 0000 0000 0000 0000 0000 0000 0000 0000 00784050: 0000 0000 0000 0000 0000 0000 0000 0000 00784060: 0000 0000 0000 0000 0000 0000 0000 0000 00784070: 0000 0000 0000 0000 0000 0000 0000 0000 -bash-3.2$ vme edit 0x784000 00784000: 0000> 0001 00784002: 0000> -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 100c 0000 0000 0000 0000 00784020: 0000 0000 0000 0000 0000 0000 0000 0000 00784030: 0000 0000 0000 0000 0000 0000 0000 0000 00784040: 0000 0000 0000 0000 0000 0000 0000 0000 00784050: 0000 0000 0000 0000 0000 0000 0000 0000 00784060: 0000 0000 0000 0000 0000 0000 0000 0000 00784070: 0000 0000 0000 0000 0000 0000 0000 0000 -bash-3.2$ vme edit 0x784010 00784010: 0000> 9876 00784012: 0000> 5432 00784014: 0000> -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 00784010: 9876 0432 0000 100c 0000 0000 0000 0000 00784020: 0000 0000 0000 0000 0000 0000 0000 0000 00784030: 0000 0000 0000 0000 0000 0000 0000 0000 00784040: 0000 0000 0000 0000 0000 0000 0000 0000 00784050: 0000 0000 0000 0000 0000 0000 0000 0000 00784060: 0000 0000 0000 0000 0000 0000 0000 0000 00784070: 0000 0000 0000 0000 0000 0000 0000 0000 8. CMX_ALG ========== 8.1 Firmware inventory -------------------- CMM FW from Ian: ---------------- C:\My Docs\Work\MSU\Upgrade\CMM\CMM FW\Ian_vhdl: - cmm_vme_cpld - FW for the VME interface on CMM, used and modified for Spartan - cmm_main_hdl - FW for srate and systen Virtex-E FPGAs (?) + packages, etc... - cmm_ace_cpld - FW for ACE CPLD, not used, replaced by Uli FW VAT FW: ------- C:\My Docs\Work\MSU\Upgrade\VAT\VAT Firmware - cmx_test: - cmx_vat_test - Test design for Spartan-3AN (XC3S400AN-4FTG256C) to light the LED "DONE" (LD5) and the LEDs LD1-LD4 - test configuration - cmx_alg_test - Test design for CMX_ALG FPGA (XC6VLX75T-1FFG784C) to drive the ST<5..1>) of bank 15 '0' and '1' - cmx_ace_test - Test of Uli's "vme" with ACE access - cmx_vme - VME/ACE/TTC interface in FPGA Spartan-3AN - wrapper for IPB's "vme_interface", "cmm_ace_interface" and "i2c_ttc" - cmx_alg - implementation of the VME interface for the Virtex6 FPGA XC6VLX75T-1FFG784C - cmx_vat - VME/ACE/TTC interface in FPGA Spartan-3AN - wrapper for IPB's - use Uli model for ACE (VME, control-13.vhd) instead of Ian model; CMX FW: ------- C:\My Docs\Work\MSU\Upgrade\CMX\CMX Firmware - cmx_support - CMX Support FPGA 8.2 CMX_ALG VME access implementation ------------------------------------- Create cmx_alg.vhd and instantiate vme_outreg ("ye_ro84" = "abcd") and vme_inreg ("ye_rw86") 13.08.2013 Refreshig - what is on the VAT card ----------------------------------- - Use PuTTY to connect to sbccmx00.cern.ch source /afs/cern.ch/work/l/laughron/public/l1calo/scripts/login/.lxplus_bashrc sbccmx00.cern.ch> vme scan Region 0: 800000 to 87ffff (this is JEM0 GEO_ADDR=>"00000", for VAT-CMM was Region 0: 780000 to 7fffff) Region 1: c00000 to c00fff Region 2: d00000 to d00fff -> looks like the CMX_VAT FPGA is configured with the cmx_ace_test.bit file on power-on... - Use X-Win32 to connect to ASTRA, there are configuration files: - cmx_vat_Ian.bit - Initial CMX_VAT FPGA implementation using Ian ACE interface (same as cmx_vme) ? - cmx_ace_test.bit - Test of Uli's "vme" with ACE access - cmx_vat_Uli.bit - Initial CMX_VAT FPGA implementation using Uli ACE interface (ACE address 0x804000) - cmx_vat.bit - CMX_VAT FPGA implementation using Uli ACE interface (ACE address 0x784xxx) - cmx_alg.bit - implementation of the VME interface for the Virtex6 FPGA XC6VLX75T-1FFG784C - open terminal on ASTRA and: source impact.sh impact - Assign configuration files - Spartan3 -> /afs/cern.ch/user/e/ermoline/cmx_vat.bit - Virtex 6 -> /afs/cern.ch/user/e/ermoline/cmx_alg.bit - -bash-3.2$ vme scan Region 0: 780000 to 7fffff Region 1: c00000 to c00fff Region 2: d00000 to d00fff "ye_rw80" test RW register in CMX_VAT "ye_rw82" test RW register in CMX_VAT "ye_ro84" test RO register in CMX_ALG "1010101111001101", -- "abcd" "ye_rw86" test RW register in CMX_ALG vme edit 0x780080 Test Ian VME interface: ----------------------- -bash-3.2$ vme dump 0x780000 0x7800ff 00780000: 2417 095a 001e 001e 00b0 0000 0000 0000 00780010: 0000 0000 0000 0000 0000 0000 0000 0000 00780020: 0000 0000 0000 0000 0000 0000 0000 0000 00780030: 0000 0000 0000 0000 0000 0000 0000 0000 00780040: 0000 0000 0001 0001 0001 0001 0001 0001 00780050: 0001 0001 0007 002b 0003 0003 0003 0000 00780060: 0000 0000 0000 0000 0000 0000 0000 0000 00780070: 0000 0000 0000 0000 0000 0000 0000 0000 00780080: 0000 0000 abcd 0000 0000 0000 0000 0000 -bash-3.2$ vme edit 0x780080 00780080: 0000> 1234 -- "ye_rw80" test RW register in CMX_VAT 00780082: 0000> 5678 -- "ye_rw82" test RW register in CMX_VAT 00780084: abcd> -- "ye_ro84" test RO register in CMX_ALG "1010101111001101", -- "abcd" 00780086: 0000> fefe -- "ye_rw86" test RW register in CMX_ALG 00780088: fefe> -bash-3.2$ vme dump 0x780000 0x780100 00780000: 2417 095a 001e 001e 00b0 0000 0000 0000 00780010: 0000 0000 0000 0000 0000 0000 0000 0000 00780020: 0000 0000 0000 0000 0000 0000 0000 0000 00780030: 0000 0000 0000 0000 0000 0000 0000 0000 00780040: 0000 0000 0001 0001 0001 0001 0001 0001 00780050: 0001 0001 0007 002b 0003 0003 0003 0000 00780060: 0000 0000 0000 0000 0000 0000 0000 0000 00780070: 0000 0000 0000 0000 0000 0000 0000 0000 00780080: 1234 5678 abcd fefe fefe fefe fefe fefe -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0000 0000 0000 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 000c 0000 0000 0000 0000 Test Uli ACE/MPU interface: --------------------------- -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0000 0000 0000 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 000c 0000 0000 0000 0000 -bash-3.2$ vme edit 0x784000 00784000: 0000> 0001 00784002: 0000> -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 100c 0000 0000 0000 0000 -bash-3.2$ vme edit 0x784010 00784010: 0000> 9876 00784012: 0000> 5432 00784014: 0000> -bash-3.2$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 00784010: 9876 0432 0000 100c 0000 0000 0000 0000 8.3 CMM VME addressing scheme: ------------------------------ The addressing scheme divides the 24 bit (16 Megabyte) VME-- address space into two, and allocates the upper half (0x00800000 - 00FFFFFE) to JEMs and CPMs. This gives each JEM or CPM the maximum possible address space in our system of 80000x bytes (512K bytes). The CMMs are placed just below this (they need only 40000x bytes but are allocated 80000x bytes for simplicity) at 700000x and 780000x The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x00700000-0x0077FFFE : VME address (23 DOWNTO 1): 0x700000 -> "0111_0000_0000_0000_0000_000x" 20 CMM1 0x00780000-0x007FFFFE : VME address (23 DOWNTO 1): 0x780000 -> "0111_1000_0000_0000_0000_000x" GEOADD(0) - 0 (Left) 1 (Right) VME-- backplane interface signals (see 2.1): Signal mnemonic Name Component Daughtercard --------------- ---- --------- ------------ A01-A23 Address bus 74LVT574 input fuffer, clock BDS0 (inverted BDS0*) 74LVT574 outputs (for U71, U70, U68) D00-D15 Data bus 74LVT245 TS transceiver, OE*-BRDSEL_N, T/R-BWRITE* 74LVT245 A inout DS* Data Strobe 74LVT245 TS transceiver, output - BDS0* delayed BDS0* from DELAY (DS0_INT*) - for U71 only? WRITE* Write 74LVT245 TS transceiver, output - BWRITE* 74LVT574 outputs (for U71, U70, U68) DTACK* Data acknowledge SN74F38D OK output BOARD_DS from U71 The VME address decoding in VAT FPGA - vme_interface: ----------------------------------------------------- component VME_INTERFACE vme_address : IN std_logic_vector (23 DOWNTO 1); -- Address bus VMEADDR vme_data : INOUT std_logic_vector (15 DOWNTO 0) n_ds0_int : IN std_logic; -- DS strobe VMEDS_L n_write : IN std_logic; -- VME Write VMEWR_L board_ds : OUT std_logic; -- (Data ack) BRDDS -- board_ds <= n_board_select_int nor n_ds0_int; brdsel_n : OUT std_logic; -- Board select BRDSEL_L - input_latch : to Latch VME inputs because some VME masters remove them before the cycle is over if (n_ds0_int = '1') then -- n_ds0_int => VMEDS_L address_ltchd <= vme_address; -- latch at n_ds0_int = '0' vme_address(23 DOWNTO 1); n_write_ltchd <= n_write; -- latch at n_ds0_int = '0' - CMM_Board_Select: generates "board_select_n" signal using address_ltchd(23 DOWNTO 19): if (addressbus(23 downto 20)="0111") and (addressbus(19)= geoaddr_0) then board_select_n <= '0'; board_select_p <= '1'; -> board_select_n comes to U61 (ncs : IN std_logic; -- BRDSEL_N (U61-E15 - from U71-F16) - CMM_VMEdecoder: generates enable bits using address_ltchd(18 DOWNTO 1); enable bits used in Registers (ControlGeo, RW_Reg, ReadOnly_Reg) -- convert (address_ltchd(18 downto 1)&'0') to integer, ignoring LSB: address_int <= to_integer(unsigned(address_ltchd(18 downto 1) & '0')); -- compare VME address to the arrress in the package allproc: process (brdsel_p_int, address_int) is begin ye_rw80_en <= '1'; -- YE 0080 if (brdsel_p_int = '1') then -- board_select_p => brdsel_p_int (CMM_Board_Select) case (address_int) is when ye_rw80 => ye_rw80_en <= '0'; -- constant ye_rw80: integer:= 16#0080#; -- test RW register when others => null; end case; end if; end process; - gen_nds : generates single-tick data strobe at beginning of n_ds0_int used in Registers (ControlGeo, RW_Reg), gen_rlalgo, pulse_reg_a if (clk40'event and clk40 = '1') then n_ds0_old <= n_ds0_int; if (n_ds0_int = '0' and n_ds0_old = '1') then nds <= '0'; else nds <= '1'; - board_ds is only generated in vme_interface entity RW_Reg is generic( width : integer := 16 ); port( clk40 : in std_logic; nds : in std_logic; -- from gen_nds n_control_en : in std_logic; -- from CMM_VMEdecoder n_write : in std_logic; -- VME Write VMEWR_L nreset : in std_logic; regvalue : out std_logic_vector (width-1 downto 0); databusboard : inout std_logic_vector (15 downto 0) ); entity ReadOnly_Reg is generic( bus_msb : integer := 15; bus_lsb : integer := 0 ); port( n_regenable : in std_logic; -- from CMM_VMEdecoder regvalue : in std_logic_vector (bus_msb downto bus_lsb); n_write : in std_logic; databus : inout std_logic_vector (bus_msb downto bus_lsb) ); The VME address decoding in VAT FPGA - i2c_ttc: ----------------------------------------------- component I2C_TTC is addr_vme : IN std_logic_vector (16 DOWNTO 1); -- Address bus VMEADDR data_vme : INOUT std_logic_vector (15 DOWNTO 0); -- Data bus VMEDATA ds : IN std_logic; -- (Data ack) BRDDS rd_nwr : IN std_logic; -- VME Write VMEWR_L COMPONENT i2c_vme PORT ( -- Name PCB signal addr_vme : IN std_logic_vector (16 DOWNTO 1); -- Address bus VMEADDR data_to_vme : IN std_logic_vector (7 DOWNTO 0); data_vme : INOUT std_logic_vector (15 DOWNTO 0) -- Data bus VMEDATA ds : IN std_logic ; -- (Data ack) BRDDS ncs : IN std_logic ; -- ncs <= '0'; -- bypass the VME_CPLD decoding.... rd_nwr : IN std_logic ; -- VME Write VMEWR_L entity vme_inreg is generic( ia_vme : integer := 0; -- constant from vme_cmm package (or VME decoder, if implemented) width : integer := 16 ); port( ncs : in std_logic; ds : in std_logic; data_vme : inout std_logic_vector (15 downto 0); q : out std_logic_vector (width-1 downto 0); rd_nwr : in std_logic; addr_vme : in std_logic_vector (15 downto 0) ); entity vme_outreg is generic( ia_vme : integer := 0; -- constant from vme_cmm package (or VME decoder, if implemented) width : integer := 16 ); port( addr_vme : in std_logic_vector (15 downto 0); ncs : in std_logic; rd_nwr : in std_logic; ds : in std_logic; data_in : in std_logic_vector (width-1 downto 0); data_vme : out std_logic_vector (15 downto 0) ); Comparison of RW_Reg in vme_interface and vme_inreg in i2c_vme -------------------------------------------------------------- entity RW_Reg is -- vme_interface generic( width : integer := 16 ); port( clk40 : in std_logic; nds : in std_logic; -- from gen_nds n_control_en : in std_logic; -- from CMM_VMEdecoder n_write : in std_logic; -- VME Write VMEWR_L nreset : in std_logic; regvalue : out std_logic_vector (width-1 downto 0); databusboard : inout std_logic_vector (15 downto 0) ); entity vme_inreg is -- i2c_vme generic( ia_vme : integer := 0; -- constant from vme_cmm package (or VME decoder, if implemented) -- n_control_en in vme_interface width : integer := 16 ); port( ncs : in std_logic; -- ncs <= '0'; -- bypass the VME_CPLD decoding...., so, not used ds : in std_logic; data_vme : inout std_logic_vector (15 downto 0); q : out std_logic_vector (width-1 downto 0); rd_nwr : in std_logic; addr_vme : in std_logic_vector (15 downto 0) ); 8.4 Study of Ian VHDL for CP crate FPGA XCV1000E-6FG860 (U61): -------------------------------------------------------------- - Create project for Virtex6 XC6VLX550T in FF1759 package: C:\My Docs\Work\MSU\Upgrade\L1Calo\CMM\CMM Firmware\Ian_vhdl\cmm_cpcrt_vc_struct - Ian VHDL sources in: C:\My Docs\Work\MSU\Upgrade\L1Calo\CMM\CMM Firmware\Ian_vhdl\cmm_main_hdl\hdl - add top file: cmm_cpcrt_vc_struct.vhd - add all files and synthesize ENTITY cmm_cpcrt_vc IS addr_vme : IN std_logic_vector (16 DOWNTO 1); data_vme : INOUT std_logic_vector (15 DOWNTO 0) ds : IN std_logic; -- BOARD_DS (U61-C17 - from U71-F15, DTACK* generation) ncs : IN std_logic; -- BRDSEL_N (U61-E15 - from U71-F16) rd_nwr : IN std_logic; -- BWRITE* (U61-A17, from VME buffer) -- to compare: component VME_INTERFACE (U71) vme_address : IN std_logic_vector (23 DOWNTO 1); -- Address bus VMEADDR vme_data : INOUT std_logic_vector (15 DOWNTO 0) n_ds0_int : IN std_logic; -- DS strobe VMEDS_L n_write : IN std_logic; -- VME Write VMEWR_L board_ds : OUT std_logic; -- (Data ack) BRDDS -- board_ds <= n_board_select_int nor n_ds0_int; brdsel_n : OUT std_logic; -- Board select BRDSEL_L -- ENTITY vme_latch IS -- Added in the hope of reducing VME instability reported from CERN. addr_vme : IN std_logic_vector (16 DOWNTO 1); ds : IN std_logic; ncs : IN std_logic; rd_nwr : IN std_logic; addr_vme_ltchd : OUT std_logic_vector (16 DOWNTO 1); ncs_ltchd : OUT std_logic; rd_nwr_ltchd : OUT std_logic latchproc: process (ds, ncs, rd_nwr, addr_vme) begin if (ds = '0') then ncs_ltchd <= ncs; rd_nwr_ltchd <= rd_nwr; addr_vme_ltchd <= addr_vme; end if; end process; - VME interface in cmm_cpcrt_vc : ENTITY cpcrt_vme_blank IS addr_vme : IN std_logic_vector (16 DOWNTO 1); data_vme : INOUT std_logic_vector (15 DOWNTO 0) ds : IN std_logic; -- BOARD_DS (U61-C17 - from U71-F15, DTACK* generation) ncs : IN std_logic; -- BRDSEL_N (U61-E15 - from U71-F16) rd_nwr : IN std_logic; -- BWRITE* (U61-A17, from VME buffer) I5 : cpcrt_vme_blank PORT MAP ( addr_vme => addr_vme_ltchd, ds => ds, ncs => ncs_ltchd, rd_nwr => rd_nwr_ltchd, data_vme => data_vme ); - used: vme_inreg, vme_outreg - same as in the i2c_vme 8.5 Work on vme-interface for the BASE FPGA ------------------------------------------- IC_XC6LVX550T Xilinx Virtex-6 FPGA BGA 1760 pin SMD Xilinx Part No. XC6VLX550T-2FFG1759C - made top VHDL model for CMX_BASE using .ucf file from Dan C:\My Docs\Work\MSU\Upgrade\CMX\CMX Firmware\cmx_base\cmx_base_sources - component CMX_BASE_VME_BSPT to generate BOARDDS and BRDSELN for cmm_cpcrt_vc 9. DCS interface (CANbus) ======================== Common Merger Module, Version 1.8, 18-Jul-2008 ---------------------------------------------- 5.3 CAN The Common Merger Module uses a Fujitsu MB90F594 microcontroller [2.14] as an interface to the Controlled Area Network Bus (CANBus) in the processing crate. The architecture is used throughout the calorimeter trigger, and allows the module to pass voltage and temperature information via the Timing Control Module to the ATLAS Detector Control System (DCS). (Via same controller in the TCM module) The Common Merger Module has eight parameters to be monitored, comprising the three voltages generated on-board (see 5.6), three FPGA temperatures, and two G-Link temperatures. The microcontroller can be programmed from the front panel and reset both from the front panel and via VME. The temperatures of the three FPGAs on the module, the ‘system’, ‘crate’, and ‘I2C’ devices, are obtained using a MAX1668 Serial Master Bus chip (SMBus) controlled by the microcontroller. There are three connections between the microcontroller and this device, namely clock, data and an alert. The Alert pin is connected to interrupt input INT0 (p76) on the microcontroller. If an FPGA temperature exceeds a pre-determined temperature value, an exception routine deals with the problem. The voltage levels are measured using the 10-bit Analogue to Digital Converter in the microcontroller. Channels 0, 1 and 2 are connected respectively to the 1V5, 2V5 and 3V3 supplies, with the reference voltage connected to the +5V supply. The temperatures of the two HP G-Link (DAQ and ROI) chips are obtained using two LM35D temperature sensors bonded to the heat sinks. The outputs from the temperature sensors are connected to channels 3 and 4 of the 10-bit Analogue to Digital Converter. Port 7 of the microcontroller is connected to the geographical address input pins from the backplane. From this input, delays are calculated to prevent two microcontrollers on the same bus transmitting at the same time, thus preventing bus contention. Port 8 is connected to a fixed pull-up, pull-down resistor network which is a fixed code for the CMM module type. The details of this code can be found in addressing scheme for the TTC and Busy network [2.13]. For the CMM the value is set to 0x04. Port 1 of the microcontroller is connected via a buffer to the VME data bus. This is used for a software version code which can be read by VME when required. The enable signal for this buffer is controlled by the VME CPLD. Port 2 is connected to buffered signals from the VME CPLD. These control signals enable access to software version register (default) or other registers within the microcontroller. -- DCS interfaces on CMM: - Analog inputs from the CMM board: - The temperatures of the three FPGAs: MAX1668 Serial Master Bus chip (SMBus) controlled by the microcontroller reads DXP-DXN from 3 FPGAs - The voltage levels (1V8, 2V5, 3V3): are measured using the 10-bit Analogue to Digital Converter in the microcontroller (AN0-AN2) - The temperatures of the two HP G-Link (DAQ and ROI) chips (not used in CMX) two LM35D temperature sensors bonded to the heat sinks - Crate backplane: - CANbus - 2 pins CANP+CANN via CAN controller interface PCA82C250 - Front panel: - RS232 interface - 9-pin D-type connector DCS: (after discussionon DCS on June 19th 2013) ----------------------------------------------- . Implement on CMX a DCS part layout which allow to use a daughter card (Dan) . extra connectors and route all signal via these connectors . Check the difference between FUJITSU MB90F594GPF/G (CMM BOM) and MB90F594A (CMM photo) . look into documentation MB90F591A/G(5V±5%) MB90F594A/G(5V±10%) - Flash ROM product (591 and 594 - different Memory space map) http://www.fujitsu.com/global/services/microelectronics/product/micom/support/suffix/mb90590.html http://www.spansion.com/Support/microcontrollers/differenceofpartsnumber/Pages/mb90590.aspx MB90F594A - MB90F594G FLASH sector composition change CAN bit rate condition change Decrease for unnecessary radiation noise F2MC-16LX MB90590-590G Series_DS07-13704-5E: CAN bit timing setting : MB90xxx : TSEG2 >= RSJW+2TQ MB90xxxG: TSEG2 >= RSJW hm90590-cm44-10105-5e: page 294 . look at the other boards (JEM, PPM, TCM, ROD) . CPM: MB90F591A (our proto) . JEM: MB90F591A (schematics), MB90F594A (board) . PPM: MB90F594 (schematics), MB90F594A (board) . TCM: MB90F594 (schematics), MB90F594APF (BOM) . ROD: MB90F594 (schematics), . ask Ian about it and about supplier -> NO supplier . FUJITSU MB90F594G uC test on PPM . order from Club Electronics (20 pc - 1 week; EUR 87.50/pc) . ask for a possibility to order 1 pc - 2 pieces at 166.60 EUR each . new request - 5pc/48.00 or 25 pc/45.00 . ordered 5 uC - send email to Yves on 11.07.13 (Yves replied) -> MB90F594GPF -> received . CAN DC for PPM from Heidelberg . asked, Paul -> 2 PCBs available, promised to pass to Bruce + connectors -> reveived . order DC parts (Farnell), CAN chip (Mouser) -> received . CAN DC assembly at CERN . prepare docs (BOM, photos, schematics, NO an assembly file!) . asked Paul for an assembly file, got it - sent for assembly to the CERN PCB WS -> got it . Discuss with Bruce a possibility of check components . test in Heidelberg - asked Paul, not possible . DCS setup in Bld.104, CANbus microcontroller programming, CANbus card test . Possible problems: . card: soldering, connectors, components? . version G (not A, however, om CPM - also G) - there is a build switch specific to the version A/G 25 Oct 2013: Hello Paul and Bruce, What I've understood from the email exchange and discussions with Bruce over last days: 1. It can be a hardware fault of the CAN-Microcontroller card, e.g.: - there is a bit different - higher - connector (unreliable connection between the CAN-Microcontroller card and the PPM motherboard), - possible bad soldering of the components on the card, - wrong components (however, not crystal, otherwise we can’t ever download the code) - but I used the BOM from Hedelberg. 2. It can be a faulty microcontroller chip itself: - but we can download the code, it means this part works, - we can't connect to the chip via CANbus from the microcontroller on the TCM module - one may conclude this part doesn’t work. This is very unlikely from my point of view, as far as I remember, once we were able to communicate with our card... However, who knows, maybe want we saw was not generated by the microcontroller itself... 3. We ordered and soldered microcontroller MB90F594G (G-version), while on all other cards on PPM and TCM there are MB90F594A (A-version): - the A and G versions indeed have some differences: http://www.spansion.com/Support/microcontrollers/differenceofpartsnumber/Pages/mb90590.aspx (CAN bit rate condition change: look at page 5 of the attached datasheet) - as Bruce said, there is a build switch specific to the version A/G in Softune, therefore a common code can be compiled individually for out card (Bruce tried this without success) - maybe G (on our card) and A (on original PPM card) cannot be connected to the same CANbus controlled by TCM? - maybe G (on our card) and A (on TCM) can't communicate? However, in the test rig CPM crate there are A version on the TCM, CMMs and JEMs and G version in the CPM modules... How the DCS CAN code was compiled for the CMP crate, was the A/G build switch used during compilation? How the CANbus works in the CPM crate - is it possible to have a look in the PVSS? Paul, would it be possible to run PVSS locally, in the lab 104 - without disturbing you all the times we make a small modification or try different option? Are you going to CERN next week? Can we try to look into the CPM crate CANbus via PVSS? In a case everything is OK in the CPM crate, it may indicate that the A/G difference is not a reason. I'm alsoing look into possibility to make another card with the A version of the microcontroller on it: - I got 2 PCBs from Heidelberg, one was assembled, second is still available, - asked supplier about availability, price and delivery time, - asked Heidelberg about proper connectors, - components can be ordered and delivered. It may takes 2-3 weeks before we will get the new assembled card, however... . FUJITSU MB90F594A uC test on PPM (one more DC PCB available) . order from Club Electronics - send email to Yves on 25.10.13 about availability - ordered finally 43 parts . ask Heidelberg about proper connectors (our - 3307, their - 4301) - send email to Paul and Klaus on 25.10.13 . order DC parts (Farnell), CAN chip (Mouser) . CAN DC assembly at CERN . Version A tested on Dec.19 2013 - works! 9.1 PPM CANbus microcontroller programming: ------------------------------------------- From Bruce (18-19/12/2012): There are no Accemic zip files on the HP laptop. But you can find v 2.6 on the accemic web site (after registering.) The processor type is MB90F594G. The serial setup is as attached. I also checked that the brainbox-rs232 PCMCIA card works under windows 7. Well - it finds drivers. Ok - the laptop (PCATL1CUK1) now is running under windows 7. The Accemic MDE is installed (COM4 - I sent the attachment yesterday.) It starts properly and Windows found the driver for the serial-card. https://twiki.cern.ch/twiki/bin/viewauth/Atlas/LevelOneCaloTriggerCAN Ask Heidelberg about connection to uC - Klaus Schmitt Heidelberg CANbus card programming alone (connect to PS and Dsub9 connector) - works! A PC with a PCMCIA port and a long extension for the serial DB-9 connection to the modules. At CERN this is usually the l1calo laptop from 3150. Reprogramming the Kernel: 1) First put the module in programming mode. 2) Start the Accemic software on laptop 3) Select the "Preferences" menu and in the "Select Processor" window that pops up: Manufacturer: Fujitsu Type: MB90F594G (NOTE At Birmingham pre-pre-production module in ROD and CMM it is possibly the 591) click "Next" 4) In the "Setup Processor" window that pops up: PLL Factor: 4 (the speed should be set to 57600 Bits/s at CERN and 9600 Bits/s at Birmingham). click "Download Kernel". This will download the Accemic kernel to the CAN chip. Note: after downloading the kernel a pop-up window will appear asking you to set it into either "burn in" or "normal" mode. This is just a reminder to set programming or running mode for the module so just click OK. 5) Put the CAN chip into running mode. Loading the CAN code: So the kernel is loaded and the PC is still connected to the module 1) Select the File->Load File menu in Accemic 2) Navigate to the L1C-X-Y-Z.abs file and click "open". This will load the CAN code onto the chip 3) Select the Tools->Automatic Start menu. 4) Tick the automatic start after reset box. The code will now start running everytime the module powers up. 5) Select the Start->Run menu (or use the play icon). This will start the code running. 6) Disconnect from the module. 9.2 CAN code programming: ------------------------- The general idea is to load the same version of the CAN code on all CAN chips in all L1Calo modules. Since 1/10/2013 the CAN code is able to find the correct crate ID for all TCMs(CP/JEP and ROD/PPM types). The compilation is made using from softtune (docu to be inserted above - have some handwritten notes) MB90F594A and MB90F594G - There is a build switch (in Softune) specific to the version A or G. 9.3 PVSS/CANbus/TCM: -------------------- PC/W7/PVSS/RemoteTermibal, Paul-Slava, access uC on the TCM and on the PPM https://twiki.cern.ch/twiki/bin/viewauth/Atlas/LevelOneCaloCernTestRig#DCS_Setup The ATLTDQLV1LCS project runs as a service on the PC: pc-l1c-dcs-00. Users (one at a time!) can log on directly to the PC and run the project. If you want to connect via a remote desktop then you need to be registered as a remote desktop user (ask Taylor/Murrough). -> sent email -> now can login - PVSSII 3.8 in C:\ETM\PVSS2\3.8 ToDo for MSU: ------------- - install Accemic software on my Fujitsy Lifebook W/XP (or on HP EliteBook W7 ?) - find a serial cable (brainbox-rs232 PCMCIA card?) or fund out how to use USB cable (80.02.09.001.9 - ADAPTATEUR USB-RS232) - install Softune on my HP EliteBook and learn how to use it 10. CMX test plans ================== CMX test plan 05.07.2013 ============= 0. Preparation of the MSU test rig ---------------------------------- Aim: Prepare the environment for the CMX tests at MSU for initial tests of the prototype and production modules HW: 9U L1Calo crate, VMM+SBC, TCM, CMM, JEM 6U crate, SBC, TTCvi, TTCvx, LTP PC to run SW (TDAQ, L1Calo, XILINX) SW: TDAQ SW, L1CaloFramework, XILINX ISE loading test vectors to JEM, playback data in JEM, capture in the CMM, compare to the expected data TBD: setup for JEM, move to MSU, setup at MSU ----------------------- 1. Initial tests at MSU ----------------------- Dat: Sep-Dec 2013 Aim: power supplies and clocks function as expected all 3 FPGAs can be configured HW: Power supply, PC to run XILINX SW SW: XILINX ISE TBD: ------------------------ 2. Tests at MSU test rig ------------------------ Dat: Sep-Dec 2013 Aim: Prototype testing VME read/write to registers works Data transfer from JEM to CMX works - 400 backplane inputs slow speed I/O through front and back LVDS HW: MSU test rig SW: MSU test rig SW + test SW? FW: CMX test FW, optical link loop TBD: MSU test rig SW setup at MSU assignment of FW tasks in support of CMX initial testing Possible issues: I/O through the 400 backplane inputs only one JEM, to test all CMX input lines have to be moving the JEM around a lot? Some other way of feeding in data? -------------------------------- 3. Tests at CERN L1Calo test lab -------------------------------- Dat: Sep-Dec 2013 Aim: Integration of the CMX in the L1Calo environment System and integration testing HW: L1Calo test rig and DCS environment SW: L1Calo test rig SW (TDAQ SW, L1CaloFramework, DCS) FW: CMX FW, patterns available for L1Topo TBD: assignment of FW tasks in support of CMX system testing Coordination with L1Topo designers Possible issues: only few processor modules available ----------------------------- 4. Tests in the counting room ----------------------------- Dat: Jan-Feb 2014 Aim: Full-rack test of backplane signals at 160 MHz before a PRR Production testing HW: USA15 L1Calo system SW: USA15 L1Calo SW FW: CMX FW TBD: Coordination of this is critical and will involve many players ------------------------------------------------------------ 5. Final commissioning and replacement of CMM cards with CMX ------------------------------------------------------------ Dat: Apr-Jun 2014 Aim: Test in the USA15 L1Calo system during shutdown Wojtek ------ 1.Establish the system clocking for Base and Topo FPGAs: 0.5 day 1.Lock on 40.08 MHZ clocks DSKW_1 and 2, as well as 320, propagate MMCMs lock and recovered clocks on the debug pins. measure jitter properties. 2.Capture the TTCdec signals on Base and Topo FPGA’s 2.Backplane connectivity and timing measurement: 3 days 1.Static pattern capture 2.Measure relative time delays between signals P0-23 and 24 from a single JEM. 3.Test data transfer at 160Mbps from a single JEM, moving the JEM periodically from slot to slot. 4.Variety of patterns, including stress patterns 5.Detect parity error 3.Low speed serial TX connectivity test; 1 day 1.establish reference 120.00MHz clock lock for the PLLs on the two GTX’s 2.use the G-Link emulation firmware module to send out a pre-defined or predictable data pattern on 4 fibers and use a test receiver to flag errors. 4.High speed serial Base RX/ Topo TX connectivity: 3 days. 1.establish PLL lock for the reference clocks on BASE and Topo Function 2.send out a test PRNG test pattern from the Base FPGA and capture on Topo FPGA 1.Pattern conforming to CMX->Topo protocol 2.8b/10b and CRC monitoring to flag errors 3.Test all (2 ribbons) outputs and (3 ribbons) inputs 5.LVDS RTM (crate ->system) communication at 80 Mbps: 1 day 1.loopback tests each of the 3 rear 27 pair connectors tested in both directions (A->B, A->C, B->A, C->A) 1.PRNG patterns, stress patterns 2.Detect Parity error 6.LVDS frontpanel (CTP) communication at 40 Mbps: 1 day 1.Base-> Topo and Topo->Base test pattern transmission from one connector to the other when either of the connector is driven or receiving from Base or Topo. 7.BASE->TOPO GPIO link: 0.5 day 1.Test LVDS and direct connectivity 2. Push rate CMX test plans 16.12.2013 ============== Preparation: ------------ Dec 16-20 Test rig mechanical assembly at MSU, DCS tests continues at 104 at CERN 23-27 Test rig computing infrastructure setup at MSU Initial: -------- Jan 06-10 Test rig software setup 13-17 CMX prototypes arrive to MSU Assembly, grounding, power, clock, JTAG/CF FPGA config BSPT FW, Dummy bit files for FPGAs (based on .ucf and .vhd top file) 20-24 Pawel and Wojciech at MSU Test data interfaces standalone in loopback Test FW for BSPT, Base and Topo FPGAs, Special FW for JEM CMX/JEM software 27-31 Pawel and Wojciech at MSU (L1Calo/L1Topo test week in 104) Test data interfaces standalone in loopback First CMX ready for shipping to CERN Second CMX tests at MSU Pre PRR: -------- Feb 03-07 Wojtek arrive to CERN with first CMX Preparation in 104, CMX tests in 104 Second CMX sent to CERN 10-14 Preparation for the tests in USA15 (L1Calo/L1Topo test week in 104) CMX tests in 104 Second CMX arrives to CERN 17-21 First and second CMX tests in 104 Preparation for the tests in USA15 24-28 Two CMX tests in USA15 with JEMs Post PRR: --------- Mar 03-07 H PRR preparation (USA15 shielding wall istallation on the first floor till end of March) 10-14 H PRR, Two CMX tests in 104, two CMX tests at MSU 17-21 H PRR outcome 24-28 H CMX ready for production 11. CMX firmware ================ IC_XC3S400A Xilinx Spartan 3A FPGA BGA 400 pin SMD Xilinx Part No.XC3S400A-4FGG400C PROM - xcf04s (to generate a .mcs file) 11.1 CMX_BSPT VCCAUX level, Card Serial Number, Resets ------------------------------------------------------ Spartan-3 Generation Configuration User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG332 (v1.6) October 26, 2009 p.77: VCCAUX Level In the Spartan-3A and Spartan-3A DSP platforms, the VCCAUX level is programmable as either 2.5V (default) or 3.3V. The user specifies the value in the software through the CONFIG VCCAUX=2.5 or CONFIG VCCAUX=3.3 constraint. In the Spartan-3AN platform, the user must set CONFIG VCCAUX=3.3 (default) for using the In-System Flash. The Spartan-3 and Spartan-3E families have a fixed VCCAUX at 2.5V. Inputs for the 5-bit CMX Card Serial Number Jumpers JMP101:JMP105 set the 5-bit CMX Card Serial Number. These 5 jumper run from from BSPT Input-Only pins to ground. There are no pull-up resistors on these lines - thus the pull-ups internal to the BSPT for these pins must be turned on. From the Spartan 3A data sheet these internal pull-ups should be in the range of 5.1 to 33.1 k Ohm. XILINX Constraints Guide UG625 (v. 13.4) January 18, 2012 p.215 Resets in CMM: -------------- TOP inputs: VMERST_L(System reset) and PONRST(Power ON reset) -> VME_INTERFACE(n_sysreset and pon_reset) outputs: ACERST_L (from gen_rlalgo), TTCRST_L (from pulse_reg_a), CANRST_L, BRDRST_L, DLLRST_L => all outputs from reset register VME_INTERFACE: generation: nreset <= n_sysreset and not pon_reset; -> gen_rlalgo(nreset), pulse_reg_a(nreset) output:n_board_reset <= n_board_reset_internal (from pulse_reg_a(0)) -> to BRDRST_L gen_rlalgo: input:nreset => idle; "n_fls_rlalgo" generation -> System ACE controller reset (ACERST_L) - 60 CLK40 cycles | (ACERST_L) - min 3 ACE clock cycles, ACE clock - 10 MHz (4 CLK40 cycles) -> ACERST_L = min 12 CLK40 cycles | pulse_reg_a: input:nreset => init; "resets" generation - 20 CLK40 cycles | => n_board_reset_internal -> to Registers(n_board_reset) - output from FPGA (BRDRST_L) | Module Resets Register => n_ttc_reset, -> output from FPGA (TTCRST_L) - Reset_B of TTCrx | => n_can_reset, -> output from FPGA (CANRST_L) | => n_reset_i2c, -> to VME_INTERFACE:I2CRESET -> I2C_TTC:input:n_i2c_rst | Registers: input:n_board_reset (from pulse_reg_a) -> ControlGeo (reset and set the GEOADDR) - but this is NOT on power-up! I2C_TTC: input:n_i2c_rst -> i2c_rst <= not n_i2c_rst; -> ff, i2c_clk_gen, i2c_ttc_engine, i2c_vme, sr_i2c_input, sr_ps, ttc_dump Resets in CMX: -------------- TOP inputs: OCB_SYS_RESET_B. NO power-on reset! outputs: ACE_RESET_B, TTC_RESET_B CMX_BSPT_VME: input: n_sysreset; n_board_reset <= n_board_reset_internal (from Module Resets Register) output: n_board_reset - not used 11.2 CMX LVDS links control --------------------------- On Thu, Feb 6, 2014 at 2:42 PM, Wojciech Tadeusz Fedorko wrote: Pawel and I looked briefly at the schematics and documentation and while we don't claim to fully understand the board oversight logic we think we do understand the implications form the BF/TP perspective. The proposal for the setup and some questions below... We understand that the lines X_REQ_X_INPUT meaning is that when 'low' a given FPGA is requesting to drive a given LVDS IO - is that correct? For instance if both BF and TP FPGAs drive their _REQ_CTP_1_INPUT to '0' then this means that both are requesting CTP cable 1 to be configured as output. In this case BS FPGA coupled to the board oversight logic configures the transcievers so that output of one of the FPGAs is output on the LVDS lines but there is no contention on the data lines for the FPGAs that got 'suppressed'. E.g. if BF FPGA 'wins' the transcievers are not driving the corresponding lines of the TP FPGA - is this correct? All drivers mentioned below will be configured as LVCMOS25 with DRIVE=2 (mA - this is the weakest setting available) All inputs mentioned below will be configured as LVCMOS25 with PULLUP constraint (from ug361: "For input (IBUF) buffers, the input can also have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. This feature can be invoked by adding the following possible constraint values to the relevant net of the buffers: • PULLUP • PULLDOWN • KEEPER" We propose to statically drive the following lines in the BF and TP 'safety' FW: BF/TP_REQ_CTP_(2 downto 1)_INPUT <= '0' BF/TP_DOUT_CTP(65 downto 0)<='0' BF_REQ_CABLE_(3 downto 1)_INPUT<='0' (BF) D_CBL_zz_B BF/TP_LED_REQ_(4 downto 0) <= '0' Both BF and TP connections to BS are configured as outputs on BF and TP and driven to '0'; they must be unconfigured or configured as inputs on BSPT: BF/TP_TO_FROMBSPT(7 downto 0)<='0' We propose to configure SLINK_RETURN lines for now as direct signalling outputs on BF and direct signalling inputs on the TP (same formats/settings as above). These are the only connections between the two FPGAs correct? On BF: BF_TO_TP_(DAQ/ROI)_SLINK_RETURN(DIR/CMP)<='0' Two test VME will be implemented RO and RW on both BF and TP FPGAs All backplane inputs to BF will be configured as LVCMOS25 inputs with weak PULLUP. Readout will be made available on 32 VME registers and chipscope cores and also forwarded to 10 debug outputs using multiplexers utilizing VIO chipscope core. -----Original Message----- From: Yuri Ermoline Sent: 06 March 2014 10:52 Subject: RE: Current version of BSPT firmware I've prepared and download to the XILINX directory on msul1c.pa.msu.edu a "safe" version of FW to load into the BSPT PROM. "cmx_bspt_safe_20140306" In the BSPT FPGA the output control signals are set to static values regardless of the input signals in such a way that: - all LVDS transceivers (CTP and Backplane) are configured as inputs to the CMX, - all level translators are configured as inputs to the BSPT/BF/TP FPGAs and are disabled. In this way the BF and TP FPGAs may remain unconfigured after BSPT configuration from the PROM on power up. Please, look into attached file cmx_bspt.vhd for the translators and transceivers direction and enable pins settings in the -- CTP LVDS Connectors Management -- YE 06.03.2014 "safe" BSPT configuration -- Backplane LVDS Cables Managements -- YE 06.03.2014 "safe" BSPT configuration All other BSPT configurations (e.g. - for the LVDS tests) can be downloaded directly to the BSPT FPGA via JTAG. For the next version I will implement the control logic in the BSPT FPGA according to the Dan's proposal: CTP Connector Management Logic in the BSPT FPGA: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/23_ctp_connector_bstp_logic.pdf Backplane LVDS Cable Management: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/21_backplane_cable_management.pdf I will also implement status registers to read the status of all control bits. CTP LVDS Connectors Management - CTP LVDS control logic in the BSPT FPGA ------------------------------------------------------------------------ Upon power up the BSPT FPGA generates signal BSPT_RUNNING_OK_B - output from BSPT FPGA, set to '0' after configuration: BSPT_RUNNING_OK_B <= '0'; The control logic in the BSPT firmware listens to the following 8(6) input signals: ALLOW_BUSSED_IO BF_CONFIG_DONE TP_CONFIG_DONE TP_FPGA_INSTALLED_B BF_REQ_CTP_1_INPUT TP_REQ_CTP_1_INPUT BF_REQ_CTP_2_INPUT TP_REQ_CTP_2_INPUT The control logic in the BSPT firmware generates 10 output signals according to the Dan's proposal: CTP Connector Management Logic in the BSPT FPGA: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/23_ctp_connector_bstp_logic.pdf CTP_1_TRNCVR_DIR CTP_1_BF_TRNSLT_DIR BSPT_CTP_1_BF_TRNSLT_OE_B CTP_1_TP_TRNSLT_DIR BSPT_CTP_1_TP_TRNSLT_OE_B CTP_2_TRNCVR_DIR CTP_2_BF_TRNSLT_DIR BSPT_CTP_2_BF_TRNSLT_OE_B CTP_2_TP_TRNSLT_DIR BSPT_CTP_2_TP_TRNSLT_OE_B BF_CONFIG_DONE and TP_CONFIG_DONE -> Module Satus 1 Register RO_0008 bits 5 and 6 Backplane LVDS Cables Managements - Backplane LVDS control logic in the BSPT FPGA --------------------------------------------------------------------------------- The control logic in the BSPT firmware listens to the following 5(3) signals: ALLOW_BUSSED_IO BF_CONFIG_DONE BF_REQ_CABLE_1_INPUT BF_REQ_CABLE_2_INPUT BF_REQ_CABLE_3_INPUT The control logic in the BSPT firmware generates the 9 control signals according to the Dan's proposal: Backplane LVDS Cable Management: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/21_backplane_cable_management.pdf CABLE_1_TRNCVR_DIR CABLE_1_TRNSLT_DIR BSPT_CABLE_1_TRNSLT_OE_B CABLE_2_TRNCVR_DIR CABLE_2_TRNSLT_DIR BSPT_CABLE_2_TRNSLT_OE_B CABLE_3_TRNCVR_DIR CABLE_3_TRNSLT_DIR BSPT_CABLE_3_TRNSLT_OE_B All other bits are in LinkStatus1 RO_000C and LinkStatus2 RO_000E registers 11.3 Work on ACE interface for the BSPT FPGA (Test on the VAT card ------------------------------------------------------------------ - ace reset generation after power-on Resetting the System ACE CF Controller: There are three types of reset of the System ACE CF controller: 1. Power-on-reset (POR) 2. Device reset 3. Configuration controller reset Power-on-Reset (POR): The POR circuit is used to reset the entire System ACE CF controller device upon device power up. The built-in POR circuit can be bypassed in order to use an external POR circuit. To bypass the built-in POR circuit, the POR_BYPASS pin should be set to ‘1’ and the POR_RESET pin is used to reset the device. System ACE reset generation: - ace reset generation after configuration (NOT afetr power-on... ?) "The built-in POR circuit is used to reset the entire System ACE CF controller device upon device power up" remove pwr-up and pwr_down signals process(CLK40) variable acerst : std_logic :='0'; variable tick : std_logic_vector(13 downto 0):=(others=>'0'); -- set counter to zero begin if rising_edge(CLK40) then tick := tick + '1'; -- increment counter if tick = "10000100000000" then -- "10_0001_0000_0000" (8162+256)*25ns=210us !!! acerst := '1'; -- end of ACE reset signal end if; end if; ACERESET_L <= acerst; end process; ACE control (ACE_CLK is 10 MHz: CLK40 divided by 4) System ACE VME addresses: set now to 0x780080-0x7800DF -bash-4.1$ vme edit 0x780080 00780080: 0000> 0001 -bash-4.1$ vme edit 0x780090 00780090: 0000> 9876 00780092: 0000> 5432 -bash-4.1$ vme dump 0x780000 0x7801ff 00780080: 0001 0000 0200 0001 0000 0000 0000 0000 (00780084 - STATUSREG<15:0> - OK mode=1, cfgaddr=000) 00780090: 9876 0432 0000 100c 0000 0000 0000 0000 VME - BSPT communications with the System ACE (software) - TBD!!! 11.4 Work on vme-interface for the BSPT FPGA -------------------------------------------- - made top VHDL model for CMX_BSPT using .ucf file from Dan C:\My Docs\Work\MSU\Upgrade\CMX\CMX Firmware\cmx_bspt\cmx_bspt_sources - instantiate VME interface component - define signals for VME_INTERFACE component - connect all VME components I/O to CMX_BSPT I/O - define VME control output signals and VME-OCB Bus Management signals generated by BSPT FPGA - set all other outputs to defined values - create TB for CMX_BSPT (CMX_BSPT_TB) - 10.01.2014 tested VME interface only - modify module_idsn - Module ID and SN RO_0000 (CMM_VMEdecoder, Registers, signal n_module_idsn_en, module_idsn_val, - modify module_revision - Module HW/FW Revisions RO_0002 - modify module_cntrl - Module Control Register RW_0004 - modified all vme_interface - check with TB Test on the VAT card: - make a design CMX_BSPT_VAT_TEST and instantiate CMX_BSPT_VAT_TEST_VMEIF : CMX_BSPT_VME - generate programming file (cmx_bspt_vat_test.bit) - transfer cmx_bspt_vat_test.bit to ASTRA (lxplus) using WinSCP - to connect to ASTRA run astra.xw32; then open terminal on ASTRA and "source impact.sh"; then run "impact" - initilize chain; assign new configuration file to Spartan3 -> cmx_bspt_vat_test.bit; program FPGA - connect to sbccmx-00.cern.ch: -bash-3.2$ source vme.sh <<<<< - change since 06.02.2014 # Setup for VME myOsVersion="slc6" myGccVersion="gcc47" myTdaqVersion="tdaq-05-00-01" export L1CALO_ROOT=/afs/cern.ch/atlas/project/tdaq/level1/calo/testrig/releases/tdaq-05-00-01/LVL1/l1calo/installed/ source /afs/cern.ch/atlas/project/tdaq/level1/calo/testrig/releases/tdaq-05-00-01/LVL1/l1calo/scripts/login/.lxplus_bashrc myArchitecture="i686" -bash-3.2$ vme scan Region 0: 780000 to 7fffff - read first -bash-3.2$ vme dump 0x780000 0x78000f 00780000: 1a33 0101 001e 001e 5555 aaaa aaaa ffff 00000 RO ModuleIDSN = "1a33" module_idsn_v <= module_sn & module_id; module_sn <= "000" & serial_num(5 downto 1); -> set in VAT to "1a" by jumpers module_id <= X"33"; 00002 RO ModuleRew = "0101" module_rev_v <= module_fwr & module_hwr; module_fwr <= X"01"; module_hwr <= X"01"; 00004 RW ModuleControl = 001e (0000_0000_0001_1110) Bits 4..1 are GEOADD(6-4)&GEOADD0 set in VATto "1111" 00006 RW ModuleResets = "001e" (shall be read back as zero, but not implemented in FW) 00008 RO ModuleStatus1 = "5555" (set in FW to "5555" for test) 0000A RO ModuleStatus2 = "aaaa" (set in FW to "aaaa" for test) 0000C RO FIFOStatus not implemented 0000E reserved Modification of the DTACK generation (Test on the VAT card): - initial state: DTACK is BRDDSVME - board_ds output from Ian VME model + ext. delay of 5 ns (IC25, ST60) - configure Spartan with cmx_vat.bit -bash-4.1$ vme edit 0x780080 00780080: 0000> 1234 00780082: 0000> 5678 -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 2417 095a 001e 001e 0f11 00ff 00ff ffff 00780040: 0000 0000 0001 0001 ffff ffff ffff ffff 00780050: ffff ffff 0007 002b 0003 ff03 ffff 0000 00780080: 1234 5678 5678 ffff ffff ffff ffff ffff -> check Uli's code for ACE access: -bash-4.1$ vme dump 0x784000 0x7840ff 00784000: 0000 0000 0000 0001 0000 0000 0000 0000 00784010: 0000 0000 0000 000c 0000 0000 0000 0000 In order to use WORD mode, you have to write x“0001” to BUSMODEREG Register at x00804000 -bash-4.1$ vme edit 0x784000 00784000: 0000> 0001 -bash-4.1$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 (00784004 - STATUSREG 00784010: 0000 0000 0000 100c 0000 0000 0000 0000 Here is an example of writing to MPULBAREG Register (x”00804010” and x”00804012”) and then reading from it: -bash-4.1$ vme edit 0x784010 00784010: 0000> 9876 00784012: 0000> 5432 -bash-4.1$ vme dump 0x784000 0x7840ff 00784000: 0001 0000 4200 0001 0000 0000 0000 0000 00784010: 9876 0432 0000 100c 0000 0000 0000 0000 - compile cmx_bspt_vat_test.vhd (BRDDS <= BRDDSVME; -- DTACK from VMEIF (Ian) configure Spartan with cmx_bspt_vat_test.bit -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 1a33 0101 001e 001e 5555 aaaa aaaa ffff --> OK - compile cmx_bspt_vat_test.vhd (BRDDS <= not BRDDSACE_L; -- DTACK from ACEIF (Uli) configure Spartan with cmx_bspt_vat_test.bit -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 1a33 0101 001e 511e 5555 aaaa aaaa ffff -> check Uli's code for ACE access: -bash-4.1$ vme dump 0x784000 0x7840ff 00784000: 0000 0000 0000 0001 0000 0000 0000 0000 --> OK 00784010: 0000 0000 0000 000c 0000 0000 0000 0000 All checked... - compile cmx_bspt_vat_test.vhd with -- VME access - DTACK (BRDDS) generation after delay configure Spartan -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 1a33 0101 001e 511e 5555 aaaa aaaa ffff -> check Uli's code for ACE access: OK Use "rw_reg" to make two RW registers at the addresses 000C and 000E and a bunch of 16 registers from 00E0 to 00FE, they are all 16-bit wide and are not connected to the FPGA pins. > From: Philippe Laurens [mailto:laurens@pa.msu.edu] > Sent: 19 February 2014 16:56 > After doing a few manual read and write tests to the BSPT dummy registers, we turned to python to do repeated tests. > From: Philippe Laurens [mailto:laurens@pa.msu.edu] > Sent: 21 February 2014 00:38 > We added a feature to the Random Register Test program to be able to control the mix of read and writes. > It is clear that it is only the writes that sometime fail or initiate temporary problems for the following read(s). The register with errors is "rw_reg" used in CMX_BSPT_VME. The other register is "vme_inreg" used in CMX_BSPT_TTC - "i2c_vme" and in "cmm_cpcrt_vc" Try to make "rw_reg" (000C and 000E) similar to "vme_inreg" - didn't help Try to make new registers 0038 (in CMX_BSPT_VME) and 003A (in CMX_BSPT_TTC - i2c_vme) using "vme_inreg" - WORKS!!! Remove 0038 and 003A and implement 000C, 000E and 16 registers from 00E0 to 00FE using "vme_inreg" (renamed to vme_rw_reg) Array, implemented with vme_rw_array doesnt work Implemented with vme_rw_reg using GENERATE - works with some errors ------------------------------------------------------- From: Philippe Laurens [mailto:laurens@pa.msu.edu] Sent: 25 February 2014 12:23 Subject: How to copy new firmware to msul1c, configure the BSPT FPGA, run the random register test proram --- 1) copy the (zip) file containing the BSPT xilinx project to msul1c. The area holding these files is /home/cmxuser/Xilinx I rename the file to add the date to the file name, e.g. cmx_bspt_20140225.zip if there is more than one for the same day you could use, 20140225_b, 20140225_c, etc 3) run the impact software from a new command window. You first need to run the Xilinx setup script. There is an alias to invoke this script: cmxuser@msul1c<~> Xilinx_setup cmxuser@msul1c<~> impact & --- Note: if the crate (the SBC) has just been powered up, there is one extra step to be done just once: From a command line window, connect to the SBC (no password needed) cmxuser@msul1c<~> ssh root@sbccmx-01.aglt2.org And run Duc's setup script that starts AFS and load the vme drivers. root@sbccmx-01<~>source sbccmx-startup-script.sh --- 6) from a command line window, connect to the SBC (no password needed) cmxuser@msul1c<~> ssh cmxuser@sbccmx-01.aglt2.org 7) Initialize the L1calo software environement cmxuser@sbccmx-01<~>source l1calo_i686.sh Setting up TDAQ Common SW release "tdaq-common-01-23-00" Setting up DQM Common SW release "dqm-common-00-23-00" Setting up DAQ SW release "tdaq-05-00-01" Setting up L1Calo SW development version Setting up gcc-4.7.2 on i686 8) Navigate to the area holding the test program. This is using Duc's shared area between the SBCs and msul1c so that one can easily copy files back and forth. cmxuser@sbccmx-01cd /tmp/common/RandRegTest/ 9) run the test program cmxuser@sbccmx-01python RandRegTest.py -r cmx1_block16_dummy_reg_block.def -t 100 The command above runs 100 test loops on the block of 16 registers from the cmx in slot 20. There are additional register definition files, and more than one set of registers can be combined: -r file1 -r file2 ... cf below for a description of the other program parameters 10) Optional, but typically useful: if you want to save a copy of the screen output, you can use pipe and the 'tee' command, eg. python ... | tee RandRegTest_mytestresults.log ------------------------------------------------------- These are the parameters available in the current version: cmxuser@sbccmx-01python RandRegTest.py RandRegTest V1.3 Starting at Tue Feb 25 18:12:12 ** missing parameter: register address file name ** Usage: python RandRegTest.py -r|--reg_addr register_address_file [-t|--test_loops total_test_loops] [-p|--patrol_loops total_patrol_loops] [-w|--wait_on_error seconds_before_2nd_try] [-z|--init_0x0000] -r register_address_file or --reg_addr register_address_file Specify the name of a file defining the set of registers to test. The content of this file should add members to the array "vme_addr_arr" e.g.: vme_addr_arr += ( "0x0070000c", "0x0070000e" ) This argument is required. -t total_test_loops or --test_loops total_test_loops Specify the desired number of test loops. This argument is optional and the default is 1 test loop. -p total_patrol_loops or --loops total_patrol_loops Specify a desired number of patrol loops for check other registers after having modified each targeted register. Specifying a positive number N will check all registers N times. Specifying a zero will skip all patrol check. Specifying a negative number -N will check randomly chosen N registers. This argument is optional and the default is 1 patrol loop (i.e. check all registers once). -w seconds or --wait_on_error seconds Specify an optional wait period after reading an incorrect value before attempting a second chance read. This argument is optional and the default is no waiting. -z or --init_0x0000 Specify that all registers' content be initialized with 0x0000. This argument is optional and the default is to initialize with random values. ------------------------------------------------------- Try to implement synchronous VME interface based on old design - works for 2 registers Install RandRegTest.py on the SBC in the 6U VME crate with the VAT card - program works Re-working vme interface and check with the random register test proram on VAT card 25.03.2014 - check again what is where: ---------- CMX Firmware\archive\FPGA_BSPT_FW_v1_20140310 - "safe" in PROM on CMX 000C and 000E implemented using vme_rw_reg temporary array of 16-bit RW registers from 0060 to 007E - using vme_rw_reg (generate) temporary array of 16-bit RW registers from 00E0 to 00FE - using vme_rw_array test on CMX in 104: errors Test: after power-up reading -bash-4.1$ vme dump 0x00700000 0x007000ff - CMX#3 in slot 3, BF FPGA only 00700000: 0033 0101 001e 001e f0fa 7744 0000 0000 00008 RO ModuleStatus1 -> f0fa = 1111 0000 1111 1010 - MiniPod345 not installed 0000A RO ModuleStatus2 -> 7744 = 0111 0111 0100 0100 - SFP3 and SFP4 not installed -bash-4.1$ vme dump 0x00780000 0x0078000f - CMX#1 in slot 20, BF and TP FPGAs 00780000: 0033 0101 001e 001e 80ea 4444 0000 0000 00008 RO ModuleStatus1 -> 80ea = 1000 0000 1110 1010 0000A RO ModuleStatus2 -> 4444 = 0100 0100 0100 0100 -- TTCrx access: -bash-4.1$ vme edit 0x780006 - Write 2 to RW_06 (ModuleResets) - Reset TTCrx chip 00700006: 0000> 2 -bash-4.1$ vme edit 0x780030 - Write 0300 to RW_30 (TTCrxControl) - read TTCrx control reg 03 00700030: 0000> 0300 -bash-4.1$ vme edit 0x780032 - Read data from RO_32 (TTCrxStatus) => 93 00700032: 0093> ^C -- SystemACE access: -bash-4.1$ vme dump 0x00780000 0x007800ff - after power-on 00700080: 0000 0000 0000 0000 0000 0000 0000 0000 00700090: 0000 0000 0000 000c 0000 0000 0000 0000 -bash-4.1$ vme edit 0x780080 00700080: 0000> 0001 - set 16-bit WORD access mode -bash-4.1$ vme dump 0x00780000 0x007800ff 00700080: 0001 0000 0200 0001 0000 0000 0000 0000 - 0200 STATUSREG(15:0) bit 9 CFGMODEPIN=1 00700090: 0000 0000 0000 100c 0000 0000 0000 0000 - 100c VERSIONREG(15:0) 16 R Version register = version 1.0.0C -bash-4.1$ vme edit 0x780090 00780090: 1234> 9876 - MPULBAREG(15:0) 16 bits RW 00780092: 0000> 5432 - MPULBAREG(27:16) 12 bits RW -bash-4.1$ vme dump 0x00780000 0x007800ff 00700080: 0001 0000 0200 0001 0000 0000 0000 0000 00700090: 9876 0432 0000 100c 0000 0000 0000 0000 Last version (19.03.2014) - test v2 on CMX 0x0078: 28_2E, 60_7E and E0_FE (Ian design) Test: Configure BSPT FPGA with version 2 -bash-4.1$ vme edit 0x780006 00780006: 0000> 0002 - Reset TTCrx chip -bash-4.1$ vme dump 0x00780000 0x007800ff 00780000: 0133 0201 0002 0002 808a 4444 fffe 0fff 00000 RO ModuleIDSN -> OK 00002 RO ModuleRew -> OK 00004 RW ModuleControl -> OK (GEOADDR0=1, GEOADD(6:4)=000) 00006 RW ModuleResets -> OK (doesn't read a value, keep previous register) 00008 RO ModuleStatus1 -> 80fa = 1000 0000 1111 1010 0000A RO ModuleStatus2 -> 4444 = 0100 0100 0100 0100 0000C RO LinkStatus1 -> fffe = 1111 1111 1111 1110 0000E RO LinkStatus2 -> 0fff = 0000 1111 1111 1111 Tests: - illuminate 2 LEDs LED_1R_GREEN_DRV <= not BUF_TTC_READY; LED_2L_GREEN_DRV <= not BF_CONFIG_DONE; LED_2R_GREEN_DRV <= not TP_CONFIG_DONE; 08.04.2014 - Use lond delay ("safe" configuration) - errors during - Remove long DTACK delay in the Ian design (used for ACE interface) - still errors - Modify logic for DTACK delay generation: - in CMX_BSPT_VME: add sync to clk process(clk40) begin if rising_edge(clk40) then brdds <= board_select_n nor n_ds0_int; brdsel_n <= board_select_n; end if; end process; board_ds <= brdds; - remove DTACK delay in CMX_BSPT => register test OK (but ACE access doesn't eork) - add back DTACK delay with ariable dcnt - use variable dcnt=40 => errors in E0_FE??? and not in 28_2E, 60_7E (but can access ACE) - use variable dcnt=10 => errors in E0_FE??? and not in 28_2E, 60_7E (can't access ACE) - use variable dcnt=9 => NO errors in E0_FE - what is this magic number??? - use signal DTACK_CNT : std_logic_vector (4 DOWNTO 0) instead of variable - constant DTACK_DEL : std_logic_vector (4 DOWNTO 0):="11111"; -- (31) CLK40 periods = 0.775 us DTACK delay (for System ACE) -> errors in E0_FE??? - constant DTACK_DEL = "01010" (=10) - errors in E0_FE??? - constant DTACK_DEL = "01001" (=9) - OK -!!! understood! try to access the address space (E0-EF), allocated to ACE! (80-FF) with short DTACK delay ACE didn't yet assert data, with long - do, this is why errors with long delay 11.5 Work on TTC interface for the BSPT FPGA (Test on the VAT card) ------------------------------------------------------------------- TTC interface on CMX works after installing jusmper for Dout<2>='1' (JMP 14-15) TTCrx Chip_ID<13..0> = SubAddr<5..0>Data<7..0> TTCrx Address Module Type and Addresses ID_I2C 0ccc 000n 000100 CMM: module n=0–1 in crates ccc=0–5 4 n = GEOADD(0); ccc = GEOADD(6:4)- set to 000 in L1Calo test rig in Bld104 TTCrx I2C interface: ------------------- CMX_BSPT_TTC: reset (n_i2c_rst -> i2c_rst -> ff, i2c_clk_gen, i2c_ttc_engine, i2c_vme) from RW_06 ModuleResets(5) i2c_vme: TTCIF_RW_0030 : vme_rw_reg -- TTCrx Control Register: output -> vme_din rst_status <= vme_din(15) or i2c_rst; -> go to ff_e(rst) and reg_e(rst) i2c_abort <= vme_din(15); -> output from i2c_vme: go to i2c_ttc_engine i2c_rd_nwr <= not vme_din(13); ttc_pointer <= vme_din(12 downto 8); data_to_ttc <= vme_din(7 downto 0); TTCIF_RO_0032 : vme_ro_reg -- TTCrx Status Register: input -> ttc_status_i ttc_status_i <= '0' -- (15) & i2c_err_held -- (14) & i2c_busy -- (13) & "00000" -- (12-8) & ttc_data_held; -- (7-0) 11.6 Work on SFP control ------------------------ Avago AFBR-57M5APZ is a Small Formfactor Pluggable optical transceiver -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 0033 0201 0002 0002 f0fa 7744 ffc2 0666 00780010: 0000 0000 0000 0000 0000 0000 0000 0000 00004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F Bit 10: SFP1_TX_DISABLE - SFP1 Transmitter Disable (DAQ?) ===> now bit 12 (15.04.2014) TX_DISABLE allows the BSPT to turn off the laser in the transmitter. -bash-4.1$ vme edit 0x780004 00780004: 0002> 0402 -bash-4.1$ vme edit 0x780004 00780004: 0402> ^C 00006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F Bit 12: Reset SFP1 I2C controller -bash-4.1$ vme edit 0x780006 00780006: 0000> 1000 0000A RO ModuleStatus2 2 Module Satus 2 Register module_stat2 BSPT Opto Bit 00: SFP1_TX_FAULT - SFP1 Transmitter Fault => def 0 (module operational) Bit 01: SFP1_MOD_PRESENT - SFP1 Module Present->Low => def 0 (module installed) Bit 02: SFP1_RX_LOS - SFP1 Receiver Signal Loss => def 1 (no optical fibre connected) TX_FAULT signal allows the BSPT FPGA to know if there are problems with the laser transmitter. MOD_DEF0 signal tells the BSPT whether or not a component is plugged into the SFP socket. RX_LOS indicates that the optical input is absent or unusable. -bash-4.1$ vme dump 0x780000 0x7800ff 00780000: 0033 0201 0002 0002 f0fa 7744 ffc2 0666 7744 => 0111 0111 0100 0100 00010 RW SFP1Control1 2 SFP1 Control Register 1 sfp1_control1 BSPT Opto Bits 07–00: Data to SFP1 - This 8-bit field contains data to be written to the Avago AFBR-57M5APZ chip. Bits 15-08: Avago AFBR-57M5APZ Register Number - Specify the register number to be read or written Writing "0000" => Data to SFP1 = "00", Register Number = "00"; 00012 RW SFP1Control2 2 SFP1 Control Register 2 sfp1_control2 BSPT Opto Bit 08: SFP1 Page: 0 => SFP I2C address: 1010000X (0xA0); 1 => SFP I2C address: 1010001X (0xA2) Bit 09: SFP1 Write - When set to 1, defines the operation as a write to SFP1. When set to 0, the operation is a read. Bit 10: SFP1 I2C Controller Abort When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. The SFP1 I/O operation takes place whenever this register is written unless the I2C bus is busy Writing "0000" => Page 0; Reading; No I2C Controller Abort 00014 RO SFP1Status 2 SFP1 Status Register sfp1_status BSPT Opto Bits 07-00: Data from SFP1 - This 8-bit field contains data read from the SFP1 chip. Bit 10: SFP1 I2C Busy - When set to 1, indicates that an I2C transaction is underway Bit 11: SFP1 I2C Error - When set to 1, indicates that an I2C error has occurred Read from SFP works! Read byte 110 (X"6E") from page 1: - RW_10 -> 6e00; RW_12 -> 0100 => RO_14 : 0012 -> 0000_0000_0001_0010 Read byte 128 (X"80") from page 1: - RW_10 -> 8000; RW_12 -> 0100 => RO_14 : 0000 Write to byte 128 (X"80") on page 1 value "55": - RW_10 -> 8055; RW_12 -> 0300 Read from byte 128 (X"80") on page 1: - RW_10 -> 8000; RW_12 -> 0100 => RO_14 : 0055 Write to SFP works! Modified RW_04(ModuleControl) and RW_06(ModuleResets) - compile and test -> still works -- New version test CMX_BSPT_SFP2 : CMX_BSPT_OC id => '0', -- 0 = SFP tx => '0', -- NA csr_addr => sfp2_csr, -- SFP2 Control/Status Register data_addr => sfp2_data -- SFP2 Data register --> temporary addressing for tests 00020 RW SFP2_CSR Bits 07–00: MiniPOD Register Number - Specify the register number to be read or written. Bits 10-08: MiniPOD TWS Module Bus Address bits Adr[2:0] Address has the form 0101Adr[2:0](TX) or 0110Adr[2:0](RX) Bit 11: Write - When set to 1, defines the operation as a write to SFP1. When set to 0, the operation is a read. Bit 12: MP12 I2C controller Abort - When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit 14: MP12 I2C controller Busy - When set to 1, indicates that an I2C transaction is underway Bit 15: MP12 I2C controller Error - When set to 1, indicates that an I2C error has occurred Writing "0000" => Register 0, Page 0; Reading; No I2C Controller Abort 00022 RW SFP2_Data Bits 07-00: Data from MP12 - This 8-bit field contains last data read from MP12 Writing to these bits has no effect Bits 15–08: Data to MP12 - This 8-bit field contains data to be written to MP12 Read back the value written to the RW_22 SFP2_Dataregister Read byte 110 (X"6E") from page 1: - RW_20 -> 016e; RW_22 : 0012 -> 0000_0000_0001_0010 Write to byte 128 (X"80") on page 1 value "55": - RW_22 -> 5500; RW_20 -> 0980 (0000_1001_1000_0000); Read from byte 128 (X"80") on page 1: - RW_20 -> 0180; RW_22 -> 5555 11.7 Work on MiniPOD control ---------------------------- MiniPOD™ AFBR-811VxyZ, AFBR-821VxyZ, 10 Gbps/Channel, Twelve Channel, Parallel Fiber Optics Modules Two Wire Serial (TWS) interface with maskable interrupt for expanded functionality including: – Individual channel functions: disable, squelch disable, lane polarity inversion, TX eye margin enable – A/D read back: module temperature and supply voltages, per channel laser current and laser power, or received power – Status: per channel Tx fault, electrical (transmitter) or optical (receiver) LOS, and alarm flags – Programmable equalization integrated with DC blocking caps at transmitter data input – Programmable receiver output swing and de-emphasis level – Field Upgradable Firmware capability Control Signal Interface The control interface includes dedicated signals for address inputs, interrupt output and reset input and bidirectional clock and data lines for a two-wire serial access (TWS interface) to control and status and information registers. The TWS interface is compatible with industry standard two-wire serial protocol. The MiniPOD module is implemented as a slave device. Two Wire Serial Interface Clock Rate - 400kHz (max) - 2.5µs (TTCrx - 1 MHz -> 1µs ?) Two Wire Serial Interface Write Cycle Time (up to 2 sequential bytes) - tWC 100ms Reset Pulse Width tRSTL PW - 10µs (4 clock cycles) Adr[2:0] TWS Module Bus Address bits: Address has the form 0101hjkx where Adr2, Adr1 and Adr0 correspond to h, j and k respectively and x corresponds to the R/W command. ResetL - Reset signal to module, Asserted Low: When asserted the optical outputs are disabled, TWS interface commands are inhibited, and the module returns to default and non-volatile settings. An internal pull-up biases the input High if the input is open. 00020 RW MP12_CSR 2 MP12 Control/Status Reg mp12_csr BSPT Opto_mp Bits 07–00: MiniPOD Register Number - Specify the register number to be read or written. Bits 10-08: MiniPOD TWS Module Bus Address bits Adr[2:0] Address has the form 0101Adr[2:0](TX) or 0110Adr[2:0](RX) Bit 11: Write - When set to 1, defines the operation as a write to MiniPOD. When set to 0, the operation is a read. Bit 12: MP12 I2C controller Abort - When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit 14: MP12 I2C controller Busy - When set to 1, indicates that an I2C transaction is underway Bit 15: MP12 I2C controller Error - When set to 1, indicates that an I2C error has occurred 00022 RW MP12_Data 2 MP12 Data Register mp12_data BSPT Opto_mp Bits 07-00: Data from MP12 - This 8-bit field contains last data read from MP12; Writing to these bits has no effect Bits 15–08: Data to MP12 - This 8-bit field contains data to be written to MP12 Read back the value written to the RW_22 SFP2_Dataregister Reading byte 2: |IntL Status: Coded 1 for asserted IntL. - RW_20 -> 0000; RW_22 : 0006 -> 0000_0000_0000_0110 => |LOS Status: Coded 1 when a LOS flag is asserted for any channel Reading byte 129 (X"81") on TX Memory Map 00h Upper Page -bash-4.1$ vme edit 0x780020 00780020: 0000> 0081 -bash-4.1$ vme dump 0x780000 0x7800ff 00780020: 0081 0042 0000 0000 0000 0000 0000 0000 42 => 0100_0010 => OK!!! Reading byte 130 (X"82") on TX Memory Map 00h Upper Page C0 => 1100_0000 => OK!!! Reading byte 131 (X"83") on TX Memory Map 00h Upper Page 46 => 0100_0110 => shall be 0101_0101 (55)? 132 84 19 => 0001_1001 0000_1100 (0c)? 133 85 67 => 0110_0111 => OK!!! 11.8 CAN-Bus Monitoring Readout -------------------------------