RECOMMENDATIONS AND COMMENTS from the CMX prototype review of 7 march 2013 cf. http://www.pa.msu.edu/hep/atlas/l1calo/cmx/specification/3_prototype_review/ ---> The height of the Avago MiniPOD optical transmitter/receivers intrudes by 0.7mm into the space reserved by the neighbouring modules, according to VME specifications. It was felt that this should not present a real physical problem, but further mechanical tests at CERN will be carried out to be sure of this. A -> 5 miniPOD devices were installed on the CMX mechanical model. These miniPODs were positioned to match the location on the prototype CMX card. The CMX mechanical model was then tested again for interference in the l1calo test crate in bldg 104. cf. http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/manufacturing/1_mechanical_only/photos/minipod_height_checks/ The conclusion of these tests is that there is sufficient clearance. ---> Due to space issues, the CMX prototype layout does not allow front-panel access to the CompactFlash card, so changing this card would require the module to be removed and then re-inserted in the crate. Frequent extraction/insertion of the CMX poses a significant risk of backplane damage, and should be avoided. Alternatives include implementing a reliable alternative method for changing the flash card contents (through VME or JTAG), or moving the CompactFlash to the front panel. A cost-benefit analysis should be performed and applied. A -> The Compact Flash card is now accessible through the front-panel. To make room for the Compact Flash on the front-panel of CMX, the number of MTP feed-through connectors on the front-panel was reduced from 5 to 2. Only the Base Function will be used with all CMX cards in L1calo and 2 MTP connectors are a perfect match for the two miniPOD transmitters associated with the Base Function output to L1topo. Re-writing the content of the compact flash from VME is still being explored, but this feature is no longer critical. ---> All single-ended signal lines on the backplane were manufactured and tested to have 60 ohms impedance within 10%. A -> The characteristic impedance of the CMX traces connecting the backplane inputs to the BF FPGA has been specified to be 60 Ohm. ---> The DAQ and RoI outputs from the BF FPGA will be sent to the L1Calo RODs using G-link data formats. For timing compatibility the BF FPGA needs to be provided with a 40.000 MHz crystal clock. A -> It has been determined that a fixed clock frequency of 120.00 MHz is the optimal frequency to support G-link output to match the details specific to the PLL circuitry of the Virtex-6 GTX transmitters. A dedicated crystal provides 120.00 MHz to the GTX quads from the Base Function FPGA which are connected to the DAQ and ROI SFP modules associated with reaoud of the Base Function. ---> The L1Topo modules are expected to act as their own RODs, providing readout to DAQ and the ROIB using S-link protocol. To do the same from the TP FPGA, the TP and BF FPGAs would need to be provided with a 100.000 MHz crystal clock, the input links on the two TP SFP cages would need to be brought to spare GTX inputs on the BF FPGA, and two single-ended flow-control signals would need to be routed between the BF and TP FPGAs. Additionally two "BUSY" lemo cables would need to be routed through the front panel. Since this implies a significant addition to the CMX specification and potentially significant delays, it has since been confirmed that there is room on existing L1Calo RODs for the TP to provide eventual (limited) topology readout over G-link formats to those RODs. In this case, the TP FPGA must also be provided with a 40.000 MHz crystal clock for compatibility. A cost-benefit analysis should guide the choice of solutions. A -> For maximal future flexibility, and for lack of evidence that the need for ROD functionality on the TP FPGA could ever be ruled out in the long run, and to avoid additional delays, this recommendation was converted into a new requirement that the Topo FPGA needs to be able to support ROD functionality. All TTC signals were made accessible to the TP FPGA. Two signals from the TP FPGA can be made available through the front panel for use as S-link "BUSY" signals. A separate crystal provides a fixed clock to the GTX quads connected to the DAQ and ROI SFP modules associated with the readout of the Topo Function -- namely two GTX transmitters from the TP FPGA and two GTX receivers from the Base Function FPGA. This crystal site can be populated with either a 120.00 MHz clock to support G-link readout or 100.00 MHz to support S-link readout. ---> Currently the CMX front panel has five MTP/MPO outputs, each supporting one 12-fiber ribbon. If additional space must be freed, condensing the inputs and outputs to two 48-fiber connectors is straightforward. A -> The CMX front-panel now only has two MTP feedthrough connectors to make room for front-panel access to the Compact Flash card. ---> Interface with the VME-- bus: Existing boards in the system use 3.3V devices that are 5V tolerant. It is recommended to do the same on CMX. A -> This is indeed what has been used on CMX. ---> The required output from the TTCDec to the BF FPGA includes only the two deskew clocks, L1A and the BC reset signal. If the TP FPGA acts as its own ROD, then most or all of the TTCdec outputs should be routed to that device. If not, then the TP FPGA has the same requirements as the BF. A -> The BF FPGA receives Deskew1 and Deskew2 as fabric clocks and L1A and the BC reset signal are available as logic inputs. The TP FPGA receives Deskew1 and Deskew2 as fabric clocks and all of the TTCdec signals are available as logic inputs. ---> The CANbus monitoring should also include currents, implying an implementation using an analog multiplexer. A -> An analog multiplexer was added. Current monitoring is available to the CANbus microprocessor in addition to voltage monitoring of the DC-DC converters on CMX. ---> To save front-panel space, the number of LEDs at the front-panel is decreased to ten. The LEDs are driven by FPGA outputs, so their functionality can be changed over time. Still, suggestions are solicited for which LEDs are most useful, in testing and running conditions. A -> The flexibility gained by giving full control of the front-panel LEDs to FPGA firmware leaves this choice to the designers as they continue to learn what CMX states or activities will be the most useful to display. ---> The CMM specification included two front-panel outputs for the deskew1 and deskew2 clocks, but these were not included in the production version. These clock outputs were useful during early testing of the CMM, and could be similarly useful for the CMX. It is acceptable for these signals to be made available on a header; lemo connectors are not required. Again, this should be decided on a cost/benefit basis. A -> Two logic signals are available on connector J12 accessible on the front-panel. Each of these two signals can be set via jumpers to come from logic pins from the BF, TP or Board Support FPGA. A copy of e.g. the Deskew1 clock can be forwarded from the BF FPGA to the front-panel. These signals have indeed proven useful for testing CMX and would be used to supply S-Link BUSY signals if ever necessary. ---> The number of production CMX modules of each time still has to be finalized. Based on the CMM production run of 19 boards, it was suggested to produce 20 CMX boards due to the need for an additional test rig at MSU. Of the 20 production modules, 6 of them would have TP FPGAs installed. The approximate breakdown of where the different boards would be located: - USA15: 10 non-TP + 2 TP - CERN test rig: 1 TP - UK test rig: 1 non-TP - Mainz test rig: 1 non-TP - MSU test rig: 1 TP - Spares (CERN): 2 non-TP + 2 TP A -> Fewer than 6 production CMX cards will be assembled with a TP FPGA for the following reasons: - There is no plan for a CMX-Topo system to be used in l1calo. - The prototype CMX boards are fully equivalent to production modules. - In principle a TP FPGA could be added to a TP-less CMX at a later time. - The Virtex-6 FPGAs cost about $3500 each 20 production CMX boards will be assembled, as requested. Only 2 of the production boards will include a TP FPGA. A revised allocation table could then be |----------------+-----------------------+--------------------------------| | | Production CMX boards | Prototypes CMX boards | | | without | with | without | with | No TP FPGA | | | TP FPGA | TP FPGA | TP FPGA | TP FPGA | No BF FPGA | |----------------+-----------+-----------+---------+---------+------------| | USA15 | 12 | | | | | | CERN test rig | 1 | 1 | | | | | UK test rig | 1 | | | | | | Mainz test rig | 1 | | | | | | MSU test rig | | | 1 | 2 | 1 | | Spares (CERN) | 3 | 1 | | | | |----------------+-----------+-----------+---------+---------+------------| | Total | 18 | 2 | 1 | 2 | 1 | |----------------+-----------+-----------+---------+---------+------------|