//
//  SiLab Clock Setup Data                   Rev. 10-Aug-2018
//
//  The intent of this SiLab Clock Generator setup file for
//  the HTM Card is to use a 40.08 MHz Reference that is
//  received differentially on its input pins In1 and In2
//  and generate four 320.64 MHz outputs on its four output
//  pin pairs.
//
//  The steps in this process are:
//
//   - Divide the input Ref frequency by 2  to keep the 
//     phase/frequency detector working within its range
//
//   - In the analog PLL multiply up by a factor of 128 at
//     the MSn stage to a frequency of 2.565 GHz  which is
//     right in the middle of the VCO's range.
//
//   - Divide by a factor of 8 in the four MSx stages.
//
//   - Divide by a factor of 1 in the four output R stages.
//
//   - Notes:  
//
//       It my be better to divide by a factor of 4 at the
//       four MSx stages and then a factor of 2 at the four
//       output R stages,  i.e. helps guarantee symmetric
//       output waveform but we loose the guarantee of all
//       4 outputs running in phase.
//
//       I will keep the configuration of the PLL Parameters
//       as they are in the file from Trenz.  This makes sense
//       becuase the Phase Frequence Detector frequency is only
//       changing from 25 MHz to 20.04 MHz which is in the same
//       PFD frequency range listing,  i.e. > 15 MHz.   The VCO
//       frequency only changes from 2.500 GHz to 2.560 GHz so
//       all of the VCO paramters look OK for now.
//
//       I will keep the configuration of the four Output
//       Drivers as I found it in the file from Trenz - even
//       though this setup is a bit strange.   The Output Drivers
//       are controlled by the registers in the range 31 through
//       42.  Recall that on this Trenz FPGA Mezz card that all
//       supply pins to this Si5338 Clock Generator are 1.8 Volt.
//       Even so the four Output Drivers are setup for 3.3V LVDS.
//
//       I have not studied the sections on:
//          Frequency Increment/Decrement
//          Initial Phase Offset and Step Size
//          Spread Spectrum
//          Power Down Registers
//       and I assume / hope that all of this junk is turned Off.
//
//       The starting place for this file was the default
//       SiLabs Clock setup from Trenz.  I'm putting comments
//       on all changes to this default setup as shown below.
//


Reg_Data const code Reg_Store[NUM_REGS_MAX] = {

{ 0,0x00,0x00},

{ 1,0x00,0x00},

{ 2,0x00,0x00},

{ 3,0x00,0x00},

{ 4,0x00,0x00},

{ 5,0x00,0x00},

{ 6,0x08,0x1D},

{ 7,0x00,0x00},

{ 8,0x70,0x00},

{ 9,0x0F,0x00},

{ 10,0x00,0x00},

{ 11,0x00,0x00},

{ 12,0x00,0x00},

{ 13,0x00,0x00},

{ 14,0x00,0x00},

{ 15,0x00,0x00},

{ 16,0x00,0x00},

{ 17,0x00,0x00},

{ 18,0x00,0x00},

{ 19,0x00,0x00},

{ 20,0x00,0x00},

{ 21,0x00,0x00},

{ 22,0x00,0x00},

{ 23,0x00,0x00},

{ 24,0x00,0x00},

{ 25,0x00,0x00},

{ 26,0x00,0x00},

{ 27,0xF0,0x80},


//
// The intent of registers 28, 29, and 30 is to program
// the Input Section:
//
//   to use the In1-In2 differential input pins as the source
//   of the Reference Signal
//
//   to use P1 to divide the input reference frequency by 2
//   to keep it within range of the Phase Frequency Detector
//
//   and to select the MSn output signal as the Feedback to
//   the Phase Frequency Detector.
//
// Input pins 3, 4, 5, and 6,  the Feedback Selector, the
// P2 Divider, and the Xtal Oscillator are not used in the
// HTM Card application.
//

{ 28,0x03,0xFF},  // was 0x0B,  now use P1_Div_In = In1-In2 Diff,
                  // keep Xtal = 0b11,  keep P2_Div_In = NoClk,
                  // keep bit 7 Low vs Hi as specified in Ref Book

{ 29,0x41,0xFF},  // was 0x08,  now use P1_Div_In = In1-In2 Diff,
                  // use PFD_IN_Ref = P1_Div_Out,  Set P1_Div = 2

{ 30,0xB0,0xFF},  // was-is 0xB0,  keep PFD_IN_FB = NoClk,
                  // keep P2_Div_IN = NoClk,  keep P2_Div = 1

{ 31,0xC0,0xFF},

{ 32,0xC0,0xFF},

{ 33,0xC0,0xFF},

{ 34,0xC0,0xFF},

{ 35,0x00,0xFF},

{ 36,0x06,0x1F},

{ 37,0x06,0x1F},

{ 38,0x06,0x1F},

{ 39,0x06,0x1F},

{ 40,0x63,0xFF},

{ 41,0x0C,0x7F},

{ 42,0x23,0x3F},

{ 43,0x00,0x00},

{ 44,0x00,0x00},

{ 45,0x00,0xFF},

{ 46,0x00,0xFF},

{ 47,0x14,0x3F},

{ 48,0x3A,0xFF},

{ 49,0x00,0xFF},

{ 50,0xC4,0xFF},

{ 51,0x07,0xFF},

{ 52,0x10,0xFF},


//
// Registers 53 through 62 program the MS0 divider
// for integer division by 8
//
//    MS0_P1 = 0x0200
//    MS0_P2 = 0
//    MS0_P3 = 1
//

{ 53,0x00,0xFF},

{ 54,0x02,0xFF},  // was 0x08 for divide by 20
                  // now 0x02 for divide by  8

{ 55,0x00,0xFF},

{ 56,0x00,0xFF},

{ 57,0x00,0xFF},

{ 58,0x00,0xFF},

{ 59,0x01,0xFF},

{ 60,0x00,0xFF},

{ 61,0x00,0xFF},

{ 62,0x00,0x3F},

{ 63,0x10,0xFF},


//
// Registers 64 through 73 program the MS1 divider
// for integer division by 8
//
//    MS1_P1 = 0x0200
//    MS1_P2 = 0
//    MS1_P3 = 1
//

{ 64,0x00,0xFF},

{ 65,0x02,0xFF},  // was 0x08 for divide by 20
                  // now 0x02 for divide by  8

{ 66,0x00,0xFF},

{ 67,0x00,0xFF},

{ 68,0x00,0xFF},

{ 69,0x00,0xFF},

{ 70,0x01,0xFF},

{ 71,0x00,0xFF},

{ 72,0x00,0xFF},

{ 73,0x00,0x3F},

{ 74,0x10,0xFF},


//
// Registers 75 through 84 program the MS2 divider
// for integer division by 8
//
//    MS2_P1 = 0x0200
//    MS2_P2 = 0
//    MS2_P3 = 1
//

{ 75,0x00,0xFF},

{ 76,0x02,0xFF},  // was 0x08 for divide by 20
                  // now 0x02 for divide by  8

{ 77,0x00,0xFF},

{ 78,0x00,0xFF},

{ 79,0x00,0xFF},

{ 80,0x00,0xFF},

{ 81,0x01,0xFF},

{ 82,0x00,0xFF},

{ 83,0x00,0xFF},

{ 84,0x00,0x3F},

{ 85,0x10,0xFF},


//
// Registers 86 through 95 program the MS3 divider
// for integer division by 8
//
//    MS3_P1 = 0x0200
//    MS3_P2 = 0
//    MS3_P3 = 1
//

{ 86,0x00,0xFF},

{ 87,0x02,0xFF},  // was 0x08 for divide by 20
                  // now 0x02 for divide by  8

{ 88,0x00,0xFF},

{ 89,0x00,0xFF},

{ 90,0x00,0xFF},

{ 91,0x00,0xFF},

{ 92,0x01,0xFF},

{ 93,0x00,0xFF},

{ 94,0x00,0xFF},

{ 95,0x00,0x3F},

{ 96,0x10,0x00},


//
// Registers 97 through 106 program the MSn divider
// for integer division by 128
//
//    MSn_P1 = 0x3E00
//    MSn_P2 = 0
//    MSn_P3 = 1
//

{ 97,0x00,0xFF},

{ 98,0x3E,0xFF},  // was 0x30 for divide by 100
                  // now 0x3E for divide by 128

{ 99,0x00,0xFF},

{100,0x00,0xFF},

{101,0x00,0xFF},

{102,0x00,0xFF},

{103,0x01,0xFF},

{104,0x00,0xFF},

{105,0x00,0xFF},

{106,0x80,0xBF},

{107,0x00,0xFF},

{108,0x00,0xFF},

{109,0x00,0xFF},

{110,0x40,0xFF},

{111,0x00,0xFF},

{112,0x00,0xFF},

{113,0x00,0xFF},

{114,0x40,0xFF},

{115,0x00,0xFF},

{116,0x80,0xFF},

{117,0x00,0xFF},

{118,0x40,0xFF},

{119,0x00,0xFF},

{120,0x00,0xFF},

{121,0x00,0xFF},

{122,0x40,0xFF},

{123,0x00,0xFF},

{124,0x00,0xFF},

{125,0x00,0xFF},

{126,0x00,0xFF},

{127,0x00,0xFF},

{128,0x00,0xFF},

{129,0x00,0x0F},

{130,0x00,0x0F},

{131,0x00,0xFF},

{132,0x00,0xFF},

{133,0x00,0xFF},

{134,0x00,0xFF},

{135,0x00,0xFF},

{136,0x00,0xFF},

{137,0x00,0xFF},

{138,0x00,0xFF},

{139,0x00,0xFF},

{140,0x00,0xFF},

{141,0x00,0xFF},

{142,0x00,0xFF},

{143,0x00,0xFF},

{144,0x00,0xFF},

{145,0x00,0x00},

{146,0xFF,0x00},

{147,0x00,0x00},

{148,0x00,0x00},

{149,0x00,0x00},

{150,0x00,0x00},

{151,0x00,0x00},

{152,0x00,0xFF},

{153,0x00,0xFF},

{154,0x00,0xFF},

{155,0x00,0xFF},

{156,0x00,0xFF},

{157,0x00,0xFF},

{158,0x00,0x0F},

{159,0x00,0x0F},

{160,0x00,0xFF},

{161,0x00,0xFF},

{162,0x00,0xFF},

{163,0x00,0xFF},

{164,0x00,0xFF},

{165,0x00,0xFF},

{166,0x00,0xFF},

{167,0x00,0xFF},

{168,0x00,0xFF},

{169,0x00,0xFF},

{170,0x00,0xFF},

{171,0x00,0xFF},

{172,0x00,0xFF},

{173,0x00,0xFF},

{174,0x00,0xFF},

{175,0x00,0xFF},

{176,0x00,0xFF},

{177,0x00,0xFF},

{178,0x00,0xFF},

{179,0x00,0xFF},

{180,0x00,0xFF},

{181,0x00,0x0F},

{182,0x00,0xFF},

{183,0x00,0xFF},

{184,0x00,0xFF},

{185,0x00,0xFF},

{186,0x00,0xFF},

{187,0x00,0xFF},

{188,0x00,0xFF},

{189,0x00,0xFF},

{190,0x00,0xFF},

{191,0x00,0xFF},

{192,0x00,0xFF},

{193,0x00,0xFF},

{194,0x00,0xFF},

{195,0x00,0xFF},

{196,0x00,0xFF},

{197,0x00,0xFF},

{198,0x00,0xFF},

{199,0x00,0xFF},

{200,0x00,0xFF},

{201,0x00,0xFF},

{202,0x00,0xFF},

{203,0x00,0x0F},

{204,0x00,0xFF},

{205,0x00,0xFF},

{206,0x00,0xFF},

{207,0x00,0xFF},

{208,0x00,0xFF},

{209,0x00,0xFF},

{210,0x00,0xFF},

{211,0x00,0xFF},

{212,0x00,0xFF},

{213,0x00,0xFF},

{214,0x00,0xFF},

{215,0x00,0xFF},

{216,0x00,0xFF},

{217,0x00,0xFF},

{218,0x00,0x00},

{219,0x00,0x00},

{220,0x00,0x00},

{221,0x0D,0x00},

{222,0x00,0x00},

{223,0x00,0x00},

{224,0xF4,0x00},

{225,0xF0,0x00},

{226,0x00,0x00},

{227,0x00,0x00},

{228,0x00,0x00},

{229,0x00,0x00},

{231,0x00,0x00},

{232,0x00,0x00},

{233,0x00,0x00},

{234,0x00,0x00},

{235,0x00,0x00},

{236,0x00,0x00},

{237,0x00,0x00},

{238,0x14,0x00},

{239,0x00,0x00},

{240,0x00,0x00},

{242,0x00,0x02},

{243,0xF0,0x00},

{244,0x00,0x00},

{245,0x00,0x00},

{247,0x00,0x00},

{248,0x00,0x00},

{249,0xA8,0x00},

{250,0x00,0x00},

{251,0x84,0x00},

{252,0x00,0x00},

{253,0x00,0x00},

{254,0x00,0x00},

{255, 1, 0xFF}, // set page bit to 1

{ 0,0x00,0x00},

{ 1,0x00,0x00},

{ 2,0x00,0x00},

{ 3,0x00,0x00},

{ 4,0x00,0x00},

{ 5,0x00,0x00},

{ 6,0x00,0x00},

{ 7,0x00,0x00},

{ 8,0x00,0x00},

{ 9,0x00,0x00},

{ 10,0x00,0x00},

{ 11,0x00,0x00},

{ 12,0x00,0x00},

{ 13,0x00,0x00},

{ 14,0x00,0x00},

{ 15,0x00,0x00},

{ 16,0x00,0x00},

{ 17,0x01,0x00},

{ 18,0x00,0x00},

{ 19,0x00,0x00},

{ 20,0x90,0x00},

{ 21,0x31,0x00},

{ 22,0x00,0x00},

{ 23,0x00,0x00},

{ 24,0x01,0x00},

{ 25,0x00,0x00},

{ 26,0x00,0x00},

{ 27,0x00,0x00},

{ 28,0x00,0x00},

{ 29,0x00,0x00},

{ 30,0x00,0x00},

{ 31,0x00,0xFF},

{ 32,0x00,0xFF},

{ 33,0x01,0xFF},

{ 34,0x00,0xFF},

{ 35,0x00,0xFF},

{ 36,0x90,0xFF},

{ 37,0x31,0xFF},

{ 38,0x00,0xFF},

{ 39,0x00,0xFF},

{ 40,0x01,0xFF},

{ 41,0x00,0xFF},

{ 42,0x00,0xFF},

{ 43,0x00,0x0F},

{ 44,0x00,0x00},

{ 45,0x00,0x00},

{ 46,0x00,0x00},

{ 47,0x00,0xFF},

{ 48,0x00,0xFF},

{ 49,0x01,0xFF},

{ 50,0x00,0xFF},

{ 51,0x00,0xFF},

{ 52,0x90,0xFF},

{ 53,0x31,0xFF},

{ 54,0x00,0xFF},

{ 55,0x00,0xFF},

{ 56,0x01,0xFF},

{ 57,0x00,0xFF},

{ 58,0x00,0xFF},

{ 59,0x00,0x0F},

{ 60,0x00,0x00},

{ 61,0x00,0x00},

{ 62,0x00,0x00},

{ 63,0x00,0xFF},

{ 64,0x00,0xFF},

{ 65,0x01,0xFF},

{ 66,0x00,0xFF},

{ 67,0x00,0xFF},

{ 68,0x90,0xFF},

{ 69,0x31,0xFF},

{ 70,0x00,0xFF},

{ 71,0x00,0xFF},

{ 72,0x01,0xFF},

{ 73,0x00,0xFF},

{ 74,0x00,0xFF},

{ 75,0x00,0x0F},

{ 76,0x00,0x00},

{ 77,0x00,0x00},

{ 78,0x00,0x00},

{ 79,0x00,0xFF},

{ 80,0x00,0xFF},

{ 81,0x00,0xFF},

{ 82,0x00,0xFF},

{ 83,0x00,0xFF},

{ 84,0x90,0xFF},

{ 85,0x31,0xFF},

{ 86,0x00,0xFF},

{ 87,0x00,0xFF},

{ 88,0x01,0xFF},

{ 89,0x00,0xFF},

{ 90,0x00,0xFF},

{ 91,0x00,0x0F},

{ 92,0x00,0x00},

{ 93,0x00,0x00},

{ 94,0x00,0x00},

{255, 0, 0xFF} }; // set page bit to 0

//End of file