From: yperin@ttm.com [mailto:yperin@ttm.com]
Sent: Sunday, June 03, 2018 6:05 AM


Customer : DEBRON INDUSTRIAL ELECTRONICS
Part #   : 40-00643-00LF
Catalog  : 181875
PO #     : 70867
OnHold   : May 24 2018 01:14:24:000AM


Problem 1 :
Stack-up attached for your approval.


Problem 2 :
Geber data attached for your approval


Problem 3 :
Ipc netlist not found. We will extract from gerber data.


Problem 4 :
We have added 50mil dot-pattern thieving spaced at 75mil c/c
keeping 200mil away from features. Please find attached data
and approve.


Problem 5 :
Customer provided big cu pads for 106.3 and 118.1mil npth
drills in both outer layers, We will do secondary drilling
for these non-plated holes.


Problem 6 :
artwork received for plug via from top side. The vias
required plugging are exposed from both sides. Can we remove
sm clearance for these vias from both sides and plug them?


Problem 7 :
There is no info on score, array dimension. we will score
rails using 30 degree blade, web 0.015 +/-5mil. We have added
tooling holes and fiduciall at the location specified in otl
layer.


Regards,

Engineering Contact
Yogeswaran Perinpanayagam
416-208-2100
yperin@ttm.com




From: Perinpanayagam, Yogeswaran
[mailto:Yogeswaran.Perinpanayagam@ttm.com]
Sent: Friday, June 01, 2018 9:45 PM

To: Josh A.Schell <schell@Debron-Electronics.com>
Subject: RE: PRR 18-2575, P/N: 40-00643-00LF, PO: 70867

Hi Josh,

Updated Stack-up attached for your approval.

See below the plots details.

DRL: All the primary drilled holes (plated+ non-plated)

DBE: All the secondary drilled non-plated holes


The second drilled DBE holes are the non-plated holes
which are drilling through copper pads.

In order to avoid burring these non-plated holes are
drilled before etching.

Best regards,

Yoges Perinpan | Front End Engineering - Toronto | TTM Technologies, Inc.

416-208-2187 |yperin@ttm.com| www.ttm.com