Dan's HTM Notes ------------------- Rev Date: 2-Apr-2018 Vcco Connections on the FPGA Mezz: ---------------------------------- Vcco Pins ----------------- Banks: 10 J3-99 J3-100 3.3 Volt max I/O Banks 11 J3-159 J3-160 12 J2-159 J2-160 13 J2-99 J2-100 Banks: 33 J1-99 J1-100 1.8 Volt max I/O Banks 34 J1-159 J1-160 FPGA Mezzanine Card Power In/Out Connections: --------------------------------------------- I currently believe that +12V power goes into the FPGA Mezz card on pins: J2: 165, 166, 167, 168 I currently believe that +3.3V CPLD power goes into the FPGA Mezz card on pins: J2: 147, 148 I currently believe that the FPGA Mezz provides 3V3 output on its pins: J2: 169, 170, 171, 172 J2: 111, 123, 135 J2: 112, 124, 136 I currently believe that the FPGA Mezz provides 1V8 output on its pins: J1: 169, 170, 171, 172 The FPGA Mezz has separate pinout for the JTAG to its FPGA and for the JTAG to its CPLD: ---------------------------------------------- The FPGA JTAG connects to the HTM's J12 front panel Access Connector TMS J3-142 TCK J3-141 TDI J3-147 TDO J3-148 The CPLD JTAG connects to pins on the J15 connector. M_TMS J3-82 M_TCK J3-81 M_TDI J3-87 M_TDO J3-88 The pin JTAG_ENB J3-136 must be pulled LOW for JTAG operation. I think that this JTAG_ENB pin only effects the CPLD JTAG and does not effect the FPGA's JTAG operation. FPGA on the TE0782 FPGA Mezzanine: ------------------------------------ The Xilinx ZYNQ part is: XC7Z035 PACKAGE: FFG900ABX1625 This FPGA Mezz uses a SiLabs Si5338A clock generator and Marvell Alaska 88E1512 Gigabit Ethernet PHY Clock Input Pins to the Logic Fabric part of the XC7Z035: --------------------------------------------------------- The clock inputs to the fabric are the SRCC and MRCC pins in the normal Select I/O banks. Single Region Clock Capable Multi Region Clock Capable MRCC - These are the clock capable I/Os driving BUFRs, BUFIOs, BUFGs, and MMCMs/PLLs. In addition, these pins can drive the BUFMR for multi-region BUFIO and BUFR support. SRCC - These are the clock capable I/Os driving BUFRs, BUFIOs, BUFGs, and MMCMs/PLLs. Recall the Connections to J23 of a FEX Slot: -------------------------------------------- Connector Usage for a FEX Slot |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | Connect | Row | | Connector Pin Pairs | | | Number | Num | Name | A B | C D | E F | G H | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 01 | Fabric | Tx2[02]+ Tx2[02]- | Rx2[02]+ Rx2[02]- | Tx3[02]+ Tx3[02]- | Rx3[02]+ Rx3[02]- | | | | Channel | RO Stream 3 to HUB 2 | RO Stream 5 to HUB 2 | RO Stream 4 to HUB 2 | RO Stream 6 to HUB 2 | | | | 02 | | | | | | | 02 | | Tx0[02]+ Tx0[02]- | Rx0[02]+ Rx0[02]- | Tx1[02]+ Tx1[02]- | Rx1[02]+ Rx1[02]- | | | | | RO Stream 1 to HUB 2 | LHC Clock Hub 2 | RO Stream 2 to HUB 2 | Combined Data Hub 2 | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 03 | Fabric | Tx2[01]+ Tx2[01]- | Rx2[01]+ Rx2[01]- | Tx3[01]+ Tx3[01]- | Rx3[01]+ Rx3[01]- | | | | Channel | RO Stream 3 to HUB 1 | RO Stream 5 to HUB 1 | RO Stream 4 to HUB 1 | RO Stream 6 to HUB 1 | | | | 01 | | | | | | | 04 | | Tx0[01]+ Tx0[01]- | Rx0[01]+ Rx0[01]- | Tx1[01]+ Tx1[01]- | Rx1[01]+ Rx1[01]- | | | | | RO Stream 1 to HUB 1 | LHC Clock Hub 1 | RO Stream 2 to HUB 1 | Combined Data Hub 1 | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 05 | Base | BI_DA1+ BI_DA1- | BI_DB1+ BI_DB1- | BI_DC1+ BI_DC1- | BI_DD1+ BI_DD1- | | | | Chan 01 | GE Pair A IPbus Net | GE Pair B IPbus Net | GE Pair C IPbus Net | GE Pair D IPbus Net | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 06 | Base | BI_DA2+ BI_DA2- | BI_DB2+ BI_DB2- | BI_DC2+ BI_DC2- | BI_DD2+ BI_DD2- | | | | Chan 02 | GE Pair A IPMC Net | GE Pair B IPMC Net | GE Pair C IPMC Net | GE Pair D IPMC Net | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 07 | Base | BI_DA3+ BI_DA3- | BI_DB3+ BI_DB3- | BI_DC3+ BI_DC3- | BI_DD3+ BI_DD3- | | | | Chan 03 | Unused signal pair | Unused signal pair | Unused signal pair | Unused signal pair | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 08 | Base | BI_DA4+ BI_DA4- | BI_DB4+ BI_DB4- | BI_DC4+ BI_DC4- | BI_DD4+ BI_DD4- | | | | Chan 04 | Unused signal pair | Unused signal pair | Unused signal pair | Unused signal pair | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 09 | Base | BI_DA5+ BI_DA5- | BI_DB5+ BI_DB5- | BI_DC5+ BI_DC5- | BI_DD5+ BI_DD5- | | | | Chan 05 | Unused signal pair | Unused signal pair | Unused signal pair | Unused signal pair | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| | P23/J23 | 10 | Base | BI_DA6+ BI_DA6- | BI_DB6+ BI_DB6- | BI_DC6+ BI_DC6- | BI_DD6+ BI_DD6 | | | | Chan 06 | Unused signal pair | Unused signal pair | Unused signal pair | Unused signal pair | |---------+-----+----------+----------------------+----------------------+----------------------+----------------------| Recall the MiniPOD Power Consumption: ------------------------------------- HTM has one MiniPOD Transmitter and one MiniPOD Receiver. Current in mAmps. AFBR-811 FN1Z AFBR-821 FN1Z Supply Transmitter Receiver -------- ----------------- ----------------- 2.5 Volt 280 typ / 365 max 350 typ / 525 max 3.3 Volt 105 typ / 185 max 48 typ / 90 max Other Part No. 812 813 814 822 823 824 Total 2.5 V Current: 630 mA typ / 890 mA max Total 3.3 V Current: 153 mA typ / 275 mA max Clock Inputs to the SiLabs 5338A: --------------------------------- Si5338 signal IN1 pin #1 is routed to FPGA Mezz pin J3-40 Note that in the Si5338 IN1 is shown as the Dir side of the signal but the FPGA Mezz calls this SI5328_CLK1_N Si5338 signal IN2 pin #2 is routed to FPGA Mezz pin J3-38 Note that in the Si5338 IN2 is shown as the Cmp side of the signal but the FPGA Mezz calls this SI5328_CLK1_P Yes, the FPGA Mezz names these signals "SI5328" even though the device on their card is a SI5338A. Si5338 signal IN3 pin #3 is routed to output of the 25 MHz oscillator on the FPGA Mezz. The reference inputs the the SI5338A should be terminated and then AC coupled into this device. They show 100 nFd DC Blocking capacitors. HTM Card Thickness: ------------------- For the bid I will say 10 layers with the middle 2 at one oz. Having looked at some ATCA cards I see thicknesses of 82 - 84 mils about 2.11 mm for a do not much RTM and 105 mils about 2.67 mm for a front side FPGA card The ATCA specification requires the thickness to be in the range 1.6 mm to 2.4 mm with +-0.2 mm tollerance 1.4 mm to 2.6 mm absolute drop dead range. For the bid let's ask for something in the range 2.2 to 2.6 mm thick which for 10 layers gives about 0.24 mm per layer. This is about 1.75 x the per layer thickness of the Hub. For reference the Hub is in the range 2.97 to 3.07 mm thick and is 22 layers so about 0.137 mm per layer. Miscellaneous FPGA Mezz Signals: -------------------------------- - Currently all 8 of the front panel LEDs are controlled by Select I/O signals from the PL section of the zync FPGA. Do we want to move any of these to being controlled by CPLD I/O pins or MIO pins from the PS section of the zync FPGA ? For example, from the CPLD we could probably make LED control signals to indicate: All FPGA Mezz are up and running OK The FPGA is configured - I see no access to the FPGA's main control signals, i.e. PROG_B, INITIALIZE, DONE from the J1,J2,J3 pins on the mezzanine card. - Other control signals available on the FPGA Mezz card: JTAGENB Logic high enables CPLD JTAG pins. If low CPLD update is disabled. This pin affects only the CPLD (not the FPGA). On the base board this signal is pulled-up by 10k Ohm and has Switch S1B to Ground. On the FPGA Mezz card JTAGENB goes to pin 82 of the CPLD which may be called PT15C/JTAGENB. The CPLD is U14 a LCMX02-1200HC-4TG1001. This signal is J3-136. BOOTMODE On the base board this signal is pulled-up by 10k Ohm and has Switch S1B to Ground. On the FPGA Mezz card this signal goes to pin 99 on the CPLD U14. I think this is just a normal I/O pin on the CPLD called PT9A. This signal is J3-135. RESIN On the base board this runs to the header (J8) for the CPLD's JTAG adaptor along with the CPLD signals 00, 01, 02 (and the 4 CPLD JTAG signals ( M_T bla )). On the FPGA Mezz card this signal goes to pin 97 on the CPLD U14. I think this is just a normal I/O pin on the CPLD called PT10A. This signal is J3-130. CONFIGX On the base board this runs to the header (J7) for the FPGA's JTAG adaptor along with CPLD signals 03, 04, 05, (and the 4 FPGA JTAG signals T bla). On the FPGA Mezz card this signal goes to pin 98 on the CPLD U14. I think this is just a normal I/O pin on the CPLD called PT9B. This signal is J3-129. VBAT_IN On the base board this is pulled up to 1.8V_M by 1.82K in series with 330 Ohm. It is pulled down to ground by 10K Ohm. On the FPGA Mezz card VBAT_IN just runs to an anode in dual diode D3 (the other anode is tied to 3.3V). The common cathode runs to the VBAT pin on the Intersil Readtime Clock chip and to the input pin on some little regulator U21 which outputs the bus VBAT which I think just goes to the VBAT pin on the FPGA. I assume that this is really ment to go to a battery - not to the resistors on the base board. This signal is J3-124. CPLD GPIO 0, 1, 2 go to the J8 USB-JTAG mezz connector Conn J2 on the BaseBoard CPLD JTAG ----------- GPIO_0 is CPLD pin #12 Pin Name PL5A/CLKT3-1 Mezz Pin 10 GPIO_1 is CPLD pin #11 Pin Name VccIO3 Mezz Pin 12 GPIO_2 is CPLD pin #10 Pin Name PL4B Mezz Pin 14 CPLD GPIO 3, 4, 5 go to the J7 USB-JTAG mezz connector Conn J2 on the BaseBoard FPGA JTAG ----------- GPIO_3 is CPLD pin #9 Pin Name PL4A Mezz Pin 16 GPIO_4 is CPLD pin #8 Pin Name PL3D Mezz Pin 18 GPIO_5 is CPLD pin #7 Pin Name PL3C Mezz Pin 20 HTM Routing Notes: ------------------ Differential Traces: Normal 0.14 mm wide traces on 0.40 mm center to center. This gives a 0.26 mm air gap between traces. Stager by 0.20 mm to start a 45 deg run. 0.30 mm x sqrt 2 = 0.4243 mm center to center in the 45 deg run. This gives a 0.284 mm air gap between traces in the 45 deg run. So on the 45 deg run there is 109% of the normal air gap. More copper 0.18 mm wide traces on 0.50 mm center to center. The 0.18 mm wide traces is about 29% more copper. This gives a 0.32 mm air gap between traces. Stager by 0.30 mm to start a 45 deg run. 0.40 mm x sqrt 2 = 0.5657 mm center to center in the 45 deg run. This gives a 0.386 mm air gap between traces in the 45 deg run. So on the 45 deg run there is 121% of the normal air gap. The differential pair C to C spacing is 2.0 mm More comfortable spacing is 2.0 mm between adjacent traces of the adjacent pairs. On other cards routed as tight as 0.6 mm from the outer edge of the Diff Pair to the edge of the via in the Differential Via Pair, e.g. in the Hub MGT Fanout. Have routed with an air gap of 0.4 mm front outer edge of the Diff Piar to the Edge of the via in the DVP in the FPGA escape. Routing Trace Widths and Via Types: The small signal routing via can be via_0mm60 or where there is space one can use via_0mm65. The smallest small signal trace is 0.14 mm. For the 0603 components: 0.60 mm trace with via_0mm65 vias. Center of via is 0.5 to 0.6 mm from the edge of the component pad. For the 0805 components: 0.60 mm trace with via_0mm65 vias. Center of via is 0.5 to 0.6 mm from the edge of the component pad. For the 1206 components: 1.20 mm trace with via_1mm1 via. Center of via is 0.9 mm from the edge of the component pad. For the V case Tant: 2x 1.2 mm trace and via_1mm1 with about 1 mm from center of via to edge or pad. For tssop power and ground: use 0.30 mm trace width and via_0mm65 via. For Samtek 160 pin: use 0.18 or 0.20 mm trace width on signal pins use 0.28 mm trace width on Ground power pins use 0.45 mm trace width on the blades use via_0mm65 via for straight out Gnd Vias go out 0.6 full mm ticks for between pad Gnd Vias go out 0.9 full mm ticks and down by 0.2 full mm ticks for High-Speed pairs go out 0.2 full mm ticks and then angle in to the 0.4 mm C_to_C spacing over another 0.2 mm outward all with 0.14 mm trace Checks of the Samtec 160 (172) Pin Connector on the HTM Card: --------------------------------------------------------------- Brian can look at the "design files" and the Gerber files for the Base Board for the FPGA card. To help Spencer verify that we have a good Geometry for this connector in our Mentor system, Brian dug out the following measurements which allowed Spencer to remove some ambiguities in the Samtec data sheet for this connector. From email notes from Brian: All dimensions in mm, Pulled from the Altium design files for TEBT0782 3rd pad on right from center Center of connector: 68.699, 88.941 56.751, 88.941 5th pin on right from center: 79.938, 88.941 6th pin on right from center: 84.828, 88.941 Center of NW pin central block: 49.493, 91.805 Center of NE pin, left (high speed) block: 43.498, 91.805 Difference, center to center: 5.995 Center of 4th pin on right: 73.588, 88.941 Recall that we also have the two png files from Brian that verify the numbering of the 12 center blade pins on this connector. These png files are on the web in the HTM site.