Design Rule Checks on the Hub Module -------------------------------------- Initial Rev. 17-Apr-2018 Current Rev. 24-Apr-2018 This file contains notes about runs of the Design Rule Checker on the Hub Module. In general the Design Rule Check is run from Layout on the Traces part of the Hub Design. Check --> Traces --> Check_Traces A typical setup is: Entire Board Remove Trace Violations -- NOT Check Net Agains Itself -- NOT Check Trace Widths Less Than Net Rule -- NOT Check All Thermal Ties on Pins and Vias -- NOT Check Same Net Pad to Pad Clearances -- NOT Remove Deplicate Routing -- NOT Check Pas connectivity with fill hatch - NOT Report Off Grid Vias as -- No Checking Report Uncovered Plated Drill Holes as -- Warning Runs on Traces File 103 with Fills In on 17-Apr-2018: -------------------------------------------------------- These DRC runs were made with the Design Rules: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.20 0.35 Trace 0.12 0.20 0.185 Fill 0.35 0.35 0.50 0.50 Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.38 1.00 Trace 0.12 0.26 0.21 Fill 0.35 0.35 0.50 0.50 ---------------------------- Check Traces Options ---------------------------- Note: Same Net Checking: OFF (from: Idea/Util/Lay Template 13) Note: Off Grid Via Checking: OFF (from: Idea/Util/Lay Template AA) Note: Same Net Pad to Pad Clearance Checking: OFF (from: Idea/Util/Lay Template B7) Note: Trace/Via/Routing Keepout Clearances: ON (from: Idea/Util/Lay Template B8) ---------------------------- Check Traces Messages --------------------------- Warning: Pin (81.354,20.507) has poor coverage by Fill_Area (55.05,10.05) (187.45,245.95). (from: Idea/Util/Fill 1C) Warning: Pin (101.4,126.86) has poor coverage by Fill_Area (74.45,116.05) (117.95,130.15). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,126.86) has poor coverage by Fill_Area (74.45,116.05) (117.95,130.15). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,128.13) has poor coverage by Fill_Area (74.45,116.05) (117.95,130.15). (from: Idea/Util/Fill 1C) Warning: Pin (103.87,133.14) has poor coverage by Fill_Area (74.45,131.05) (117.95,143.95). (from: Idea/Util/Fill 1C) Warning: Pin (102.6,133.14) has poor coverage by Fill_Area (74.45,131.05) (117.95,143.95). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,133.14) has poor coverage by Fill_Area (74.45,131.05) (117.95,143.95). (from: Idea/Util/Fill 1C) Warning: Pin (101.4,92.86) has poor coverage by Fill_Area (74.45,82.05) (117.95,96.15). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,92.86) has poor coverage by Fill_Area (74.45,82.05) (117.95,96.15). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,94.13) has poor coverage by Fill_Area (74.45,82.05) (117.95,96.15). (from: Idea/Util/Fill 1C) Warning: Pin (103.87,99.14) has poor coverage by Fill_Area (74.45,97.05) (117.95,109.95). (from: Idea/Util/Fill 1C) Warning: Pin (102.6,99.14) has poor coverage by Fill_Area (74.45,97.05) (117.95,109.95). (from: Idea/Util/Fill 1C) Warning: Pin (100.13,99.14) has poor coverage by Fill_Area (74.45,97.05) (117.95,109.95). (from: Idea/Util/Fill 1C) ---------------------------- Check Traces Summary ---------------------------- Note: Number of classic fills checked = 0 (from: Idea/LAYOUT/Thermal Tie 00) Note: Number of areafills checked = 10 (from: Idea/LAYOUT/Thermal Tie 01) Note: Number of actual shapes found = 10 (from: Idea/LAYOUT/Thermal Tie 07) Note: Number of island shapes found = 8 (from: Idea/LAYOUT/Thermal Tie 08) Note: Number of pins with ties checked = 15 (from: Idea/LAYOUT/Thermal Tie 02) Note: Number of vias with ties checked = 8 (from: Idea/LAYOUT/Thermal Tie 03) Note: Number of flood ties checked = 23 (from: Idea/LAYOUT/Thermal Tie 04) Note: Number of isolate ties checked = 0 (from: Idea/LAYOUT/Thermal Tie 05) Note: Number of thermal ties checked = 0 (from: Idea/LAYOUT/Thermal Tie 06) Note: Checked: 11137 Segments, 590 Vias and 10 Fill_Areas (from: Idea/LAYOUT/ROUTE E6) Note: Other Errors/Warnings = 13 (from: Idea/LAYOUT/ROUTE AD) Note: Odd Angle Segments = 6511 (from: Idea/LAYOUT/ROUTE F1) Note: Unroutes = 0 (from: Idea/LAYOUT/ROUTE E2) Note: Unplaced components = 0 (from: Idea/LAYOUT/PLACEMENT2 67) Note: Off-board components = 0 (from: Idea/LAYOUT/PLACEMENT2 68) The "poor coverage" in the fills are understood and expected, i.e. yes the coverage is not complete when the adjacent pin is from a different net. Start a sequence of multiple runs to explore where the clearance violations start. This traces file is 103 with all Fills In. Move Trace to Trace for both Default and HS to 0.26 mm. Passes with zero errors but that is the limit. Blow up if either Default or HS is above 0.26 mm. Study Default Via to Via. Could be 0.45 mm ( 0mm65 vias on 1.1 mm centers) but there are two places where I use 0mm65 vias on 1.0 mm centers, i.e. to escape the 40 MHz clocks from the Samtec 160 connectors and that forces a 0.35 mm clearance for Default Via to Via. 0.35 mm is OK for Default Via to Via. HS Via to Via - stay at 1 mm as there are none. Study Default Via to Pin. When I crank up this clearance it mostly (or perhaps only) finds violations for the Gnd vias associated with the Samtec 160 pin connectors. Zero errors at 0.40 mm. At 0.41 mm pick up about 30 errors in the Samtec 160s. 0.40 mm is OK for Default Via to Pin. Study Default Via to Trace. Limit is in the escape from the Samtec 160s. Zero at 0.32 mm. 23 error at 0.33 mm. I could drop the LED Control traces as they escape the Samtec 160s through the via field from 0.20 mm width to 0.18 mm width and pick up 0.02 mm clearance. 0.32 mm is OK for Default Via to Trace. Study Default Pin to Trace. Limit is escape from J12. At 0.16 mm zero errors. At 0.17 the only errors are in J12 with 8 violation errors. At 0.22 mm still only the 8 J12 errors. At 0.23 mm it blows up to 198 errors. 0.16 mm is OK for Zero errors of Default Pin to Trace. So for Default we can run with Zero Errors: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.40 0.35 Trace 0.16 0.32 0.26 Fill 0.35 0.35 0.50 0.50 Note that all of the Fill clearance limits were just set by how the Fills were generated. Study HS Via to Pin. Limit is North of 1 mm so that is good. Study HS Trace to Pin. Limit is in the MiniPODs. With 0.22 mm you see zero errors. With 0.23 mm you have 2 or 3 violations in the MiniPODs. At 0.25 you have all 16 MiniPOD traces in violation under the MiniPOD. Nothing except HS under the MPs shows up until 0.30 mm and then the escape from the Samtec 160s shows every pin. So 0.22 is OK Study HS Trace to Via. Limit is North of 1 mm because there are none. Use 1 mm HS trace to via limit. So for HS we can run with Zero Errors: Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 1.00 1.00 Trace 0.22 1.00 0.26 Fill 0.35 0.35 0.50 0.50 Note that all of the Fill clearance limits were just set by how the Fills were generated. Note that for the HS class nets that the File to Pin and Via of 0.35 mm is actually wrong - i.e. too tight but the HTM Card design has No Fills under the HS traces near HS THD pins or vias. 24-April-2018 Since the clean up work over the weekend and yesterday on the Clock diff pair polarity flips, you can now run with Default Via to Via clearance of 0.45 mm and still have zero clearance errors. That is you can run with Default net type clearance rules: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.40 0.45 Trace 0.16 0.32 0.26 Fill 0.35 0.35 0.50 0.50