HTM Card FPGA Mezzine Connections ------------------------------------ Original Rev. 7-Apr-2018 Current Rev. 14-Apr-2018 This files list all of the connections that the HTM Card makes to the FPGA Mezzanine connectors J1, J2, and J3. Near the end of this file there are two lists of connections that are internal to the FPGA Mezz itself: - the Si Labs Clock Generator chip to FPGA connections - the Phy chip to FPGA connections LED Control Signals: 8 Upper LEDs, 8 RJ45 LEDs ------------------------------------------------ These 16 signals are all 3.3V CMOS Outputs from the FPGA. A drive of 4 mA Drive should be fine. FPGA output Low turns ON the associated LED. FPGA Mezz HTM Card Signal Name Pin No. FPGA Pin Number and Name ---------------------- ------- -------------------------- LED_1_TOP_CONTROL J2-150 AJ26 IO_L24P_T3_12 LED_2_CONTROL J2-144 AJ28 IO_L21P_T3_DQS_12 LED_3_CONTROL J2-138 AG26 IO_L17P_T2_12 LED_4_CONTROL J2-132 AD25 IO_L10P_T1_12 LED_5_CONTROL J2-126 AB29 IO_L2P_T0_12 LED_6_CONTROL J2-120 AC26 IO_L7P_T1_12 LED_7_CONTROL J2-114 Y30 IO_L1P_T0_12 LED_8_BOT_CONTROL J2-108 Y28 IO_L4P_T0_12 RJ45_J14_LED_1_CONTROL J2-90 W28 IO_L9N_T1_DQS_13 RJ45_J14_LED_2_CONTROL J2-84 T22 IO_L20P_T3_13 RJ45_J14_LED_4_CONTROL J2-78 U24 IO_L23P_T3_13 RJ45_J14_LED_3_CONTROL J2-72 R22 IO_L21P_T3_DQS_13 RJ45_J13_LED_1_CONTROL J2-66 T24 IO_L17P_T2_13 RJ45_J13_LED_2_CONTROL J2-60 P23 IO_L18P_T2_13 RJ45_J13_LED_4_CONTROL J2-54 N28 IO_L3P_T0_DQS_13 RJ45_J13_LED_3_CONTROL J2-48 N26 IO_L15P_T2_DQS_13 Hardware Address Backplane Signals: ------------------------------------ These 8 signals are 3.3V CMOS Inputs to the FPGA. FPGA HTM Card Mezz Signal Name Pin No. FPGA Pin Number and Name --------------- ------- -------------------------- HW_ADRS_0 J3-83 AB15 IO_L22P_T3_10 HW_ADRS_1 J3-89 AC17 IO_L23P_T3_10 HW_ADRS_2 J3-53 AG12 IO_L10P_T1_10 HW_ADRS_3 J3-47 AD14 IO_L9P_T1_DQS_10 HW_ADRS_4 J3-77 AE16 IO_L16P_T2_10 HW_ADRS_5 J3-71 AH14 IO_L8P_T1_10 HW_ADRS_6 J3-59 AB12 IO_L21P_T3_DQS_10 HW_ADRS_7 J3-65 AA15 IO_L20P_T3_10 FEX Readout Data MGT Ouput Differential Signals: -------------------------------------------------- Some of the FEX Readout Data connections include a Polarity Flip to facilitate routing. ST --> Straight Through PF --> Polarity Flip FPGA HTM Card Mezz Signal Name Pin No. FPGA Pin Number and Name ----------------------- ------- -------------------------- MGT_TX_HUB_2_LN_3_DIR J3-31 AK10 MGTXTXP0_109 ST MGT_TX_HUB_2_LN_3_CMP J3-29 AK9 MGTXTXN0_109 MGT_TX_HUB_2_LN_5_DIR J3-27 AK6 MGTXTXP1_109 ST MGT_TX_HUB_2_LN_5_CMP J3-25 AK5 MGTXTXN1_109 MGT_TX_HUB_2_LN_4_DIR J3-23 AJ4 MGTXTXP2_109 ST MGT_TX_HUB_2_LN_4_CMP J3-21 AJ3 MGTXTXN2_109 MGT_TX_HUB_2_LN_6_DIR J3-19 AK2 MGTXTXP3_109 ST MGT_TX_HUB_2_LN_6_CMP J3-17 AK1 MGTXTXN3_109 MGT_TX_HUB_2_LN_1_DIR J3-15 AH2 MGTXTXP0_110 ST MGT_TX_HUB_2_LN_1_CMP J3-13 AH1 MGTXTXN0_110 MGT_TX_HUB_2_LN_2_DIR J3-11 AF2 MGTXTXP1_110 ST MGT_TX_HUB_2_LN_2_CMP J3-9 AF1 MGTXTXN1_110 MGT_TX_HUB_1_LN_3_DIR J3-7 AE4 MGTXTXP2_110 ST MGT_TX_HUB_1_LN_3_CMP J3-5 AE3 MGTXTXN2_110 MGT_TX_HUB_1_LN_5_DIR J3-3 AD2 MGTXTXP3_110 ST MGT_TX_HUB_1_LN_5_CMP J3-1 AD1 MGTXTXN3_110 MGT_TX_HUB_1_LN_4_DIR J1-4 AB1 MGTXTXN0_111 PF MGT_TX_HUB_1_LN_4_CMP J1-2 AB2 MGTXTXP0_111 MGT_TX_HUB_1_LN_6_DIR J1-8 Y1 MGTXTXN1_111 PF MGT_TX_HUB_1_LN_6_CMP J1-6 Y2 MGTXTXP1_111 MGT_TX_HUB_1_LN_1_DIR J1-12 W3 MGTXTXN2_111 PF MGT_TX_HUB_1_LN_1_CMP J1-10 W4 MGTXTXP2_111 MGT_TX_HUB_1_LN_2_DIR J1-16 V1 MGTXTXN3_111 PF MGT_TX_HUB_1_LN_2_CMP J1-14 V2 MGTXTXP3_111 Combined Data MGT Input Differential Signals: ----------------------------------------------- FPGA Mezz HTM Card Signal Name Pin No. FPGA Pin Number and Name ------------------------- ------- -------------------------- COMBINED_DATA_FROM_HUB1_DIR J1-7 AB5 MGTXRXN1_111 PF COMBINED_DATA_FROM_HUB1_CMP J1-5 AB6 MGTXRXP1_111 COMBINED_DATA_FROM_HUB2_DIR J3-6 AF5 MGTXRXN2_110 PF COMBINED_DATA_FROM_HUB2_CMP J3-8 AF6 MGTXRXP2_110 Clock Signals: FPGA Logic and Spare, Si_Labs Ref, Monitor ------------------------------------------------------------ The two differential clock inputs are AC Coupled LVDS and need to use their 100 Ohm Terminator and DC Ref Voltage features. The last two signals are 3.3V CMOS FPGA Inputs FPGA Mezz HTM Card Signal Name Pin No. FPGA Pin Number and Name -------------------------- ------- -------------------------- FPGA_40.08_MHZ_LOGIC_CLK_DIR J3-156 AE22 IO_L12P_T1_MRCC_11 FPGA_40.08_MHZ_LOGIC_CLK_CMP J3-158 AF22 IO_L12N_T1_MRCC_11 SPARE_OSC_TO_FPGA_DIR J2-156 AC28 IO_L12P_T1_MRCC_12 SPARE_OSC_TO_FPGA_CMP J2-158 AD28 IO_L12N_T1_MRCC_12 HUB_2_REF_CLK_MON_TO_FPGA J2-53 P30 IO_L1P_T0_13 PLL_40_MHZ_LOCKED_MON J3-101 AK17 IO_L16P_T2_11 REF_40.08_MHZ_TO_SI_LAB_DIR J3-40 Does not connect to the FPGA. REF_40.08_MHZ_TO_SI_LAB_CMP J3-38 Connects to Si Labs Si5338A pin numbers 1 and 2, pin names IN1 and IN2 FPGA Mezz Sch pages 4 and 21. Si5338 Data Sheet pages 1, 18, and 19. MGT Reference Clocks from the Si5338A to the FPGA MGT Banks: These connections are internal to the FPGA Mezzanine itself. FPGA Mezzanine Net Names U2 Si5338A In / Out DC Blk Cap Clk Outputs ------------------------ ------------- Net Connects to Pin Signal Name Net Name FPGA MGT Bank Pin No. Name to Cap from Cap Signal Name No. --- ------ ------ ---------- --------------- --- 22 CLK0A CLK2_P MGT_CLK6_P MGTREFCLK0P_112 N8 21 CLK0B CLK2_N MGT_CLK6_N MGTREFCLK0N_112 N7 18 CLK1A CLK3_P MGT_CLK5_P MGTREFCLK1P_111 W8 17 CLK1B CLK3_N MGT_CLK5_N MGTREFCLK1N_111 W7 14 CLK2A CLK0_P MGT_CLK0_P MGTREFCLK0P_110 AA8 13 CLK2B CLK0_N MGT_CLK0_N MGTREFCLK0N_110 AA7 10 CLK3A CLK1_P MGT_CLK3_P MGTREFCLK1P_109 AF10 9 CLK3B CLK1_N MGT_CLK3_N MGTREFCLK1N_109 AF9 | | | |<----- Pg 21 ----->|<----------------- Pg 9 ---------------->| FPGA MEzz Schematic Page Numbers Notice that for normal operation where all 4 MGT Banks are operating from Reference Clocks provided by the Si5338A clock generator chip: MGT Bank 109 uses its Ref Clk 1 MGT Bank 110 uses its Ref Clk 0 MGT Bank 111 uses its Ref Clk 1 MGT Bank 112 uses its Ref Clk 0 I2C Connection from Si Labs 5338A to FPGA Select I/O: These connections are internal to the FPGA Mezzanine itself. Si Labs 5338A Zync FPGA Select I/O ------------------ FPGA Mezz --------------------------- Pin No. Pin Name Net Name Pin No. Pin Name ------- -------- --------- ------- ----------------- 12 SCL I2C_SCL L14 IO_L1N_T0_AD0N_35 19 SDA I2C_SDA L15 IO_L1P_T0_AD0P_35 See the FPGA Mezz Schematics pages 19 and 21. See the Si5338A Data Sheet pages 1, 17, and 31 MiniPOD Signals: Rec Data, Trans Data, Control/Monitor --------------------------------------------------------- All MiniPOD data signals are from/to MGT Transceivers. 12 Fibers are connected on the MiniPOD Receiver. Only 4 Fibers are connected on the MiniPOD Transmitter. The 4 Control/Monitor signals to each MiniPOD are 3.3V CMOS level and the output signals are open drain. FPGA HTM Card Mezz Signal Name Pin No. FPGA Pin Number and Name ------------------- ------- -------------------------- MINI_POD_REC_D0_DIR J3-32 AH10 MGTXRXP0_109 ST MINI_POD_REC_D0_CMP J3-30 AH9 MGTXRXN0_109 MINI_POD_REC_D1_DIR J1-31 P5 MGTXRXN3_112 PF MINI_POD_REC_D1_CMP J1-29 P6 MGTXRXP3_112 MINI_POD_REC_D2_DIR J3-26 AJ7 MGTXRXN1_109 PF MINI_POD_REC_D2_CMP J3-28 AJ8 MGTXRXP1_109 MINI_POD_REC_D3_DIR J1-25 T6 MGTXRXP2_112 ST MINI_POD_REC_D3_CMP J1-27 T5 MGTXRXN2_112 MINI_POD_REC_D4_DIR J3-24 AG8 MGTXRXP2_109 ST MINI_POD_REC_D4_CMP J3-22 AG7 MGTXRXN2_109 MINI_POD_REC_D5_DIR J1-21 U4 MGTXRXP1_112 ST MINI_POD_REC_D5_CMP J1-23 U3 MGTXRXN1_112 MINI_POD_REC_D6_DIR J3-20 AE8 MGTXRXP3_109 ST MINI_POD_REC_D6_CMP J3-18 AE7 MGTXRXN3_109 MINI_POD_REC_D7_DIR J1-19 V5 MGTXRXN0_112 PF MINI_POD_REC_D7_CMP J1-17 V6 MGTXRXP0_112 MINI_POD_REC_D8_DIR J3-16 AH6 MGTXRXP0_110 ST MINI_POD_REC_D8_CMP J3-14 AH5 MGTXRXN0_110 MINI_POD_REC_D9_DIR J1-15 AA3 MGTXRXN3_111 PF MINI_POD_REC_D9_CMP J1-13 AA4 MGTXRXP3_111 MINI_POD_REC_D10_DIR J3-12 AG4 MGTXRXP1_110 ST MINI_POD_REC_D10_CMP J3-10 AG3 MGTXRXN1_110 MINI_POD_REC_D11_DIR J1-9 Y6 MGTXRXP2_111 ST MINI_POD_REC_D11_CMP J1-11 Y5 MGTXRXN2_111 MINI_POD_TRANS_D0_DIR J1-24 R3 MGTXTXN1_112 PF MINI_POD_TRANS_D0_CMP J1-22 R4 MGTXTXP1_112 MINI_POD_TRANS_D1_DIR J1-26 P2 MGTXTXP2_112 ST MINI_POD_TRANS_D1_CMP J1-28 P1 MGTXTXN2_112 MINI_POD_TRANS_D2_DIR J1-18 T2 MGTXTXP0_112 ST MINI_POD_TRANS_D2_CMP J1-20 T1 MGTXTXN0_112 MINI_POD_TRANS_D3_DIR J1-30 N4 MGTXTXP3_112 ST MINI_POD_TRANS_D3_CMP J1-32 N3 MGTXTXN3_112 MP_REC_INTR J3-80 AD15 IO_L18N_T2_10 MP_REC_RESET J3-72 AH18 IO_L2P_T0_10 MP_REC_SCL J3-74 AJ18 IO_L2N_T0_10 MP_REC_SDA J3-78 AD16 IO_L18P_T2_10 MP_TRANS_INTR J3-66 AF18 IO_L15P_T2_DQS_10 MP_TRANS_RESET J3-48 AJ14 IO_L3P_T0_DQS_10 MP_TRANS_SCL J3-54 AK13 IO_L1P_T0_10 MP_TRANS_SDA J3-60 AJ16 IO_L4P_T0_10 Front Panel Signals: JTAG, Access, Ethernet ---------------------------------------------- FPGA Mezz HTM Card Signal Name Pin No. FPGA Pin Number and Name ----------------------- ------- -------------------------- TCK_TO_FPGA_MEZZ J3-141 JTAG connection TDI_TO_FPGA_MEZZ J3-147 to the FPGA on the TMS_TO_FPGA_MEZZ J3-142 FPGA Mezzanine TDO_FROM_FPGA_MEZZ J3-148 card. ACCESS_SIGNAL_1_FROM_FPGA J3-41 AE12 IO_L7P_T1_10 ACCESS_SIGNAL_2_FROM_FPGA J3-43 AF12 IO_L7N_T1_10 PHY_1_TRD0_6_CMP J2-21 \ PHY_1_TRD0_6_DIR J2-23 | | PHY_1_TRD1_6_CMP J2-17 | PHY_1_TRD1_6_DIR J2-19 | Ethernet Connection | to the FPGA's PHY_1_TRD2_6_CMP J2-13 | Processor Section PHY_1_TRD2_6_DIR J2-15 | | PHY_1_TRD3_6_CMP J2-9 | PHY_1_TRD3_6_DIR J2-11 / PHY_2_TRD0_6_CMP J2-37 \ PHY_2_TRD0_6_DIR J2-39 | | PHY_2_TRD1_6_CMP J2-33 | PHY_2_TRD1_6_DIR J2-35 | Ethernet Connection | to the FPGA's PHY_2_TRD2_6_CMP J2-29 | Logic Section PHY_2_TRD2_6_DIR J2-31 | | PHY_2_TRD3_6_CMP J2-25 | PHY_2_TRD3_6_DIR J2-27 / FPGA Select I/O connections to the Ethernet Phys Chips: These connections are internal to the FPGA Mezzanine itself. See FPGA Mezz Schematic pages: 10, 11, 19, 28, and 29. Processor Section U18 Enet Physical Chip Zync FPGA Select I/O ------------------ ---------------------- Pin No. Pin Name FPGA Mezz Net Name Pin No. Pin Name ------- -------- ------------------ ------- ------------ 46 RX_CLK ETH1_RXCK L20 PS_MIO22_501 43 RX_CTRL ETH1_RXCTL G20 PS_MIO27_501 44 RXD0 ETH1_RXD0 J21 PS_MIO23_501 45 RXD1 ETH1_RXD1 M19 PS_MIO24_501 47 RXD2 ETH1_RXD2 G19 PS_MIO25_501 48 RXD3 ETH1_RXD3 M17 PS_MIO26_501 53 TX_CLK ETH1_TXCK L19 PS_MIO16_501 56 TX_CTRL ETH1_TXCTL J19 PS_MIO21_501 50 TXD0 ETH1_TXD0 K21 PS_MIO17_501 51 TXD1 ETH1_TXD1 K20 PS_MIO18_501 54 TXD2 ETH1_TXD2 J20 PS_MIO19_501 55 TXD3 ETH1_TXD3 M20 PS_MIO20_501 14 LED0 PHY1_LED0 B12 IO_L20N_T3_AD6N_35 13 LED1 PHY1_LED1 C12 IO_L20P_T3_AD6P_35 12 LED2/INTn ETH1_INT A15 IO_L21N_T3_DQS_AD14N_35 15 CONFIG ETH1_CONFIG F14 IO_L12N_T1_MRCC_35 9 CLK125 ETH1_CLK125 E16 IO_L13P_T2_MRCC_35 16 RESETn ETH1_RESET CPLD U14 Pin 53 page 25 7 MDC ETH1_MDC D19 PS_MIO52_501 8 MDIO ETH1_MDIO C18 PS_MIO53_501 Logic Section U20 Enet Physical Chip Zync FPGA Select I/O ------------------ ---------------------- Pin No. Pin Name FPGA Mezz Net Name Pin No. Pin Name ------- -------- ------------------ ------- ------------ 46 RX_CLK ETH2_RXCK AD18 IO_L12P_T1_MRCC_9 43 RX_CTRL ETH2_RXCTL AE20 IO_L19N_T3_VREF_9 44 RXD0 ETH2_RXD0 AD20 IO_L19P_T3_9 45 RXD1 ETH2_RXD1 AD19 IO_L12N_T1_MRCC_9 47 RXD2 ETH2_RXD2 AB20 IO_L14N_T2_SRCC_9 48 RXD3 ETH2_RXD3 AB19 IO_L14P_T2_SRCC_9 53 TX_CLK ETH2_TXCK AC19 IO_L11N_T1_SRCC_9 56 TX_CTRL ETH2_TXCTL AC18 IO_L11P_T1_SRCC_9 50 TXD0 ETH2_TXD0 AA20 IO_L6N_T0_VREF_9 51 TXD1 ETH2_TXD1 Y20 IO_L6P_T0_9 54 TXD2 ETH2_TXD2 AA19 IO_L13N_T2_MRCC_9 55 TXD3 ETH2_TXD3 AA18 IO_L13P_T2_MRCC_9 14 LED0 PHY2_LED0 K15 IO_L5P_T0_AD9P_35 13 LED1 PHY2_LED1 B16 IO_L17N_T2_AD5N_35 12 LED2/INTn ETH2_INT A17 IO_L18N_T2_AD13N_35 15 CONFIG ETH2_CONFIG E15 IO_L13N_T2_MRCC_35 9 CLK125 ETH2_CLK125 F15 IO_L12P_T1_MRCC_35 16 RESETn ETH2_RESET B15 IO_L21P_T3_DQS_AD14P_35 7 MDC ETH2_MDC C17 IO_L17P_T2_AD5P_35 8 MDIO ETH2_MDIO B17 IO_L18P_T2_AD13P_35 Life Boat Signals to and from the FPGA Mezzanine: ------------------------------------------------- All of the following signals are made available on the HTM Card's J11 connector. The 8 "Special Control and Power" signals are also provided with pull-up / pull-down SMD pads and a via for a wire connection. FPGA HTM Card Mezz Signal Name Pin No. FPGA Pin Number and Name ---------------- ---------- -------------------------- LB_FPGA_SEL_IO_1 J3-107 AK22 IO_L2P_T0_11 LB_FPGA_SEL_IO_2 J3-113 AJ20 IO_L15P_T2_DQS_11 LB_FPGA_SEL_IO_3 J3-119 AJ21 IO_L3P_T0_DQS_11 LB_FPGA_SEL_IO_4 J3-125 AH19 IO_L17P_T2_11 LB_CPLD_GPIO_3 J2-16 \ LB_CPLD_GPIO_4 J2-18 | LB_CPLD_GPIO_5 J2-20 | LB_VBAT_IN J3-124 | Special Control and Power LB_CONFIGX J3-129 | pins on the FPGA Mezzanine LB_RESIN J3-130 | card - most to/from the CPLD. LB_BOOTMODE J3-135 | LB_JTAGENB J3-136 / CPLD_M_TCK J3-81 JTAG connection CPLD_M_TDI J3-87 to the CPLD on the CPLD_M_TDO J3-88 FPGA Mezzanine CPLD_M_TMS J3-82 card. Power Supply and Ground Connections to the FPGA Mezzanine: ---------------------------------------------------------- ISO_12V and BULK_3V3 are provided to the FPGA Mezzanine. MEZZ_3V3 and MEZ_1V8 are generated by the FPGA Mezzanine. HTM Card Signal Name FPGA Mezzanine Pin Numbers ----------- ----------------------------------------------- ISO_12V J2-165 J2-167 J2-166 J2-168 BULK_3V3 J2-147 J2-148 MEZZ_1V8 J1-99 J1-159 J1-169 J1-171 J1-100 J1-160 J1-170 J1-172 MEZZ_3V3 J2-111 J2-123 J2-135 J2-169 J2-171 J2-112 J2-124 J2-136 J2-170 J2-172 J3-99 J3-100 J3-159 J3-160 J2-159 J2-160 J2-99 J2-100 GROUND J1-51 J1-57 J1-63 J1-69 J1-75 J1-81 J1-87 J1-93 J1-111 J1-117 J1-123 J1-129 J1-135 J1-141 J1-147 J1-153 J1-161 J1-163 J1-165 J1-167 J1-52 J1-58 J1-64 J1-70 J1-76 J1-82 J1-88 J1-94 J1-112 J1-118 J1-124 J1-130 J1-136 J1-142 J1-148 J1-154 J1-162 J1-164 J1-166 J1-168 J2-45 J2-93 J2-105 J2-117 J2-129 J2-141 J2-153 J2-161 J2-163 J2-46 J2-52 J2-58 J2-64 J2-70 J2-76 J2-82 J2-88 J2-94 J2-106 J2-118 J2-130 J2-142 J2-154 J2-162 J2-164 J3-45 J3-51 J3-57 J3-63 J3-69 J3-75 J3-93 J3-105 J3-111 J3-117 J3-123 J3-153 J3-161 J3-163 J3-165 J3-167 J3-169 J3-171 J3-46 J3-52 J3-58 J3-64 J3-70 J3-94 J3-106 J3-112 J3-118 J3-154 J3-162 J3-164 J3-166 J3-168 J3-170 J3-172