xc7z035 ffg900 Package Pin to FPGA Mez Connector Pin -------------------------------------------------------- MGT GTX Banks 109 110 111 112 ----------------------------------- Original Rev. 9-Mar-2018 Current Rev. 9-Mar-2018 HTM FPGA Mezz Trenz TE0782 Memory J1 J2 J3 Connector Byte VCCAUX I/O ------------------ Pin Pin Name Group Bank Group Type Number Name --- ----------- ----- ---- ----- ------ ------- --------- AK2 MGTXTXP3_109 NA 109 NA GTX J3-19 MGT_TX3_P AK1 MGTXTXN3_109 NA 109 NA GTX J3-17 MGT_TX3_N AJ4 MGTXTXP2_109 NA 109 NA GTX J3-23 MGT_TX2_P AJ3 MGTXTXN2_109 NA 109 NA GTX J3-21 MGT_TX2_N AK6 MGTXTXP1_109 NA 109 NA GTX J3-27 MGT_TX1_P AK5 MGTXTXN1_109 NA 109 NA GTX J3-25 MGT_TX1_N AK10 MGTXTXP0_109 NA 109 NA GTX J3-31 MGT_TX0_P AK9 MGTXTXN0_109 NA 109 NA GTX J3-29 MGT_TX0_N AE8 MGTXRXP3_109 NA 109 NA GTX J3-20 MGT_RX3_P AE7 MGTXRXN3_109 NA 109 NA GTX J3-18 MGT_RX3_N AG8 MGTXRXP2_109 NA 109 NA GTX J3-24 MGT_RX2_P AG7 MGTXRXN2_109 NA 109 NA GTX J3-22 MGT_RX2_N AJ8 MGTXRXP1_109 NA 109 NA GTX J3-28 MGT_RX1_P AJ7 MGTXRXN1_109 NA 109 NA GTX J3-26 MGT_RX1_N AH10 MGTXRXP0_109 NA 109 NA GTX J3-32 MGT_RX0_P AH9 MGTXRXN0_109 NA 109 NA GTX J3-30 MGT_RX0_N AF10 MGTREFCLK1P_109 NA 109 NA GTX MGT_CLK3_P from AF9 MGTREFCLK1N_109 NA 109 NA GTX MGT_CLK3_N Si5338A AD10 MGTREFCLK0P_109 NA 109 NA GTX no connection AD9 MGTREFCLK0N_109 NA 109 NA GTX no connection AD2 MGTXTXP3_110 NA 110 NA GTX J3-3 MGT_TX7_P AD1 MGTXTXN3_110 NA 110 NA GTX J3-1 MGT_TX7_N AE4 MGTXTXP2_110 NA 110 NA GTX J3-7 MGT_TX6_P AE3 MGTXTXN2_110 NA 110 NA GTX J3-5 MGT_TX6_N AF2 MGTXTXP1_110 NA 110 NA GTX J3-11 MGT_TX5_P AF1 MGTXTXN1_110 NA 110 NA GTX J3-9 MGT_TX5_N AH2 MGTXTXP0_110 NA 110 NA GTX J3-15 MGT_TX4_P AH1 MGTXTXN0_110 NA 110 NA GTX J3-13 MGT_TX4_N AD6 MGTXRXP3_110 NA 110 NA GTX J3-4 MGT_RX7_P AD5 MGTXRXN3_110 NA 110 NA GTX J3-2 MGT_RX7_N AF6 MGTXRXP2_110 NA 110 NA GTX J3-8 MGT_RX6_P AF5 MGTXRXN2_110 NA 110 NA GTX J3-6 MGT_RX6_N AG4 MGTXRXP1_110 NA 110 NA GTX J3-12 MGT_RX5_P AG3 MGTXRXN1_110 NA 110 NA GTX J3-10 MGT_RX5_N AH6 MGTXRXP0_110 NA 110 NA GTX J3-16 MGT_RX4_P AH5 MGTXRXN0_110 NA 110 NA GTX J3-14 MGT_RX4_N AC8 MGTREFCLK1P_110 NA 110 NA GTX J3-39 MGT_CLK1_N AC7 MGTREFCLK1N_110 NA 110 NA GTX J3-37 MGT_CLK1_P AA8 MGTREFCLK0P_110 NA 110 NA GTX MGT_CLKO_P from AA7 MGTREFCLK0N_110 NA 110 NA GTX MGT_CLK0_N Si5338A V2 MGTXTXP3_111 NA 111 NA GTX J1-14 MGT_TX11_P V1 MGTXTXN3_111 NA 111 NA GTX J1-16 MGT_TX11_N W4 MGTXTXP2_111 NA 111 NA GTX J1-10 MGT_TX10_P W3 MGTXTXN2_111 NA 111 NA GTX J1-12 MGT_TX10_N Y2 MGTXTXP1_111 NA 111 NA GTX J1-6 MGT_TX9_P Y1 MGTXTXN1_111 NA 111 NA GTX J1-8 MGT_TX9_N AB2 MGTXTXP0_111 NA 111 NA GTX J1-2 MGT_TX8_P AB1 MGTXTXN0_111 NA 111 NA GTX J1-4 MGT_TX8_N AA4 MGTXRXP3_111 NA 111 NA GTX J1-13 MGT_RX11_P AA3 MGTXRXN3_111 NA 111 NA GTX J1-15 MGT_RX11_N Y6 MGTXRXP2_111 NA 111 NA GTX J1-9 MGT_RX10_P Y5 MGTXRXN2_111 NA 111 NA GTX J1-11 MGT_RX10_N AB6 MGTXRXP1_111 NA 111 NA GTX J1-5 MGT_RX9_P AB5 MGTXRXN1_111 NA 111 NA GTX J1-7 MGT_RX9_N AC4 MGTXRXP0_111 NA 111 NA GTX J1-1 MGT_RX8_P AC3 MGTXRXN0_111 NA 111 NA GTX J1-3 MGT_RX8_N W8 MGTREFCLK1P_111 NA 111 NA GTX MGT_CLK5_P from W7 MGTREFCLK1N_111 NA 111 NA GTX MGT_CLK5_N Si5338A U8 MGTREFCLK0P_111 NA 111 NA GTX J1-40 MGT_CLK4_N U7 MGTREFCLK0N_111 NA 111 NA GTX J1-38 MGT_CLK4_P N4 MGTXTXP3_112 NA 112 NA GTX J1-30 MGT_TX15_P N3 MGTXTXN3_112 NA 112 NA GTX J1-32 MGT_TX15_N P2 MGTXTXP2_112 NA 112 NA GTX J1-26 MGT_TX14_P P1 MGTXTXN2_112 NA 112 NA GTX J1-28 MGT_TX14_N R4 MGTXTXP1_112 NA 112 NA GTX J1-22 MGT_TX13_P R3 MGTXTXN1_112 NA 112 NA GTX J1-24 MGT_TX13_N T2 MGTXTXP0_112 NA 112 NA GTX J1-18 MGT_TX12_P T1 MGTXTXN0_112 NA 112 NA GTX J1-20 MGT_TX12_N P6 MGTXRXP3_112 NA 112 NA GTX J1-29 MGT_RX15_P P5 MGTXRXN3_112 NA 112 NA GTX J1-31 MGT_RX15_N T6 MGTXRXP2_112 NA 112 NA GTX J1-25 MGT_RX14_P T5 MGTXRXN2_112 NA 112 NA GTX J1-27 MGT_RX14_N U4 MGTXRXP1_112 NA 112 NA GTX J1-21 MGT_RX13_P U3 MGTXRXN1_112 NA 112 NA GTX J1-23 MGT_RX13_N V6 MGTXRXP0_112 NA 112 NA GTX J1-17 MGT_RX12_P V5 MGTXRXN0_112 NA 112 NA GTX J1-19 MGT_RX12_N R8 MGTREFCLK1P_112 NA 112 NA GTX no connection R7 MGTREFCLK1N_112 NA 112 NA GTX no connection N8 MGTREFCLK0P_112 NA 112 NA GTX MGT_CLK6_P from N7 MGTREFCLK0N_112 NA 112 NA GTX MGT_CLK6_N Si5338A AB10 MGTAVTTRCAL_112 NA 112 NA GTX R6 100 Ohm & 1.2V_MGT AB9 MGTRREF_112 NA 112 NA GTX R6 100 Ohm Notes on the Remaining 16 Pins in the Differential Pins Area of Connectors J1 and J3: ----------------------------------------------- HTM FPGA Mezz Trenz TE0782 J1 J2 J3 Connector ------------------ Actual Connection on the Trens FPGA Mezz Number Name ---------------------------------------------- ------- --------- FPGA Pin F3 IO_L14N_T2_SRCC_33 HP J1-33 J1_TX20_N FPGA Pin F4 IO_L14P_T2_SRCC_33 HP J1-35 J1_TX20_P FPGA Pin K6 IO_L6P_T0_33 HP J1-37 J1_TX21_N FPGA Pin J6 IO_L6N_T0_VREF_33 HP J1-39 J1_TX21_P FPGA Pin E5 IO_L13N_T2_MRCC_33 HP J1-34 J1_RX20_N FPGA Pin F5 IO_L13P_T2_MRCC_33 HP J1-36 J1_RX20_P see above Bank 111 pin U7 J1-38 MGT_CLK4_P see above Bank 111 pin U8 J1-40 MGT_CLK4_N FPGA Pin AF13 IO_L11N_T1_SRCC_10 HR J3-33 J3_TX20_N FPGA Pin AE13 IO_L11P_T1_SRCC_10 HR J3-35 J3_TX20_P see above Bank 110 pin AC7 J3-37 MGT_CLK1_P see above Bank 110 pin AC8 J3-39 MGT_CLK1_N FPGA Pin AG14 IO_L12N_T1_MRCC_10 HR J3-34 J3_RX20_N FPGA Pin AF14 IO_L12P_T1_MRCC_10 HR J3-36 J3_RX20_P U2 Si5338A Pin 2 Signal IN2 J3-38 Si5328_CLK1_P U2 Si5338A Pin 1 Signal IN1 J3-40 Si5328_CLK1_N MGT Reference Clocks from the Si5338A to the MGT Banks: --------------------------------------------------------- U2 Si5338A In / Out DC Blk Cap Clk Outputs --------------------- ------------- Net Connects to Pin Signal Name Net Name FPGA MGT Bank Pin No. Name to Cap from Cap Signal Name No. --- ------ ------ ---------- --------------- --- 22 CLK0A CLK2_P MGT_CLK6_P MGTREFCLK0P_112 N8 21 CLK0B CLK2_N MGT_CLK6_N MGTREFCLK0N_112 N7 18 CLK1A CLK3_P MGT_CLK5_P MGTREFCLK1P_111 W8 17 CLK1B CLK3_N MGT_CLK5_N MGTREFCLK1N_111 W7 14 CLK2A CLK0_P MGT_CLK0_P MGTREFCLK0P_110 AA8 13 CLK2B CLK0_N MGT_CLK0_N MGTREFCLK0N_110 AA7 10 CLK3A CLK1_P MGT_CLK3_P MGTREFCLK1P_109 AF10 9 CLK3B CLK1_N MGT_CLK3_N MGTREFCLK1N_109 AF9 | | | |<----- Pg 21 ----->|<----------------- Pg 9 ---------------->| Schematic Page Numbers Notice that for normal operation where all 4 MGT Banks are operating from Reference Clocks provided by the Si5338A clock generator chip: MGT Bank 109 uses its Ref Clk 1 MGT Bank 110 uses its Ref Clk 0 MGT Bank 111 uses its Ref Clk 1 MGT Bank 112 uses its Ref Clk 0