Project Log Book for the HTM_0 Board Design ----------------------------------------------- The most recent entries appear first in this log book file. ------------------------------------------------------------------------ DATE: -Oct-2018 Topic(s): ------------------------------------------------------------------------ DATE: 12-Oct-2018 Topic(s): HTM FPGA Receiver for the 40.08 MHz AC Coupled Logic Clock, Programming Configuration Flash HTM FPGA Receiver for the 40.08 MHz AC Coupled Logic Clock: The Zynq xc7z035 on the HTM Card uses a 3.3 Volt HR Select I/O Bank to receive the Differential AC Coupled 40.08 MHz Logic Clock. This is a Series 7 HR type Select I/O Bank. The Logic Clock is received on pins: AE22 IO_L12P_T1_MRCC_11 AF22 IO_L12N_T1_MRCC_11 i.e. on a differential "global clock" pin pair. The data sheet specifications for this Series 7 HR Bank LVDS differential input are: (from DS-183) This is specified with a Bank Vcco voltage of 2.5 Volts. Differential Input Voltage: 100 mV min 350 mV typ 600 mV max Differential Input Voltage is defined as (Dir - Cmp) Dir Hi (Cmp - Dir) Cmp Hi Input Common Mode: 300 mV min 1.20 V typ 1.50 V max Note that 900 mV is half way between min and max common mode. Looking at the other types of differential inputs (e.g. DIF_HSTL, DIF_SSTL, RSDS_25): the minimum differential signal is usually 100 mV the minimum common mode is usually 300 mV the typical common mode is usually 600 mV to 900 mV the maximum common mode is usually 1500 mV The FW from Pawel for this testing is in hubdev2: /home/hubuser/FW_releases/HTM/testing/ CombinedTTC_TXRX_TermFalse CombinedTTC_TXRX_TermTrue In the initial test on 9-Oct-2018 with the TermFalse FW and without any control of the DC bias to the LVDS receiver inputs: The Access Signal 1 waveform was not stable but rather changed in width and the 10 Meg impedance of the scope applied to one receiver input or the other would bias the receiver into cutoff with the output either Hi or Low. With the scope probe removed the Access Signal 1 pattern would slowly return after 5 seconds or so. In the initial test on 9-Oct-2018 with the TermTrue FW and without any control of the DC bias to the LVDS receiver inputs: The Access Signal 1 waveform looked OK, at the vertical midpoint it was HI for about 10 nsec and Low for about 15 nsec. The differential swing was about 350 mVpp. The common mode at the receiver side of the coupling caps was up at about 2 Volts. Probing the receiver inputs with the 10 Meg Ohm scope probe pulls both inputs down, i.e. you can see that the terminator is there. Now with 4.99k Ohm resistors across the 47 nFd coupling capacitors C266 and C267 and with Pawel's With Terminator FW CombinedTTC_TXRX_TermTrue configured into the HTM FPGA: FPGA Receiver 1.2208 V C226 1.1973 V Fanout Driver FPGA Receiver 1.2226 V C227 1.2435 V Fanout Driver Voltage across C226 23.5 mV with 4.99k Ohm --> 4.71 uA Voltage across C227 20.9 mV with 4.99k Ohm --> 4.19 uA Voltage across FPGA Term 1.8 mV This all looks OK but note that although the LVDS receiver runs off of the Vccaux 1.8 Volt supply. The Vccaux rail provides power to the bankâs differential input buffer circuits used for the differential and VREF I/O standards. Select I/O Guide Pg 18. The Vcco of the I/O bank must be connected to 1.8V for LVDS, and 2.5V for the LVDS_25 I/O standards to provide 100 Ohm of effective differential termination. DIFF_TERM is only available for inputs and can only be used the appropriate Vcco voltage. On the Trens FPGA card this is a 3.3 Volt Vcco Bank. See Sel I/O Guide Pg 49. I need to verify that 100 Ohm termination is within some reasonable range. The LVDS and AC coupling of LVDS is shown in the Sel I/O Guide pages 91 through 93. Now running with Pawel's 11-Oct-2018 version of test FW with the LVDS input for the 40.08 MHz Logic Clock explicitly called out as LVDS_25 with DIFF_TERM = TRUE and the Access_Signal_1 called out as LVCMOS33: 4.99k Ohm across the AC Coupling caps. FPGA Receiver 1.2210 V C226 1.1977 V Fanout Driver FPGA Receiver 1.2226 V C227 1.2429 V Fanout Driver Voltage across C226 23.3 mV with 4.99k Ohm --> 4.67 uA Voltage across C227 20.3 mV with 4.99k Ohm --> 4.07 uA Voltage across FPGA Term 1.6 mV The Access_Signal_1 output from the HTM of the 40.08 MHz Logic Clock signal now looks nice and symmetric at its half amplitude points. Note that all of the above tests have been done with HTM SN-15. The version of the FW that was used for the final testing of the Logic Clock reception comes from hubdev2: /home/hubuser/FW_releases/HTM/testing/CombinedTTC_TXRX_TermTrue/bitstream/v1 hubuser hubuser 13321522 Oct 11 05:16 htm_combTTC_TXRX_exdes.bit Here are the instructions to program the Configuration Flash Memory on the HTM Cards: The QSPI Configuration memory on the HTM is a: FPGAS25FL256SAGBHI20 1. Open Hardware Manager 2. Right click on the xc7z035 3. Select - Add Configuration Memory device 4. choose: S25FL256S-3.3V-qspi-X4-Signal, click OK 5. Do you want to Program the Configuration Memory Device Now ? click OK 6. Add the Configuration file: /home/hubuser/FW_releases/HTM/bootimage/BOOT.bin At the test bench: /HTM_FW/Boot_Image/BOOT.bin 7. Add the Zynq FSBL file: No - currently I *think* that I do not need to specify / include a FSBL file. 8. Under Program Operations: take the defaults i.e. Address Range -- Configuration Only Erase - check Blank Check - not checked Program - check verify - check 9. Click Apply and then OK. 10. Wait about 2 minutes. Done. Notes: I believe that this current BOOT.bin only sets up the SiLabs clock chip so that it provides 4 copies of 320.64 MHz Reference Clk to the MGT Banks. The setup of the SiLabs part is described in: .../htm/hardware/components/Clocks/htm_silab_clock_gen_data from 10-Aug-2018 The build of this .bin file comes from hubdev: /home/hubuser/Xilinx/Design/HTM/HTM_FSBL_SI5338/ test_board/vivado/test_board.sdk/zynq_fsbl When the HTM FPGA powers up with this in its Config Flash the whole "run time" for this startup program to setup the SiLabs clock chip is only about 2 seconds - then the LED flashing stops. The LEDs on the HTM FPGA Mezzanine only flash about two times then just the red one is on constant and dim. ------------------------------------------------------------------------ DATE: 11-Sept-2018 Topic(s): HTMs in 14 Slot Shelf 12 HTMs sending 6 lanes of IBERT data to each of 2 Hubs, with a ROD included on Hub #1, and Combined Data IBERT links running to the 12 HTMs was all running and stable at 6.4 Gbps 7 prbs (228 lanes total being checked) on 15-Aug-2018. 12 HTMs sending 6 lanes of IBERT data to each of 2 Hubs, and Combined Data IBERT links running to the 12 HTMs and IPBus Random Register Test running full blast on the 12 HTMs was all running and stable at 6.4 Gbps 31 prbs on 10-Sept-2018. ------------------------------------------------------------------------ DATE: 24-Aug-2018 Topic(s): Final Assembly of HTMs MSU Final Assembly was completed on the HTMs with the following schedule: 1 HTM was available for use in the ATCA Shelf on July 29 5 HTMs were available for use in the ATCA Shelf on Aug 3 13 HTMs were available for use in the ATCA Shelf on Aug 15 20 HTMs were available for use in the ATCA Shelf on Aug 24 HTMs SN 1 through 14 have FPGA Mezz cards installed on them that came from the components storage drawer in Rm 2150. HTM SN-15 has the FPGA Mezz installed on it that was originally installed on a Trens Base Board that was used down in the lab room with the two ATCA Shelves. HTMs SN 16 through 20 do not have an FPGA Mezzanine installed on them. ------------------------------------------------------------------------ DATE: 26-July-2018 Topic(s): Pickup the HTM Cards Drove over to Debron to pickup the 20 HTM Cards and all of the parts left over from assembly. Jack said that it was an easy build; only a couple of the cards have the LEMOs up a little, and I need to remove the chicklet from J/P 10. ------------------------------------------------------------------------ DATE: 20-July-2018 Topic(s): Anodize and Silkscreen Anodize: Shipped Out: 28-June Returned: 16-July Silkscreen: Delivered: 18-July Returned: 2-Aug ------------------------------------------------------------------------ DATE: 28-June-2018 Topic(s): Shipment to Alpha Metal Mechanical Parts - Hub HTM Today I shipped to Alpha Metal 113 parts of 5 types. These parts are a full set for HTM and a couple of things for Hub. Jamie is still the person at Alpha who appears to setup jobs like ours. Parts shipped to Alpha Metal Finishing today: Item Qty Color Aprox. Size ----------- --- ----- ------------------- Front Panel 23 Green 12.6" 1.2" 0.7" 21 HTM, 2 Hub FPGA HS 18 Black 4.5" 4.0" 0.4" Mini HS 24 Black 1.5" 1.4" 0.3" Horz Baffle 24 Black 10.5" 0.5" 0.25" Vert Baffle 24 Black 4.6" 0.8" 0.25" This set of 113 parts represents 929 holes of which 240 are tapped holes and 1251 machined edges or surfaces. All edges are broken, deburred, holes chamfered, and parts have been washed clean. Inventory of mechanical parts for Hub Module and HTM Card: Front Panel HTM Card: 21 sent out for anodizing 0 more needed Front Panel Hub Module: 2 sent out for anodizing 8 on prototype Hub Modules extra holes ---> 26 more needed FPGA Heat Sink Filler Blocks: 27 fully finished in stock 4 partially finished in stock 8 in use in prototype Hub Modules 0 more needed Hub FPGA Heat Sinks: 18 sent out for anodizing 11 in stock need deburr, clean, & anodize 8 in use in prototype Hub Modules 0 more needed MiniPOD Heat Sinks: 24 sent out for anodizing 36 in stock need deburr, clean, & anodize 8 (aprox) non-anodized on prototype Hubs ---> ?? more needed to match spare MiniPOD count HTM Horizontal Air Baffle: 24 sent out for anodizing 0 more needed HTM Vertical Air Baffle: 24 sent out for anodizing 0 more needed Top Bracket FP Hub & HTM: 21 fully finished in stock 8 in use in the prototype Hubs ---> 19 more needed Mid Bracket FP Hub: 32 fully finished in stock 0 more needed Bot Bracket FP Hub & HTM: 22 fully finished in stock 8 in use in the prototype Hubs ---> 18 more needed Hub Zone 3 Air Filler Blocks: 57 ready to use in stock 0 more needed The above "more needed" counts are based on there being: 8 prototype Hubs, 20 production Hubs, and 20 HTM Cards. ------------------------------------------------------------------------ DATE: 7-June-2018 Topic(s): Thursday Hub/HTM Meeting HTM assembly speed up Two hour meeting on Hub and HTM. I owe Gabriel a note about what registers to monitor in the MiniPODs and the drawing of the I2C bus on the Hub+ROD, and power supply list to monitor on the Hub. Note to George to ask about speeding up the HTM build. ------------------------------------------------------------------------ DATE: 6-June-2018 Topic(s): Deliver the HTM Card Parts Kit to Debron Drove to Debron and delivered the HTM Card Parts Kit. I believe that they are busy but not in panic mode busy. Delivered the Packing List and Component Description and discussed: 100 nFd cap is now supplied as 150 nFd, teflon tape on the LEMO connectors, clock fanout double label and "D1204" is its correct top-marking. Discussed that I can install the press-in connectors if there is any problems with the support jig for the HTM and Jack verified that we did not need to mill the top/bot back edges of the HTM. Talked with George, Josh, and Jack. I believe that Debron did not actually release TTM to build the HTM bare board until after we talked today - smart. ------------------------------------------------------------------------ DATE: 4-June-2018 Topic(s): Start build of HTM bare board Sent a note to Josh OKing the June 1st version of the HTM Card stackup and asking him to go ahead and have the HTM bare boards manufactured. PCB topics learned about during the HTM approval: "Secondary Drilling" of the non-plated holes that I use with the copper "washers". Secondary Drilling is done before etching to avoid burs. Secondary drilling is in their dbe file. Their drl file includes both the plated and non-plated normal holes. For holes that are going to be plugged they do not want the Solder Mask relieved - but yes relieve it on all other holes. The Solder Mask that is against the top and bottom layer of traces has a Df of about 0.0190 vs the FR408HR laminate Df of about 0.0098 to 0.0083 range. ------------------------------------------------------------------------ DATE: 30-May-2018 Topic(s): Study HTM Stackup and Plots, HTM Parts Kit The HTM stackup and plots that we received on the 24th became available in gwk format Wednesday noon. So far the issues are: - Dielectric thickness between L5-L6 too thin, between L4-L5 too thick, between L6-L7 too think. Note sent about this Wednesday morning. - Plated vs un-plated drill holes and the drl and dbe files. If the dbe file is the un-plated holes then some are missing. If the drl file is just the plated holes then some of my un-plated holes have gotten moved into it. Note sent about this Wednesday at close of business. - Postponed the scheduled Kit drop off from Thur May 31 to Wed June 6th. The 100 Ohm stuff in HTM looks OK, i.e. L1...L4 is good and L7...L10 looks good. The plots back from TTM are: in inches 2.6, offset by 0.4" for the rail, and of a different number. Philippe has neat idea to look at Mentor plots and TTM plots on top of each other to look for differences. No word back from TTM yet. ------------------------------------------------------------------------ DATE: 24-May-2018 Topic(s): HTM pcb Stackup We received the proposed Stackup for the HTM pcb today. It is from the normal good place - TTM Technology ViaSystems. It is from a different person than either Hub or CMX. From a quick first look it seems OK but still requires a serious study. ------------------------------------------------------------------------ DATE: 21-May-2018 Topic(s): Bar Stock Order, Screw Lengths I had to order more bar stock for the Air Baffles because I had made a mistake in calculating how many full pieces of each baffle type you can get from a 3 foot bar. You can get 7 of the Vertical baffles per bar and only 3 of the Horizontal baffles per par. As normal to help reduce the chance of loose screws coming out and causing short circuits the intent is to use lots of thread turns. 4-40 button head screws have been ordered for the following plan: Front Panel to Horz Air Baffle, 3/8", should give 13.0 threads Vert to Horz Air Baffles, 9/16", should give 12.5 threads Board to Air Baffles 7/16", should give 13.6 threads All of the parts are being made with 20 good threads. ------------------------------------------------------------------------ DATE: 14,15-May-2018 Topic(s): Mechanical Parts and PO Monday - Started the work order for the front panel and the air baffles in the Machine Shop. Tuesday - The PO to build the 20 HTM cards was finally sent to the assembly vendor by MSU Purchasing. ------------------------------------------------------------------------ DATE: 27-Apr-2018 Topic(s): Mechanical Drawings and Parts Order Start the mechanical drawings for the HTM front panel. ------------------------------------------------------------------------ DATE: 26-Apr-2018 Topic(s): Bulk 2V5 and 3V3 V Set Resistors HTM Build Parts Inventory & Orders The trim pot and resistor setup for the Bulk_2V5 and Bulk_3V3 supplies is: 1k to Gnd, 100 Ohm Trim Pot, 1070 Ohm to Bulk_2V5 and 1780 Ohm to Bulk_3V3. This gives trim ranges of: Bulk_2V5: 2.387 V -4.5% to 2.626 V +5.0% Bulk_3V3: 3.168 V -4.0% to 3.485 V +5.6% ------------------------------------------------------------------------ DATE: 25-Apr-2018 Topic(s): Next to final checking and then HTM PO asked for and design released to Debron, start parts work HTM design checking via Philippe's netname to manufacturers pin name comparison and his Gerber viewer. Both are very good tools and I must use them more. Found that the Not Installed list was missing U253. Sent notes to Janice, Brenda to get the HTM assembly PO and to Debron pointing to the design area on the web. Started work on the parts that need to be ordered and the inventor for the HTM build kit. ------------------------------------------------------------------------ DATE: 24-Apr-2018 Topic(s): Work on production release files The current final traces without fills is traces_109. Copy this traces file to a backup traces_109_save. From layout run the design rule checker with the clearance constraints from htm_drc_run_notes.txt which are: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.40 0.35 Trace 0.16 0.32 0.26 Fill 0.35 0.35 0.50 0.50 Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 1.00 1.00 Trace 0.22 1.00 0.26 Fill 0.35 0.35 0.50 0.50 Note that all of the Fill clearance limits were just set by how the Fills were generated. Note that since the clean up work over the weekend and yesterday on the Clock diff pair polarity, you can run with default via to via clearance of 0.45 mm and still have zero clearance errors. Note while in Layout make a final current trace length file. The diff pair Logic Clock to the FPGA have a skew of 2.65 mm. Note after running DRC then rm .../pcb/check/check_report Backup at tar tues_1 OK, start the build from comps_194 (Spencer_mentor), nets_120, traces_109 = 109_save without fills, sperture_29 from 12-Apr-18. No change in versions or counts from close of business yesterday. Follow the build procedure as shown in 20-Apr-18 log book entry which is the same as the 18-Apr-18. - generate_drill_table_and_drill_files.sh Now at drill table 44 with no change from before. No change in plated or un-plated file size. - generate_all_htm_fills.sh This makes traces_110. Move traces_109 to traces_109_orig to make sure it is saved. Recall that it is important to generate the Fills before generating the Gerber data even for the layers that do not include any Fills. This is because some extra pads may occur if you generate gerber files for certain layers from a traces file that does not include the fills. This is because, before the fills are generated and in the traces file, the traces file does not know that a given net will eventually be connected to a fill, and the routing for a given trace may have gotten as far as a via that is going to a non surface layer, and the pad for that via may appear in your gerber for an internal layer. - Look at htm in mentor layout to see the new traces_110 with all Fills and to check the counts. Components 482 Nets 699 Connections 1371 Finished 1371 UnFinished 0 Guides 0 Shapes 10 Fills 10 - generate_gerber_all_16_plots_for_htm.sh No errors, no missing apertures, no painting - remove_most_ground_thermal_relief.sh The new no-therm file sizes are slightly bigger than before as expected. - I'm going to go with the top gnd plane on Ls 2 and 4 and the bottom gnd pln on Ls 7 and 9 - so rename accordingly. ..._gnd_plane_L2_... ---> ..._gnd_plane_Ls_2_4_... ..._gnd_plane_Ls_4_7_9_... ---> ..._gnd_plane_Ls_7_9_... - The back-drill configuration files are pointing at traces_109_save then run: backdrill_most__generate.sh backdrill_zone2_generate.sh no errors and no changes in output file sizes when generating either set of back-drill files. If there were any change (or possibility of a change) then I should run the script to make a new HTM pcb geometry so that I would have current mentor back-drill circles to look at. I will do this. Backup at tar tues_2 comps_194, nets_120, trac_110 Move all of these Bare Boards files to the web. Edit the aaa bare board assembly instructions in moto .../Release_2/ to make them current and to remove some small traces of the bid version and for current hole counts then copy to web. Copy the AMP ATCA connector document to the bare board area. Notice that I really should have run the center conductor to the two LEMO connectors on an internal or bottom signal layer. As it is it is on the Top signal layer and in theory could contact the grounded body of the LEMO connector. I may move the two LEMO connectors to the Not Installed by the assembly house list and put them in during MSU Final Assembly with Kapton tape over these traces. Backup at tar tues_3 Start work on release of the assembly house data: Generate the Bill of Materials: 1. This whole process assumes that we running the design from a script written comps file that comes out of the directory: /home2/designs/boards/HTM_0/Work/Components/ 2. The first step is to hack-up this good normal human written comps file and make a special version of it. This is needed because for example: We don't want to tell the assembly house about Receiver and Transmitter MiniPODs rather we need to tell them about an 81 pin FCI connector. From the Tools directory.Run the script: make_special_comps_file_for_bom.sh The make_special_comps_file_for_bom.sh script does the following: - It makes a local copy of the full comps file that it gets from .../Hub_0/Work/Components/ - It makes the necessary edits on this local file. - Finally it passes this local file to Mentor in its directory: /home2/designs/boards/Hub_0/Hub_0_pcb/pcb Note: When you are finished generating the Mentor BOM file you need to restore the real comps file to the Mentor directory before running layout or anything like that. That is you need to run aaa_htm_0_data_path_comps.sh in the /home2/designs/boards/HTM_0/Work/Components directory. or you need to restore the mentor format comps file e.g. with reference designator silk in final position. 3. Now from the Tools directory.run the script: generate_bill_of_materials.sh This runs the Mentor FabLink program and writes out a BOM file in the Text directory named: .../Hub_0/Work/Text/bill_of_materials_current.txt This script contains documentation about what information is put into the BOM file, i.e. only a subset of what Mentor can stick into the BOM file that it generates. 4. Start the cleanup of the BOM file as written by Mentor. Run the script: clean_up_bom_file.sh This script starts the BOM clean up by: Delete some of the Mentor header text Making some obvious substitutions, e.g. Tant_V_Case for Tant_D_THD Delete the first 4 space characters from all lines. Delete the trailing space characters from all lines. Finally this script copies the now some what cleaned up BOM into the main text directory as: ../Text/bill_of_materials_cleaned_current.txt and it finishes by deleting the temporary files that it has used to get the BOM to this point. 5. Move the "cleaned" BOM file to the release directory and continue the clean up as necessary, e.g. by changing the format of how many spaces there are in and between columns as required and in the first section put a blank line between each part type. Recall that choosing to include or exclude from the BOM the various specialized value capacitors and resistors (e.g. in the DCDC Converters) is as simple as assigning them or not to use the _1sb version of the component (one solder blob version). Generate the XY Component Placement Data: 1. This whole process assumes that we running the design from a human script written comps file that comes out of the directory: /home2/designs/boards/HTM_0/Work/Components/ 2. From the Tools directory run the following script to make a special version of the components file: make_special_smd_installed_comps.sh Only the SMD components that the Assembly House will actually install are included in this special version of the comps file. Note that this special version of the comps file is NOT passed to Mentor so we do not need to worry about restoring the normal comps file to Mentor when this X,Y generation process is finished. While running this script it reports the total number of placements and the number of "component types" as used on both the Top and Bottom sides of the card. Running this script generates the following temporary files: temp_smd_top_side_comps_all_data.txt temp_smd_bot_side_comps_all_data.txt temp_smd_top_side_comps_list.txt temp_smd_bot_side_comps_list.txt temp_smd_top_side_comps_types.txt temp_smd_bot_side_comps_types.txt temp_smd_top_side_usage_counts.txt temp_smd_bot_side_usage_counts.txt Some of these temporaty files are used in the next step in generating the XY placement data. The two "usage" files provide the content for the two "component counts" files that are sent to the assembly house. 3. From the Tools directory run the following script to make the XY placement data file generate_smd_xy_placement_data.sh This script makes the files: temp_top_smd_xy_place_data.txt and temp_bot_smd_xy_place_data.txt 4. Rename and Edit the "usage" and "xy_placement" files to make the versions that will actually be released to the assembly house. The editing work mainly involves adding a header and date as the body of the file is already rationally formated. Just delete the other unused temp files from the Tools directory once this editing work is finished. Finish editing the text release files: aaa_htm_assembly_description.txt aaa_htm_bare_pcb_description.txt htm_assembly_house_bill_of_materials.txt htm_component_descriptions.txt htm_not_installed_components.txt htm_smd_component_counts_bottom.txt htm_smd_component_counts_top.txt htm_smd_xy_placement_data_bottom.txt htm_smd_xy_placement_data_top.txt htm_thd_components.txt Backup at tar tues_6 All to web directory. Close of business on Tuesday: Components 482 Nets 699 Connections 1371 Finished 1371 UnFinished 0 Guides 0 Shapes 10 Fills 10 comps_195 (spencer mentor silk), nets_120, traces_110 (with all fills) Backup at tar tues_7 ------------------------------------------------------------------------ DATE: 23-Apr-2018 Topic(s): Murge in the Durand work from weekend, work on release with rational Clk Polarity Flips Add the Not In BOM property to the front panel MPT feedthrough connector geometry. Drop everything from the ./mfg/ directory. Drop all Fills from traces - now at traces.traces_108 which is equal to traces.traces_107_save Murge in the clock_generation_comps and jtag_and_associated_comps that are now equivalent to Spencer's mentor comps with good Ref Desig Silk. So we are back to having equivalent Script Comps and Mentor Comps. Prove this by looking at the start up counts and messages from Layout. Now at: comps_193_mentor_save or comps_194_script_save nets_119, trac_108 = trac_107_save Counts: Components 482 Nets 699 Connections 1334 Finished 1224 UnFinished 79 Guides 31 Murge the edits into clock_generation_nets so that only the feed to the Si Labs ref clk input has a flip. There are no other flips in any of the diff pair clk wiring on the HTM. We need to make it appear that there is a flip in the diff pair input to the Si Labs chip because according to the schematic for the FPGA Mezz card they wired this backwards, i.e. FPGA Mezz pin J3-40 is labeled Si5328_Clk1_N but it goes to pin #1 of the Si5338 which is its non-inverting Ref Clk input. Backup at tar mon_2 Finish the trace editing to get in the new non-flipped differential clock traces. Then the current file set is: comps_193_mentor_save current Spencer with Ref Desig Silk comps_194_script_save current from Script == to above nets_120 current nets from script with correct clk polarities traces_107_save pre today's trace work wo fills traces_108 hand edits to above to fit correct clk nets traces_109 current fully routed - correct clk nets wo fills Layout to verify that counts are as above: 1334, 1224, 79, 31 with either Script comps or Spencer comps with ref desig silk. Then switch to using Spencer Comps with Ref Desig Silk. Backup at tar mon_4 Notice that the Bulk_3V3 and Bulk_2V5 function silks are backwards. Add function labels for the power input fuses. This all means edit the HTM pcb geom. Backup at tar mon_5 mon_6 ------------------------------------------------------------------------ DATE: 20-Apr-2018 Topic(s): Fix the power pin problem to the 40.08 MHz fanout that Philippe found Delete the comps from script files. We will run on Spencer's mentor comps files and then have to edit the script comps to match them for BOM and XY generation. Delete all files in .../mfg/ Drop all fills, i.e. trace_104_orig ---> trace_105. Backup at tar fri_1 Layout: disconnect and move C275 and C276, clean up ties to L251, move R362 West 0.3 mm R364 West 0.2 mm, drop the connection to C262-1, clean up the Hub Clk Mon diff pair near 258, 117. This makes comps_191, trac_106. Hand edit mentor comps_191 to add: L281, C281, C282. Edit HTM clock generation net list to move U254 power and its local bypass caps to CLK_2V5 and to add the CLK_2V5 power filter connections to: L281, C281, C282. Now at: comps_191_mentor_edited, nets_119, trac_106 Layout to move: C261, C275, C276, C281, C282, then route. This puts us at: comps_192, nets_119, trac_107 Backup at tar fri_4 Fablink to clean up the Reference Designators of the new and moved components --> comps_193 Verify comps_192 and 103 differ only in Ref Desig text location and size. Backup at tar fri_5 comps_193, nets_119, trac_107 Recall that the Script Comps must be brought up to match comps_193 before the BOM or the XY placement data is generated. Recall that this requires passing the script comps to Mentor and then restoring. Copy comps_193 to comps_193_save to prevent its loss. Copy traces_107 to traces_107_save to prevent its loss. Counts: Components 482 Nets 699 Connections 1334 Finished 1224 UnFinished 79 Guides 31 Generate Drills, Fills, Gerbers, and no-thermo Gerbers starting from comps_193, nets_119, trac_107 the processs is as described in 18-Apr-18 log book. Work in the Tools directory and do the steps to release the design: - generate_drill_table_and_drill_files.sh Now at drill table 43 with no change from before. New un-plated drill files is same size. New plated drill file is 18773 --> 18863 increase as expected - generate_all_htm_fills.sh This makes traces_108. Move traces_107 to traces_107_orig to make sure it is saved. - Look at htm in mentor layout to see the new traces_108 and to check the counts. Components 482 Nets 699 Connections 1371 Finished 1371 UnFinished 0 Guides 0 Shapes 10 Fills 10 - generate_gerber_all_16_plots_for_htm.sh No errors, no missing apertures, no painting Only a few of the artwork files have not changed size, e.g. plugs and mechanical. - remove_most_ground_thermal_relief.sh The new no-therm file sizes are slightly bigger than before as expected. - Edit the back-drill configuration files to point at traces_107_orig and then: backdrill_most__generate.sh backdrill_zone2_generate.sh no errors and no changes in output file sizes when generating either set of back-drill files. If there were any change (or possibility of a change) then I should run the script to make a new HTM pcb geometry so that I would have current mentor back-drill circles to look at. I will do this. Backup at tar fri_6 comps_193, nets_119, trac_108 - Move everything to the web. - Spencer and Philippe push me on how many -1s I have in the clock circuit to fix the FPGA Mezz card signal name problem to their Si Labs chip. It looks like I screwed this up. The FPGA Mezz card named their pins that go to the Si Labs chip backwards so the HTM should have a flip there, but HTM should not have a flip to front panel or to Logic Clock feed to the FPGA Mezz. I need to check this and add a clear crisp annotation to the HTM Clock Generation NetList file. Close of business on Friday: No Errors 193 119 108 Components 482 Nets 699 Connections 1371 Finished 1371 UnFinished 0 Guides 0 Shapes 10 Fills 10 ------------------------------------------------------------------------ DATE: 18-Apr-2018 Topic(s): Final pass through trace edits and generation of release data. Drop the trc_103 with fills, go back to trc_102, and make a final set of trace edits: move sig_2 trc away from the alignment pin hole at left side J11 fix trace width at right side of R208 pull out the no longer needed jog from the sig_9 clk monitor lines pull out the un-needed jogs from the HW Adrs lines make a more direct path for the Access Signals under J1 consider pulling the sig_10 jog out of LB_JTAG_ENB flip sig_10 Mez_1V8_Monit to the other side of R509 Post this trace edit session we are at traces_104 with counts: Components 479 Nets 698 Connections 1313 Finished 1201 UnFinished 80 Guides 32 Currently: comps_190 nets_118 traces_104 all on Moto all as expected. Work in the Tools directory and do the steps to release the design: - generate_drill_table_and_drill_files.sh Now at drill table 42 with no change from before. New drill files themselves did not change size wrt before. - generate_all_htm_fills.sh This makes traces_105 which is 1354 bytes smaller than traces_103 with fills (as expected). Move traces_104 to traces_104_orig to make sure it is saved. - Look at htm in mentor layout to see the new traces_105 and to check the counts. - generate_gerber_all_16_plots_for_htm.sh No errors, no missing apertures, no painting Many new file sizes are the same as previous version. Some smaller e.g. L8 as expected - remove_most_ground_thermal_relief.sh The new no-therm file sizes are the same as previous version as expected. - Edit the back-drill configuration files to point at traces_104_orig and then: backdrill_most__generate.sh backdrill_zone2_generate.sh no errors and no changes in output file sizes when generating either set of back-drill files. If there were any change (or possibility of a change) then I should run the script to make a new HTM pcb geometry so that I would have current mentor back-drill circles to look at. I will do this. - Move everything to the web. - Look at htm with layout again. Check counts and run DRC with the tightest possible constarints from yesterday. Components 479 Nets 698 Connections 1352 Finished 1352 UnFinished 0 Guides 0 Shapes 10 Fills 10 Currently: comps_190 nets_118 traces_105 all on Moto comps_190 is Spencer's from 17 April traces_105 is with all fills DRC has no errors. Back-Drill mentor circles match the intended back-drill pattern. Generate a new net trace length report. - Run nuk_all_logs_run_all_trace_diffs.sh and verify that nothing has disturbed the HS trace length match. - Need to look at gerbers on the web and check the two instructions files. ------------------------------------------------------------------------ DATE: 17-Apr-2018 Topic(s): Clean up for Release, Back-Drill files Philippe found a trace 0.4 mm from an unplated hole in the J11 (voltage monitor, CPLD JTAG, Life Boat) connector. This may be OK but is not good. This is a strong enough reason to touch the traces again. Philippe has prepaired a written list of things to look at. Some others will be touched at the same time, e.g. extra jogs in the HW Adrs, and monitor clk lines, and list from yesterday. I will not touch until the design rule study is finished. The setup for back-drill generation is now final and stable and all the config and script files are setup in final form. Two depths from bottom for Zone 2 and two depths from bottom for DPVs. The back-drill check circles in the Mentor PCB Geom are: DPV 0.25 Keep L8 to L1 Sheet_Dielectric_8 DPV 0.25 Keep L3 to L1 Sheet_Dielectric_9 DPV 0.25 all back-drills Sheet_Dielectric_12 Zone_2 0.46 Keep L8 to L1 PrePreg_10 Zone_2 0.46 Keep L6 to L1 PrePreg_11 Zone_2 0.46 all back-drills PrePreg_12 Design rul study was finished today. all of the details are in the file: htm_drc_run_notes.txt The clearances are more or less as expected and none of them should be any trouble to build the card. Spencer has made a final pass over the silk and he found a way to clean up the WTerm Ref Desigs under J11. I think that silk looks OK now. Spencer also check a few entries from each XY Placements file against actual locations as displayed in Layout to verify that things look OK in that file. Comps files - recall that Spencers comps files and the comps file generated by the script should currently match as far a placements go and should differ only in silk format and locations. No change in counts of versions on moto today. ------------------------------------------------------------------------ DATE: 16-Apr-2018 Topic(s): Clean up for Release, Generate Back-Drills Worked on the setup to generate the Back-Drill files for the HTM card. This is basically all working now but I still have one question to check on about the configuration files for the back-drill python program. All runs from scripts. Need to edit the build script for the HTM PCB to include the back drill checking files. Current setup is 2 back drill depths from the bottom for the Zone 2 Conn and 2 back drill depths from the bottom for the differential via pairs. That's it. Spencer is working on Ref Desg silk sna function label silk. He made new comsp and pcb geom silk files today. Philippe almost has the HTM gerbers displayed in his system. Routing to correct: bottom LED of the 8 has a wider trace from its resistor than the others do Access signal routing can be shorter if it runs under J2 in a rational location No change in counts today or change in nets, traces, or apertures. ------------------------------------------------------------------------ DATE: 14-Apr-2018 Topic(s): Cleanup: Silk, Gnd Planes, htm_pcb_to_fpga_mezz_connections.txt Spencer's reference designator silkscreen work from Friday was moved to moto and put into the mentor htm design file set. New silkscreen plots were made and copied to the release area on the web. Silk now looks about final except for some additional labels of circuit function areas. The script was run to pull out all of the wagon wheel thermal relief flashes from the Ground Plane gerber plots except for: D265 ATCA Iso_12V Module Gnd Pin D266 no longer used exposed pad thermal via D276 ATCA Power Entry Module Gnd Pin D405 wrap_3mmo, WTerms, Scope Loops Ground Plane plots were copied to the web release area. Worked on the htm_fpga_mezz_connections.txt file to add anotations and more information about Si Lab chip connections to FPGA and Phy chip connections to the FPGA. Both of these sets of connections are internal to the FPGA Mezz. Remaining work to do: - finish the silk circuit function labels - finish the design rule study - start and do the Back-Drill file generation Note that the front panel MTP feed through connector geometry is probably missing the "not in bom" property. No change in counts or versions on moto. ------------------------------------------------------------------------ DATE: 13-Apr-2018 Topic(s): Cleanup: Silk, Design Rules, Ground Plane Thermal Reliefs In the morning I copied Spencer's comps file with his edited silkscreen to moto and hand edited to add the comps that were put into the design yesterday, i.e. a scope loop via pair, and 13 ground plane rivets. The count all match up running on this comps file so I have moved moto to use it and then I replaced the full set of design files on Spencer's machine. Edited the script that removes most of the Thermal Relief flashes from the two ground plane plots. This script is now setup for the HTM Card. This scrip now removes all Ground Plane Thermal Reliefs except for: Scope Loop Vias, Gnd Pin on ATCA Power Entry Module, Gnd Pin on the ATCA Iso_12V Module. Now with all Fills in and running on Spencer's Silkscreen No Warnings - At close of business on Friday: Components 479 Nets 698 Connections 1352 Finished 1352 UnFinished 0 Guides 0 Shapes 10 Fills 10 Currently: comps_190 nets_118 traces_103 all on Moto ------------------------------------------------------------------------ DATE: 12-Apr-2018 Topic(s): Cleanup and Practice Release More added Comps Finished the HS Trace Length Match at Traces_102. Have added more Comps to the script comps process: Scope Loops WTerm 3 and 4 Ground Rivets GR 111:117 and 121:126 Must add these and delete the 3 DPVs from Spencer's Comps. Tar 3 then start practice release at: Components 479 Nets 698 Connections 1313 Finished 1201 UnFinished 80 Guides 32 Currently: comps_188 nets_118 traces_102 all on Moto Now with all Fills in - At close of business on Thursday: Components 479 Nets 698 Connections 1352 Finished 1352 UnFinished 0 Guides 0 Currently: comps_190 nets_118 traces_103 all on Moto No Warnings - still running on moto script comps ------------------------------------------------------------------------ DATE: 11-Apr-2018 Topic(s): Cleanup and Working for Release Spencer has the top side SilkScreen about finished. There is very little silk on the backside. I've tested pulling DPV 1,3,5 out of Spencer's comps file and it works OK with the rest of the design. Finished smoothing all HS trace bends and have about 3/4 of the trace length match finished. Checking trace length on both sides of the coupling caps. At close of business on Wednesday: No Warnings Components 464 Nets 698 Connections 1313 Finished 1201 UnFinished 80 Guides 32 Currently: comps_187 nets_117 traces_99 all on Moto ------------------------------------------------------------------------ DATE: 10-Apr-2018 Topic(s): Cleanup and Work for Release Fills now all work Trimming Trace Length traces 79 and 83 are the same and complete but without the modified connection to ISO_12V Shield traces 84 has the modified connection to 12V Shield and the plan is to dump this version Finally all 10 Fills are working correctly. One script makes all 10 of them and only increments the traces file once so no chance of lost traces file. The 2 day problem with the Iso_12V Shielf Fill was that the via for the connection from resistor to fill was just on the edge of the fill (half in half out) and that blocked the fill from connecting up. Now DiffLengthCompare is running on the HTM Card. I'm looking at: Combined Data Input, FEX Data Output, and MiniPOD In and Out. It was fairly quick to get DiffLength Compare running on the new design. Things are about as expected. For the FEX Data Output traces that run through DPV1, DPV3, and DPV5 I going to pull these components out and run all FEX Data Output traces that go to the TOP chicklet in J23 on the TOP pcb layer. I will back up to traces 79/83 to start this work. Working on smoothing the HS trace bends - perhaps about half through this. This picked up from traces 79. Still running on Script Comps so when I switch to Spencer's Mentor SilkScreen Comps I need to hand edit to remove DPV 1,3,5. Running on Nets with all the net High-Speed properties are in. At close of business on Tuesday: No Warnings Components 464 Nets 698 Connections 1313 Finished 1201 UnFinished 80 Guides 32 Currently: comps_187 nets_117 traces_92 all on Moto ------------------------------------------------------------------------ DATE: 9-Apr-2018 Topic(s): Design Rules and Study Need to clean up the HTM Card design rules and finish a study of how loose/tight we can run the HTM rules as that information is needed to setup the final version of Fill Generation. Currently as layed out: Default High-Speed --------------------- -------------------- pin via trace fill pin via trace fill pin 1.00 0.50 via 0.20 0.35 0.38 1.00 trace 0.12 0.20 0.185 0.12 0.26 0.21 fill 0.14 0.20 0.300 0.40 0.15 0.20 0.35 0.40 traces_75_save = traces_78_save good - no known errors 467 698 1317 1204 78 35 traces_79_save fix U201 pin 23, fix Bulk_3V3 feed to HW-Adrs, tie up R961 and run traces and vias to SHIELD_ATCA_12V_MODULE, and Ground. Spencer is working on the SilkScreen. The HS property is now in on all the required netlists. The Iso_12V Shield Fill is still not working - but the UnFin and Guides go to zero when the fills are in. Spencer's netlist with the HS property are also now in. At close of business on Monday: No Warnings Components 467 Nets 698 Connections 1319 Finished 1206 UnFinished 81 Guides 32 Currently: comps_186 nets_115 traces_81 all on Moto ------------------------------------------------------------------------ DATE: 7,8-Apr-2018 Topic(s): Connection list to the FPGA Mezzanine card, Nets Finally wrote and put on the web the list of all connections that the HTM pcb makes to the FPGA Mezzanine J1, J2, J3. The intent is that this list can be used to confirm the HTM design and that it passes the required design information to the Firmware people. Found problems with a couple of net names in the JTAG and Sunday net list files, e.g. a netname missing and underscore caracter so that it was in two pieces but still appears to have work. ------------------------------------------------------------------------ DATE: 6-Apr-2018 Topic(s): Routing and Cleanup Work Spencer has finished the LED control signal runs and has finished the FPGA Mezz No_Conns. With the final LED traces in, I then put in the final J2 blade and power pin connections (all but C80 that probably needs to move). That should finish up all traces on the card - but still need the Shelf Grounds to both Air Baffles. Worked on the Fill Generation script. For HTM I will do all Fills in just one script which will make 9 calls and increment the traces file only once. General list of things to finish up - cleanup - generate - verify: - Add Mechanical Mounting holes in the top part of the card - Add final Scope Loops - Add final Perimeter Rivets - Add big heat sink area to the LT Linear Regulator Geometry - Cleanup and add useful SilkScreen top and bottom - Design Rule study: look for problems and to study how tight can we make the Clearance Rules - Write Fill Generation script with parameters based on Design Rule Clearance study - Generate final Fills - Note the HS Diff Pair nets are all missing the (NET_TYPE, 'DIFF_PAIR_HS') property - Prepair the control files for the HS Diff Pair Trace Length study - Equalize Diff Pair Trace Lengths with serpentines - Round the corners of the HS Diff Traces - Write Gerber Generation script - Prepair final version of Aperture Table - Generate and check final version of the Gerbers - Tune and run the script to remove the Gnd Pln Thermal Reliefs - Write Drill Generation script - Prepair final version of Drill Table - Generate and check final version of the Drill Files - Prepair the control files for the Back Drill Generation - Generate and verify the Back Drills - Verify the correct generation of the Top Plugs - Generate final version of the Assembly House BOM - Generate final version of the Assembly House Not Install Comps - Generate final version of the Assembly House XY Comp Placements - Generate final version of the Assembly House Comp Descriptions - Verify that the design is OK to release: NetList check - ListCompPinNets Gerber check - on different viewer Functionally check - verify FPGA Mezz connections Technical implementation check At close of business on Friday: No Warnings Components 466 Nets 697 Connections 1310 Finished 1189 UnFinished 78 Guides 43 Currently: comps_184 nets_112 traces_73 all on Moto - Spencer finished with LED traces ------------------------------------------------------------------------ DATE: 5-Apr-2018 Topic(s): Cleanup Work In general all of the Gerber generation and Aperture Tables is now in and working well. Drill generation is working well. Started work on the Fill generation scripts. This looks easy for the HTM Card but does require final decision on the clearance rules. Noticed that the HS_DIFF_PAIR property is missing from many of the HS trace pairs in the netlist. This must be fixed. Still need to start work on: BackDrill and Diff Length Match. HTM will require running the Remove Most Ground Thermal Relief script which will need to be tuned up and have the two new Power Apertures from today added to it. Spencer is working on the last 16 LED control traces. A new geom for the LT regulator is in that has big heat sink copper areas on the top and bottom. Ground to the Air Baffles and upper half mechanical holes are in. At close of business on Thursday: No Warnings Components 466 Nets 544 Connections 1256 Finished 1087 UnFinished 78 Guides 91 Currently at traces_69 comps_184 nets_110 all Moto but Spencer is routing. ------------------------------------------------------------------------ DATE: 4,5-Apr-2018 Topic(s): Test of Gerber Plots Overall I need to add the following apertures to plot the HTM Card: Normal Apertures: i.e. Power = False, Mirror = False, Orien = 0 Y mm Shape Type or Dia X mm --------- ----- ------ ----- circle trace 4.000 circle trace 3.500 circle trace 0.450 circle flash 5.800 circle flash 2.900 circle flash 1.950 rectangle flash 2.270 0.280 rectangle flash 2.370 0.380 rectangle flash 0.280 2.270 rectangle flash 0.380 2.370 rectangle flash 0.600 1.060 rectangle flash 0.700 1.160 rectangle flash 1.400 2.100 rectangle flash 1.500 2.200 rectangle flash 1.100 0.400 Power Apertures: i.e. Power = True, Mirror = False, Orien = 0 Y mm Shape Type or Dia X mm --------- ----- ------ ----- circle flash 4.200 circle flash 2.900 Results from a first serious test run of HTM Card Gerber Generation. Note: Artwork_1 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: circle trace 3.500000 0.000000 0 false false Note: circle trace 0.450000 0.000000 0 false false Note: circle trace 4.000000 0.000000 0 false false Note: circle flash 5.800000 0.000000 0 false false Note: rectangle flash 2.270000 0.280000 0 false false Note: rectangle flash 0.280000 2.270000 0 false false Note: rectangle flash 0.600000 1.060000 0 false false Note: rectangle flash 1.400000 2.100000 0 false false Note: rectangle flash 1.100000 0.400000 0 false false Note: No missing apertures Note: Artwork_6 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: circle trace 4.000000 0.000000 0 false false Note: circle flash 5.800000 0.000000 0 false false Note: No missing apertures Note: Artwork_3 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: circle trace 4.000000 0.000000 0 false false Note: circle trace 3.500000 0.000000 0 false false Note: No missing apertures Note: Artwork_7 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: circle flash 2.900000 0.000000 0 false false Error: Missing Apertures Error: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Error: circle flash 4.200000 0.000000 0 false true Error: circle flash 2.900000 0.000000 0 false true Warning: One or more apertures are missing, do not send this artwork file to photoplotter Note: Artwork_8 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: circle flash 2.900000 0.000000 0 false false Error: Missing Apertures Error: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Error: circle flash 4.200000 0.000000 0 false true Error: circle flash 2.900000 0.000000 0 false true Warning: One or more apertures are missing, do not send this artwork file to photoplotter Note: Artwork_12 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: rectangle flash 2.370000 0.380000 0 false false Note: rectangle flash 0.380000 2.370000 0 false false Note: circle flash 1.950000 0.000000 0 false false Note: rectangle flash 0.700000 1.160000 0 false false Note: rectangle flash 1.500000 2.200000 0 false false Note: No missing apertures Note: Artwork_14 Note: The objects with the following sizes will be painted Note: Shape Type Height(Y)/Diameter Width(X) Orientation Mirror Power Note: rectangle flash 2.270000 0.280000 0 false false Note: rectangle flash 0.280000 2.270000 0 false false Note: rectangle flash 0.600000 1.060000 0 false false Note: rectangle flash 1.100000 0.400000 0 false false Note: No missing apertures ------------------------------------------------------------------------ DATE: 4-Apr-2018 Topic(s): Routing and Script Work I think that all of the routing is finished for now except for one Voltage Monitor point and the 16 control signals to the LED Drivers that I hope that Spencer can finish so that that whole section is his. The Air Baffles are now tied to the Shelf Ground as an electrical component with pins. Finished the 12 script files that control the generation of the 16 Gerber files and I'm working on a first pass test of them. At close of business on Wednesday: No Warnings Passed to Spencer Components 466 Nets 544 Connections 1256 Finished 1087 UnFinished 78 Guides 91 Currently at traces_69 comps_184 nets_109 all Moto but Spencer may still edit today. ------------------------------------------------------------------------ DATE: 3-Apr-2018 Topic(s): Routing Work Most of the routing work was in all of the Life Boat Signals and their jumpers and WTerms. All of front panel Access Connector is now tied back into the layout. J3 blade pins are connected. At close of business on Tuesday: No Warnings Components 462 Nets 540 Connections 1239 Finished 1068 UnFinished 78 Guides 93 Currently at traces_66 comps_180 nets_106 all Moto. ------------------------------------------------------------------------ DATE: 2-Apr-2018 Topic(s): Fix Samtec-160 Geom, Routing Work Fixed the Y dimension error in the Samtec 160 pin connector geometry that Spencer found late Friday afternoon. While working on the Samtec Geom I also put in the Ground Plane Relief under the pins for the High-Speed MGT signals. All of the required corrrections for the wider Y dimension spacing were finished today. Spencer has signed off on the Samtec Geom with help from design data dimensions that Brian got him from the Base Board. At close of business on Monday: Note the lost trace or two. Components 437 Nets 438 Connections 1154 Finished 964 UnFinished 63 Guides 127 Currently at traces_62 and comps_160 both from Moto. ------------------------------------------------------------------------ DATE: 30-Mar-2018 Topic(s): Routing Work, Geometry Check, FPGA Mezz No_Connects I'm working on routing and routing cleanup. Spencer is working on generating the FPGA Mezz No_Conn single point nets and he started checking the Samtec 160 pin Geometry. I'm rather certain that he has already found at least one problem, i.e. the spacing from the long centerline to the centers of the signal pads is probably wrong; 2.30 mm in the design vs the part is probably 2.864 mm. Need to verify the full Geom before starting work to fix the problem. At close of business on Friday: Components 437 Nets 438 Connections 1155 Finished 965 UnFinished 65 Guides 125 Currently at traces_58 and comps_158 both from Moto. ------------------------------------------------------------------------ DATE: 29-Mar-2018 Topic(s): Routing Work The Distributed Bypass Capacitors are now basically all in their final locations and routed. The Control Signals to the two MiniPODs now have their Pull-Up located and most of that routing is finished. I must verify the Samtec Geometry or this all culd be a big waste of time. At close of business on Thursday with Spencer still routing: Components 437 Nets 438 Connections 1125 Finished 909 UnFinished 68 Guides 148 Currently at traces_54 on Moto with one more to come from Spencer. ------------------------------------------------------------------------ DATE: 28-Mar-2018 Topic(s): Routing Work Good drafts of all Fill Shapes are now in. The ATCA Hardware Address is routed and a lot of other areas finished up. Big issue is that I need final sign off on the Samtec 160 pin connectors and the FPGA Mezz. I risk wasting time now because I'm making "final" routes into these 3 connectors and they could be wrong or in the wrong place. At close of business on Wednesday: Components 436 Nets 422 Connections 1104 Finished 868 UnFinished 58 Guides 178 Currently at traces_51 that came from Moto. ------------------------------------------------------------------------ DATE: 27-Mar-2018 Topic(s): Routing Work Finished the Bulk Supplies, MiniPOD Filters, and a lot of clean up. At close of business on Tuesday: Components 434 Nets 422 Connections 1076 Finished 788 UnFinished 47 Guides 241 Currently at traces_45 that came from Moto. ------------------------------------------------------------------------ DATE: 26-Mar-2018 Topic(s): Review the use of ALL Special Layers in the Hub design, Routing Work Spencer is working routing the LED signals from the driver down to the RJ45 connectors. I've finished the clock system for now and have started work on the Power Fill Shapes. At close of business on Monday: Components 434 Nets 422 Connections 1011 Finished 596 UnFinished 38 Guides 377 Currently at traces_40 that came from Spencer. Review of some of the "Special Layers" used on the Hub design: Ground Plane Cuts in Top layers PrePreg_1 Ground Plane Cuts in Bot layres PrePreg_2 Ground Plane Cuts in All layers PrePreg_3 Vias Plugged from the Top PrePreg_5 Vias Plugged from the Bottom PrePreg_6 Backside metal on Bot side e.g. QFN center pad Sheet_Dielectric_1 Backside metal on Top side e.g. QFN center pad Sheet_Dielectric_2 Back-Drills non-Zone_2 from Top Shallowest Sheet_Dielectric_4 Back-Drills non-Zone_2 from Top NT Shallowest Sheet_Dielectric_5 Back-Drills non-Zone_2 from Top NT Deepest Sheet_Dielectric_6 Back-Drills non-Zone_2 from Top Deepest Sheet_Dielectric_7 Back-Drills non-Zone_2 from Bot Shallowest Sheet_Dielectric_8 Back-Drills non-Zone_2 from Bot NT Shallowest Sheet_Dielectric_9 Back-Drills non-Zone_2 from Bot NT Deepest Sheet_Dielectric_10 Back-Drills non-Zone_2 from Bot Deepest Sheet_Dielectric_11 Mark All non-Zone_2 Back-Drills Sheet_Dielectric_12 Back-Drills Only-Zone_2 from Bot Shallowest PrePreg_9 Back-Drills Only-Zone_2 from Bot Mid Depth PrePreg_10 Back-Drills Only-Zone_2 from Bot Deepest PrePreg_11 Mark All Only-Zone_2 Back-Drills PrePreg_12 Special Ground Plane Glue_Mask_1 and Component_Metal_1 Relief for only diff_pair_thru_3p_top_mid_relief diff_pair_thru_3p_mid_bot_relief. Drawing Only of the front panel and such Conformal_Mask_1 Drawing Only of the various LED Areas Conformal_Mask_2 Fill Shape Design Entry Layers Dielectric_ 1:4 Not Used (but often used on other designs) DAM_ 1:3 ------------------------------------------------------------------------ DATE: 24,25-Mar-2018 Topic(s): Routing and Design Work Besides the various FPGA Mezz CPLD and control signals, the following signals in the HTM design still do not have a home, aka connection to the FPGA Mezz: - PLL Lock signal from R268 to a FPGA 3V3 Sel I/O - Access Signals #1 & #2 from FPGA 3V3 Sel I/O to U351 - Hub #2 Clock Monitor signal from R256 to a FPGA 3V3 Sel I/O - 40.08 MHz Logic Clock from C266/C267 to FPGA 3V3 Sel I/O MR Glb Clk - Space Clock from C271/C272 to FPGA 3V3 Sel I/O MR Glb Clk Files to Restore to Moto: htm_log_book_pre_release.txt clock_generation_comps clock_generation_nets jtag_and_associated_comps jtag_and_j12_associated_nets Check: J3-34 J3-36 in table of Banks 10:13 At close of business on Sunday: Components 434 Nets 422 Connections 993 Finished 502 UnFinished 29 Guides 462 ------------------------------------------------------------------------ DATE: 23-Mar-2018 Topic(s): Routing Work Spencer is working down the West edge, aka front edge, of the card and I have recently finished the FPGA Enet and Power Supplies. At close of business: Components 432 Nets 401 Connections 974 Finished 470 UnFinished 24 Guides 480 ------------------------------------------------------------------------ DATE: 21-Mar-2018 Topic(s): Routing Work I'm routing the Enet to the FPGA Mezz and Spencer is routing the upper LED section. At close of business: Components 400 Nets 401 Connections 905 Finished 302 UnFinished 27 Guides 576 ------------------------------------------------------------------------ DATE: 16-Mar-2018 Topic(s): Routing Work The high-speed routing is in and most of the Enet is in. In the high-speed area still need to match lengths and round the corners. Working on ground to J1, J2, J3 for the FPGA Mezz card. Components 378 Nets 401 Connections 921 Finished 229 UnFinished 6 Guides 686 Need to add the front panel MPT feed through connectors. There is 48 mm between the horizontal air block and the upper front panel mounting bracket. ------------------------------------------------------------------------ DATE: 9-Mar-2018 Topic(s): Setup for smoothed trace bends: Setup Routing --> All Angle Routing ON Setup Routing --> Routing Arc Segments --> Set Routing Arc Segments = 24 (typ) Routing --> Change Trace --> Make Arc Picking something like 0.16 for the very tight bends fanning out to a via pair or coupling caps. Pick something like 0.3 to 0.5 for normal bends. May want different inner and outer radii to spread the traces slightly within the bend. ------------------------------------------------------------------------ DATE: 8-Mar-2018 Topic(s): Release the technical data for HTM Card bid, Final decisions about HTM Card PCB design Wednesday 7-Mar-2018 moved the 15 technical documents for the HTM Card bid to the web site release 1 area. Final Decisions about HTM Card PCB Design: Physical Controlled Layers Layer Type Function Impedance -------- --------------------- ------------ 1 Signal Traces 100 Ohm Diff 2 Ground Plane Upper Type 3 Signal Traces 100 Ohm Diff 4 Ground Plane Upper Type 5 Power Fills 6 Power Fills 7 Ground Plane Lower Type 8 Signal Traces 100 Ohm Diff 9 Ground Plane Lower Type 10 Signal Traces 100 Ohm Diff The HTM Card pcb will use 6 types of back-drills: bk_drill_0.25_from_Top_keep_L3_to_L10 bk_drill_0.25_from_Top_keep_L8_to_L10 bk_drill_0.25_from_Bottom_keep_L3_to_L1 bk_drill_0.25_from_Bottom_keep_L8_to_L1 bk_drill_0.46_from_Bottom_keep_L6_to_L1 bk_drill_0.46_from_Bottom_keep_L8_to_L1 ------------------------------------------------------------------------ DATE: 6-Mar-2018 Topic(s): Scripts for Drill Files and for the Gerber Plots Get the script running to generate the HTM Drill Files. generate_drill_table_and_drill_files.sh Get the script running to generate the HTM RFQ Gerber Files generate_rfq_gerber_plots_1_2_3.sh~ Work on the setup of the HTM aperture table start with the Hub aperture table 29 aperture_table.apertt_29 which is the same as aperture_table.apertt_htm_minimum_wagon_wheel Edit this by had to add the apertures for the Samtec APS 160 pin connector and the Wurth Common Mode Choke. This is 7 aperures in total. Note that HTM is staying with rev 29 of the aperutre table for now. ------------------------------------------------------------------------ DATE: 5-Mar-2018 Topic(s): Scripts for SMD Component XY Placement Get the HTM scripts working to generate the SMD component XY placement data. Generate the SMD XY Place Data by: run make_special_smd_installed_comps.sh run generate_smd_xy_placement_data.sh edit the top and bottom XY files to add the headers collect the data on placement count and type count per side ------------------------------------------------------------------------ DATE: 4-Mar-2018 Topic(s): Setup scripts for automatic BOM generation for the HTM card, Instructions for Generating the HTM Bill of Materials file Edit and setup the 3 scripts that are used to generate the BOM for the HTM card. The scripts to generate the HTM BOM files are in the directory: /home2/designs/boards/HTM_0/Work/Tools The 5 steps to run are the following: make_special_comps_file_for_bom.sh generate_bill_of_materials.sh clean_up_bom_file.sh restore the normal comps file, i.e. run data_path script in comps directory edit as necessary the resulting BOM file, recall the headers for the BOM in the Text directory The hand edits to the "clean current" bom file that results for the above scripts include: Add the correct headers for the bill_of_materials_headers.txt file that's in the HTM .../Work/Text/ director. In the by part number section remove the following columns: pull out 1 column before the Item Number pull out 4 columns between Item Number & HTM Part No. pull out 1 column between Geom & Count ------------------------------------------------------------------------ DATE: 3-Feb-2018 Topic(s): Work on adding the rest of the "known" components, Organize the HTM Reference Designators Reference Designators: 51 : 99 Distributed ByPass Caps 101 : 149 Power Supplies 17x Slot Hardware Address 201 : 249 LEDs 251 : 269 271 : 299 Xtal Oscillators 301 : 349 Ethernet 351 : 369 JTAG and J12 Access Conn Associated 371 ------------------------------------------------------------------------ DATE: 2-Feb-2018 Topic(s): Concerns about our level of understanding the FPGA Mezz, Philippe says he will do the web HTM to project level web change, Spencer work, 5 PM Layout printout to Wade I have a number of concerns about our level of understanding how to used the FPGA Mezz card. A problem with any of these could be fatal. Philippe will make the change to the top level web page so that HTM is at the full project level along with CMX and Hub. I will then move the files and save everything that is currently there. Spencer is working on FEX Data MGT Output lines from the HTM on both sides of the DC blocking capacitors and using Layout to look for errors and other problems. ------------------------------------------------------------------------ DATE: 1-Feb-2018 Topic(s): Get the HTM layout and build project, work with Spencer Thursday Feb 1st get the HTM layout and build project. Waiting for written confirmation. Spencer works on grounds on: J23, J1, J2, J3