# # FEX Data Coupling Capacitors and DVP Comps # # HTM Module Key In Components File # -------------------------------------- # # # Original Rev. 2-Feb-2018 # Most Recent Rev. 10-Apr-2018 # # # This file holds all of the DC Blocking Caps and # the Differential Via Pairs for the FEX Data output # signals from the FPGA to the J23 Backplane Connector. # # # Recall that each FEX Data Output to each Hub has 6 MGT Links. # # The HTM Card has a FEX Data Output to Hub #1 and Hub #2 # # thus 12 MGT Links in total # thus 24 DC Blocking Capacitors. # # # Board_Location # Ref Part_Number Symbol Geometry X Y Properties #----- ----------- ------ ------------------ -------------- ---------- # C1 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 114.00 1 180 C2 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 113.00 1 180 C3 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 111.00 1 180 C4 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 110.00 1 180 C5 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 108.00 1 180 C6 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 107.00 1 180 C7 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 105.00 1 180 C8 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 104.00 1 180 C9 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 102.00 1 180 C10 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 101.00 1 180 C11 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 99.00 1 180 C12 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 98.00 1 180 C13 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 96.00 1 180 C14 Cap_100_nFd_0201 SY_JUNK cap_0201_top 225.00 95.00 1 180 C15 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 93.00 1 180 C16 Cap_100_nFd_0201 SY_JUNK cap_0201_top 231.00 92.00 1 180 C17 Cap_100_nFd_0201 SY_JUNK cap_0201_top 220.00 84.00 1 180 C18 Cap_100_nFd_0201 SY_JUNK cap_0201_top 220.00 83.00 1 180 C19 Cap_100_nFd_0201 SY_JUNK cap_0201_top 226.00 81.00 1 180 C20 Cap_100_nFd_0201 SY_JUNK cap_0201_top 226.00 80.00 1 180 C21 Cap_100_nFd_0201 SY_JUNK cap_0201_top 220.00 78.00 1 180 C22 Cap_100_nFd_0201 SY_JUNK cap_0201_top 220.00 77.00 1 180 C23 Cap_100_nFd_0201 SY_JUNK cap_0201_top 226.00 75.00 1 180 C24 Cap_100_nFd_0201 SY_JUNK cap_0201_top 226.00 74.00 1 180 # # Differential Pair Vias to Escape Signals from the FPGA Perimeter # ------------------------------------------------------------------ # ##DPV1 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 237.00 113.50 1 90 ##DPV3 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 258.00 110.50 1 90 ##DPV5 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 237.00 107.50 1 90 ##DPV7 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 241.00 104.50 1 90 DPV9 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 237.00 101.50 1 90 DPV11 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 242.00 98.50 1 90 DPV13 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 237.00 95.50 1 90 DPV15 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 242.00 92.50 1 90 DPV17 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 232.00 83.50 1 90 DPV19 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 236.00 80.50 1 90 DPV21 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 232.00 77.50 1 90 DPV23 NOT_A_PART SY_JUNK DIFF_PAIR_THRU 236.00 74.50 1 90 ###DPV702 NOT_A_PART SY_JUNK DIFF_PAIR_THRU_3P 185.20 93.10 1 135 ###DPV101 NOT_A_PART SY_JUNK DIFF_PAIR_THRU_3P_TOP_MID_RELIEF 102.00 115.50 1 90 ###DPV137 NOT_A_PART SY_JUNK DIFF_PAIR_THRU_3P_1MM1 33.40 169.80 1 270 ###DPV141 NOT_A_PART SY_JUNK DIFF_PAIR_THRU_1G 33.40 158.60 1 0