# # FEX Readout to HUB Net List File # # FPGA Mezzanine J3/J1 MGT Transmitters, Readout Streams, # and Capacitors Links # ----------------------------------------------------- # # # Initial Rev. 1-Feb-2018 # Current Rev. 10-Apr-2018 # # # This file holds all of the MGT transmitter, readout stream, # and capacitor connections for the FPGA Mezzanine connector # J3, and four of these connections for the FPGA Mezzanine connector # J1. # # NET 'MGT_TX_0_to_Cap_DIR' J3-31 C1-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_0_to_Cap_CMP' J3-29 C2-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_2_DIR' J23-A1 C1-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_2_CMP' J23-B1 C2-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_1_to_Cap_DIR' J3-27 C3-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_1_to_Cap_CMP' J3-25 C4-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_2_DIR' J23-C1 C3-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_2_CMP' J23-D1 C4-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_2_to_Cap_DIR' J3-23 C5-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_2_to_Cap_CMP' J3-21 C6-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_2_DIR' J23-E1 C5-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_2_CMP' J23-F1 C6-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_3_to_Cap_DIR' J3-19 C7-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_3_to_Cap_CMP' J3-17 C8-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_2_DIR' J23-G1 C7-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_2_CMP' J23-H1 C8-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_4_to_Cap_DIR' J3-15 C9-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_4_to_Cap_CMP' J3-13 C10-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_2_DIR' J23-A2 C9-1 DPV9-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_2_CMP' J23-B2 C10-1 DPV9-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_5_to_Cap_DIR' J3-11 C11-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_5_to_Cap_CMP' J3-9 C12-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_2_DIR' J23-E2 C11-1 DPV11-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_2_CMP' J23-F2 C12-1 DPV11-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_6_to_Cap_DIR' J3-7 C13-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_6_to_Cap_CMP' J3-5 C14-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_1_DIR' J23-A3 C13-1 DPV13-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_1_CMP' J23-B3 C14-1 DPV13-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_7_to_Cap_DIR' J3-3 C15-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_7_to_Cap_CMP' J3-1 C16-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_1_DIR' J23-C3 C15-1 DPV15-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_1_CMP' J23-D3 C16-1 DPV15-2 (NET_TYPE, 'DIFF_PAIR_HS') # # These last 4 FEX Readout Data connections all contain # a Polarity Flip. The flips have been implemented by # swaping the DIR/CMP pins on the J23 connector. # # Note that on the J23 connector # # Pins: E3, G3, A4, E4 are realy the DIR signal # Pins: F3, H3, B4, F4 are realy the CMP signal # NET 'MGT_TX_8_to_Cap_DIR' J1-2 C17-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_8_to_Cap_CMP' J1-4 C18-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_1_DIR' J23-F3 C17-1 DPV17-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_1_CMP' J23-E3 C18-1 DPV17-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_9_to_Cap_DIR' J1-6 C19-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_9_to_Cap_CMP' J1-8 C20-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_1_DIR' J23-H3 C19-1 DPV19-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_1_CMP' J23-G3 C20-1 DPV19-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_10_to_Cap_DIR' J1-10 C21-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_10_to_Cap_CMP' J1-12 C22-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_1_DIR' J23-B4 C21-1 DPV21-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_1_CMP' J23-A4 C22-1 DPV21-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_11_to_Cap_DIR' J1-14 C23-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_11_to_Cap_CMP' J1-16 C24-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_1_DIR' J23-F4 C23-1 DPV23-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_1_CMP' J23-E4 C24-1 DPV23-2 (NET_TYPE, 'DIFF_PAIR_HS') # # Grounds on the Differential Via Pairs # Ground Return Vias # NET 'GROUND' DPV9-1 DPV9-4 DPV11-1 DPV11-4 DPV13-1 DPV13-4 NET 'GROUND' DPV15-1 DPV15-4 NET 'GROUND' DPV17-1 DPV17-4 DPV19-1 DPV19-4 DPV21-1 DPV21-4 NET 'GROUND' DPV23-1 DPV23-4 # # This is the Key In Net List file for the # # HTM Module Power Entry Nets # ------------------------------------------------ # # # Original Rev. 2-Feb-2018 # Most Recent Rev. 23-Mar-2018 # # # ATCA Power Entry Nets: # # # Shelf Ground # NET 'SHELF_GND' P10-25 # # LOGIC Ground # NET 'GROUND' P10-26 # # -48V Entry A & B Buses # NET 'A_BUS_N48V_BP' P10-33 F4-2 NET 'Card_BUS_N48V' F4-1 L1-1 NET 'A_BUS_EARLY_48_BP' P10-30 R951-1 NET 'A_BUS_N48V_BP' R951-2 NET 'B_BUS_N48V_BP' P10-34 F3-2 NET 'Card_BUS_N48V' F3-1 NET 'B_BUS_EARLY_48_BP' P10-31 R952-1 NET 'B_BUS_N48V_BP' R952-2 # # Power Returns A & B Buses # NET 'A_BUS_48V_RETURN_BP' P10-28 F2-2 NET 'Card_48V_BUS_RETURN' F2-1 L1-4 NET 'B_BUS_48V_RETURN_BP' P10-29 F1-2 NET 'Card_48V_BUS_RETURN' F1-1 # # ATCA "Entered" 48V Power to the 12V Converter # NET 'ENTERED_N48V' L1-2 NET 'ENTERED_48V_RTN' L1-3 NET 'ENTERED_N48V' C954-2 C955-2 C952-2 NET 'ENTERED_48V_RTN' C954-1 C955-1 C951-2 NET 'ENTERED_N48V' Power_12V-3 NET 'ENTERED_48V_RTN' Power_12V-1 NET 'SHELF_GND' C951-1 C952-1 # # Pay Load Enable Signal to the Isolated +12V Converter # NET 'ENABLE_ISO_12V_B' Power_12V-2 WTERM12-1 NET 'ENTERED_N48V' WTERM11-1 # # Isolated +12V Power from the Converter # NET 'Iso_12V' Power_12V-8 NET 'GROUND' Power_12V-4 # # Remote Sense Feedback Connections: # # The Remote Sense for both the Positive and Negative sides # of of the Iso_12V output must be isolated from the Fills # and Ground Planes that are directly under these pins. # # I provide this isolation by giving the Remote Sense pins # a unique net name and then connecting these unique remote # sense nets to the Iso_12V and Ground nets by using an # "aka" component, i.e. straight through at the same width # as the trace on a Breakout layer. # # In this section also give the "Trim" pin on the Iso_12V # supply a net name. # NET 'REMOTE_SENSE_GND_ISO_12V' Power_12V-5 AKA1-2 NET 'GROUND' AKA1-1 NET 'No_Conn_Trim_12V' Power_12V-6 NET 'REMOTE_SENSE_POS_ISO_12V' Power_12V-7 AKA2-2 NET 'Iso_12V' AKA2-1 # # Filter the Isolated +12V Power from the Converter # NET 'Iso_12V' C957-2 C958-2 C959-2 C960-2 NET 'Iso_12V' C961-1 C962-1 C963-1 C964-1 NET 'GROUND' C957-1 C958-1 C959-1 C960-1 NET 'GROUND' C961-2 C962-2 C963-2 C964-2 # # No Connection Pins on the P10 Zone 1 Connector # NET 'No_Conn_P10_Pin_13' P10-13 NET 'No_Conn_P10_Pin_14' P10-14 NET 'No_Conn_P10_Pin_15' P10-15 NET 'No_Conn_P10_Pin_16' P10-16 NET 'No_Conn_P10_Pin_27' P10-27 NET 'No_Conn_P10_Pin_32' P10-32 # # J13 Front Panel RJ-45 Backplane J23 Enet Nets # ---------------------------------------------------- # # # Original Rev. 4-Feb-2018 # Current Rev. 4-Feb-2018 # # # This Net List File contain the connections from the # FPGA Mezzanine to the front panel RJ-45 connector J14. # # J13 Lower or Left Backplane J23 Hub #1 BI Enet # Upper or Right Backplane J23 Hub #2 BI Enet # # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Pri Sec ADFplus # ATCA Alt Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # # #------------------------------------------------------------ # # # Front Panel J13 Right-Upper Hub #2 Base Interface Enet NET 'J13_U_A_0_DIR' J23-A6 J13-U1 NET 'J13_U_A_0_CMP' J23-B6 J13-U2 NET 'J13_U_B_1_DIR' J23-C6 J13-U3 NET 'J13_U_B_1_CMP' J23-D6 J13-U6 NET 'J13_U_C_2_DIR' J23-E6 J13-U4 NET 'J13_U_C_2_CMP' J23-F6 J13-U5 NET 'J13_U_D_3_DIR' J23-G6 J13-U7 NET 'J13_U_D_3_CMP' J23-H6 J13-U8 # #------------------------------------------------------------ # # # Front Panel J13 Left-Lower Hub #1 Base Interface Enet NET 'J13_L_A_0_DIR' J23-A5 J13-L1 NET 'J13_L_A_0_CMP' J23-B5 J13-L2 NET 'J13_L_B_1_DIR' J23-C5 J13-L3 NET 'J13_L_B_1_CMP' J23-D5 J13-L6 NET 'J13_L_C_2_DIR' J23-E5 J13-L4 NET 'J13_L_C_2_CMP' J23-F5 J13-L5 NET 'J13_L_D_3_DIR' J23-G5 J13-L7 NET 'J13_L_D_3_CMP' J23-H5 J13-L8 # #------------------------------------------------------------ # # # FPGA Ethernet TRANS1 J14 Front Panel RJ-45 Nets # ----------------------------------------------------- # # # Original Rev. 4-Feb-2018 # Current Rev. 5-Feb-2018 # # # This Net List File contain the connections from the # FPGA Mezzanine to the front panel RJ-45 connector J14. # # J14 Lower or Left FPGA Mezzanine PHY 2 # Upper or Right FPGA Mezzanine PHY 1 # # # TRANS1 Left J14 Lower FPGA Mezzanine PHY 2 # Right J14 Upper FPGA Mezzanine PHY 1 # # # FPGA Mezzanine PHY 1 is Bank 501 of the ARM Cortex # FPGA Mezzanine PHY 2 is Bank 9 of the FPGA Fabric # # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Pri Sec ADFplus # ATCA Alt Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # To Facilitate routing one may: # # - Swap transformers within a given side of a module. # For example R1, R3, R7, R9 could be # swapped with R4, R6, R10, R12. # # - It is probably best not to wire things up so that # for a given ethernet link some of its transformers # are in the R side of the module and some of its # transformers are in the L side of the module. # # - Swap the polarity of a given transformer. For # example one may swap R1 with R3 while also # swapping R7 with R9. # # # To facilitate understanding how the magnetics for a # given Ethernet link are wired up I'm putting the nets # for the Primary and Seconday sides of a given link # next to each other in this file. # # Note that the RC components attached to the magnetics # have net names that are independed of the Etherent link # that they service. These Center Tap (CT) nets are # listed at the end of this file. These magnetics RC # nets do not have to be disturbed if the Primary and # Seconday nets are swapped for routing. # # # #------------------------------------------------------------ # # # TRANS1 Right J14 Upper/Right FPGA Mezzanine PHY 1 # # # Primary Nets Trans 1 R NET 'PHY_1_TRD0_6_DIR' J2-23 TRANS1-R1 NET 'PHY_1_TRD0_6_CMP' J2-21 TRANS1-R3 NET 'PHY_1_TRD1_6_DIR' J2-19 TRANS1-R4 NET 'PHY_1_TRD1_6_CMP' J2-17 TRANS1-R6 NET 'PHY_1_TRD2_6_DIR' J2-15 TRANS1-R24 NET 'PHY_1_TRD2_6_CMP' J2-13 TRANS1-R22 NET 'PHY_1_TRD3_6_DIR' J2-11 TRANS1-R21 NET 'PHY_1_TRD3_6_CMP' J2-9 TRANS1-R19 # # Secondary Nets Trans 1 R Front Panel J14 Right-Upper NET 'J14_U_A_0_DIR' TRANS1-R7 J14-U1 NET 'J14_U_A_0_CMP' TRANS1-R9 J14-U2 NET 'J14_U_B_1_DIR' TRANS1-R10 J14-U3 NET 'J14_U_B_1_CMP' TRANS1-R12 J14-U6 NET 'J14_U_C_2_DIR' TRANS1-R18 J14-U4 NET 'J14_U_C_2_CMP' TRANS1-R16 J14-U5 NET 'J14_U_D_3_DIR' TRANS1-R15 J14-U7 NET 'J14_U_D_3_CMP' TRANS1-R13 J14-U8 # #------------------------------------------------------------ # # # TRANS1 Left J14 Lower/Left FPGA Mezzanine PHY 2 # # # Primary Nets Trans 1 L NET 'PHY_2_TRD0_6_DIR' J2-39 TRANS1-L1 NET 'PHY_2_TRD0_6_CMP' J2-37 TRANS1-L3 NET 'PHY_2_TRD1_6_DIR' J2-35 TRANS1-L4 NET 'PHY_2_TRD1_6_CMP' J2-33 TRANS1-L6 NET 'PHY_2_TRD2_6_DIR' J2-31 TRANS1-L24 NET 'PHY_2_TRD2_6_CMP' J2-29 TRANS1-L22 NET 'PHY_2_TRD3_6_DIR' J2-27 TRANS1-L21 NET 'PHY_2_TRD3_6_CMP' J2-25 TRANS1-L19 # # Secondary Nets Trans 1 L Front Panel J14 Left-Lower NET 'J14_L_A_0_DIR' TRANS1-L7 J14-L1 NET 'J14_L_A_0_CMP' TRANS1-L9 J14-L2 NET 'J14_L_B_1_DIR' TRANS1-L10 J14-L3 NET 'J14_L_B_1_CMP' TRANS1-L12 J14-L6 NET 'J14_L_C_2_DIR' TRANS1-L18 J14-L4 NET 'J14_L_C_2_CMP' TRANS1-L16 J14-L5 NET 'J14_L_D_3_DIR' TRANS1-L15 J14-L7 NET 'J14_L_D_3_CMP' TRANS1-L13 J14-L8 # #------------------------------------------------------------ # # # Primary Center Tap Nets Trans 1 R and L # NET 'TRANS1_R_A_0_PRI_CT' TRANS1-R2 C301-2 NET 'TRANS1_R_B_1_PRI_CT' TRANS1-R5 C304-2 NET 'TRANS1_R_C_2_PRI_CT' TRANS1-R23 C302-2 NET 'TRANS1_R_D_3_PRI_CT' TRANS1-R20 C303-2 NET 'GROUND' C301-1 C302-1 C303-1 C304-1 NET 'TRANS1_L_A_0_PRI_CT' TRANS1-L2 C307-2 NET 'TRANS1_L_B_1_PRI_CT' TRANS1-L5 C308-2 NET 'TRANS1_L_C_2_PRI_CT' TRANS1-L23 C306-2 NET 'TRANS1_L_D_3_PRI_CT' TRANS1-L20 C309-2 NET 'GROUND' C306-1 C307-1 C308-1 C309-1 # # Secondary Center Tap Nets Trans 1 R and L # NET 'TRANS1_R_A_0_SEC_CT' TRANS1-R8 R302-1 NET 'TRANS1_R_B_1_SEC_CT' TRANS1-R11 R304-1 NET 'TRANS1_R_C_2_SEC_CT' TRANS1-R17 R301-1 NET 'TRANS1_R_D_3_SEC_CT' TRANS1-R14 R303-1 NET 'TRANS1_L_SEC_CT_TIE' R301-2 R302-2 R303-2 R304-2 NET 'TRANS1_L_SEC_CT_TIE' C305-1 NET 'GROUND' C305-2 NET 'TRANS1_L_A_0_SEC_CT' TRANS1-L8 R307-1 NET 'TRANS1_L_B_1_SEC_CT' TRANS1-L11 R308-1 NET 'TRANS1_L_C_2_SEC_CT' TRANS1-L17 R306-1 NET 'TRANS1_L_D_3_SEC_CT' TRANS1-L14 R309-1 NET 'TRANS1_R_SEC_CT_TIE' R306-2 R307-2 R308-2 R309-2 NET 'TRANS1_R_SEC_CT_TIE' C310-1 NET 'GROUND' C310-2 # # HTM Card Net List File # # JTAG and all Associated J12 Nets # ---------------------------------- # # # Initial Rev. 4-Feb-2018 # Current Rev. 7-Apr-2018 # # # This file holds all of the nets associated with the # JTAG circuit and the Front Panel Access Signals # on the HTM card, that is all signals associated with # the J12 Front Panel "Access Connector". # # # # Recall the pinout of the Front Panel J12 connector on HTM: # # Pin Function # --- --------------- # # 1 Ground # 2 3V3 JTAG Power # 3 Ground # 4 TMS Input # 5 Ground # 6 TCK Input # 7 Ground # 8 TDO Output # 9 Ground # 10 TDI Input # # 11 No Connect on HTM (I2C SCL on Hub) # 12 No Connect on HTM (I2C SDA on Hub) # # 13 Ground # 14 Ground # 15 Access Signal #1 Output from HTM # 16 Access Signal #2 Output from HTM # # # Connect the 3V3 JTAG Reference power and Ground # to the front panel J12 connector JTAG pins. # NET 'BULK_3V3' F5-2 NET 'FUSED_JTAG_POWER' F5-1 J12-2 NET 'GROUND' J12-1 J12-3 J12-5 J12-7 J12-9 # # JTAG connections to/from J12 and the "Level Translator" # Buffer chip. # # Note that we are using the "B" side to "A" side direction. # # "B" data input to "A" data output. # # Thus both the Direction pin and the OE_B pin are tied Low. # # The input "B" side has 3V3 power. # The output "A" side has 3V3 power. # # R351, R352, R354 are the pull-up resistors to hold # the TMS, TCK, and TDI JTAG signals in a default state # when JTAG is not being used. # # R357, R358, R359 are the series terminators at the # buffer (driving) end of the TMS, TCK, and TDI JTAG # signals that then run to the FPGA Mezz. # # R360, R353 are the series terminators at the input # and output of the buffer for the TDO JTAG signal. # # # TMS, TCK, and TDI from J12 into Buffer: # NET 'TMS_FROM_J12' J12-4 R351-1 U351-14 NET 'TCK_FROM_J12' J12-6 R352-1 U351-15 NET 'TDI_FROM_J12' J12-10 R354-1 U351-16 NET 'BULK_3V3' R351-2 R352-2 R354-2 # # TMS, TCK, and TDI from Buffer through Series Terminator # and to the FPGA Mezz connector: # NET 'TMS_TO_SERIES_RES' U351-10 R357-2 NET 'TMS_TO_FPGA_MEZZ' R357-1 J3-142 NET 'TCK_TO_SERIES_RES' U351-9 R358-2 NET 'TCK_TO_FPGA_MEZZ' R358-1 J3-141 NET 'TDI_TO_SERIES_RES' U351-8 R359-2 NET 'TDI_TO_FPGA_MEZZ' R359-1 J3-147 # # TDO JTAG signal from the FPGA Mezz through a Series # Terminator to the Buffer through an output Series # Terminator and then to the J12 connector. # NET 'TDO_From_FPGA_Mezz' J3-148 R360-1 NET 'TDO_To_Buffer' R360-2 U351-17 NET 'TDO_To_Output_Series_Res' U351-7 R353-1 NET 'TDO_To_J12' R353-2 J12-8 # # Now connect the Access Signals from their source on # the FPGA Mezz then through the U351 buffer chip and # then through the series back terminator resistors to # their pins on front panel J12: NET 'Access_Signal_1_from_FPGA' J3-41 R361-1 NET 'Access_Signal_2_from_FPGA' J3-43 R362-1 NET 'Access_Signal_1_To_Buffer' R361-2 U351-20 NET 'Access_Signal_2_To_Buffer' R362-2 U351-21 NET 'Access_Signal_1_To_Out_Res' U351-4 R355-1 NET 'Access_Signal_2_To_Out_Res' U351-3 R356-1 NET 'Access_Signal_1' R355-2 J12-15 NET 'Access_Signal_2' R356-2 J12-16 NET 'GROUND' J12-13 J12-14 # # Connect the Power and Ground and DIR and OE_B # to the U351 Translator Buffer chip # # The input "B" side has 3V3 power. # The output "A" side has 3V3 power. # # U351 POWER AND GROUND NET 'BULK_3V3' U351-1 NET 'BULK_3V3' U351-23 U351-24 NET 'GROUND' U351-11 U351-12 U351-13 # U351 DIR and OE_B pins: # # DIR pin #2 is LOW --> from "B" side to "A" side # OE_B pin #22 is LOW --> Enable Outputs NET 'GROUND' U351-2 U351-22 # # ByPass Capacitors for U351 Translators # NET 'BULK_3V3' C351-1 C353-1 NET 'GROUND' C351-2 C353-2 NET 'BULK_3V3' C352-1 C354-1 NET 'GROUND' C352-2 C354-2 # # Define the Un-Used Inputs and Outputs # on the Translator Buffer chip U351. # NET 'No_Conn_U351_Pin_5' U351-5 NET 'No_Conn_U351_Pin_19' U351-19 NET 'No_Conn_U351_Pin_6' U351-6 NET 'No_Conn_U351_Pin_18' U351-18 # # Finally define the two unused pins # on the front panel J12 connector: # NET 'No_Conn_FP_J12_pin_11' J12-11 NET 'No_Conn_FP_J12_pin_12' J12-12 # # HTM Card Net List File # # LED Driver and all LED Associated Nets # ---------------------------------------- # # # Initial Rev. 4-Feb-2018 # Current Rev. 5-Apr-2018 # # # This file holds all of the nets associated with the # HTM card's LEDs: # # driver to LED signals # control signals to drivers # series resistors # # # # Connect J2 Select IO pins to the U201 LED Driver Chip Control Input # NET 'J2_RX11_P_U201_LED_Driver_Control_Input_14' J2-108 U201-14 NET 'J2_RX12_P_U201_LED_Driver_Control_Input_15' J2-114 U201-15 NET 'J2_RX13_P_U201_LED_Driver_Control_Input_16' J2-120 U201-16 NET 'J2_RX14_P_U201_LED_Driver_Control_Input_17' J2-126 U201-17 NET 'J2_RX15_P_U201_LED_Driver_Control_Input_18' J2-132 U201-18 NET 'J2_RX16_P_U201_LED_Driver_Control_Input_19' J2-138 U201-19 NET 'J2_RX17_P_U201_LED_Driver_Control_Input_20' J2-144 U201-20 NET 'J2_RX18_P_U201_LED_Driver_Control_Input_21' J2-150 U201-21 # # Connect LEDs 1-8 to the U201 LED Driver Chip # NET 'LED_1_Cathode_Push_Signal' LED1-1 U201-3 NET 'LED_2_Cathode_Push_Signal' LED2-1 U201-4 NET 'LED_3_Cathode_Push_Signal' LED3-1 U201-5 NET 'LED_4_Cathode_Push_Signal' LED4-1 U201-6 NET 'LED_5_Cathode_Push_Signal' LED5-1 U201-7 NET 'LED_6_Cathode_Push_Signal' LED6-1 U201-8 NET 'LED_7_Cathode_Push_Signal' LED7-1 U201-9 NET 'LED_8_Cathode_Push_Signal' LED8-1 U201-10 # # Connect Bulk_3V3 power to the R201-8 LED Resistors and # connect each R201-8 LED Resistor to one of LEDs 1-8 # NET 'BULK_3V3' R201-2 NET 'LED_1_PU_Res' R201-1 LED1-2 NET 'BULK_3V3' R202-2 NET 'LED_2_PU_Res' R202-1 LED2-2 NET 'BULK_3V3' R203-2 NET 'LED_3_PU_Res' R203-1 LED3-2 NET 'BULK_3V3' R204-2 NET 'LED_4_PU_Res' R204-1 LED4-2 NET 'BULK_3V3' R205-2 NET 'LED_5_PU_Res' R205-1 LED5-2 NET 'BULK_3V3' R206-2 NET 'LED_6_PU_Res' R206-1 LED6-2 NET 'BULK_3V3' R207-2 NET 'LED_7_PU_Res' R207-1 LED7-2 NET 'BULK_3V3' R208-2 NET 'LED_8_PU_Res' R208-1 LED8-2 # # Blocks J13 and J14 # # # Connect J2 Select IO pins to the U201 LED Driver Chip Control Input # NET 'J2_RX1_P_U202_LED_Driver_Control_Input_14' J2-48 U202-14 NET 'J2_RX2_P_U202_LED_Driver_Control_Input_15' J2-54 U202-15 NET 'J2_RX3_P_U202_LED_Driver_Control_Input_16' J2-60 U202-16 NET 'J2_RX4_P_U202_LED_Driver_Control_Input_17' J2-66 U202-17 NET 'J2_RX5_P_U202_LED_Driver_Control_Input_18' J2-72 U202-18 NET 'J2_RX6_P_U202_LED_Driver_Control_Input_19' J2-78 U202-19 NET 'J2_RX7_P_U202_LED_Driver_Control_Input_20' J2-84 U202-20 NET 'J2_RX8_P_U202_LED_Driver_Control_Input_21' J2-90 U202-21 # # Connect J13 LED Cathodes 1-4 to the U202 LED Driver Chip # NET 'J13_LED_1_Cathode_Push_Signal' U202-7 J13-LED1CTH NET 'J13_LED_2_Cathode_Push_Signal' U202-8 J13-LED2CTH NET 'J13_LED_3_Cathode_Push_Signal' U202-10 J13-LED3CTH NET 'J13_LED_4_Cathode_Push_Signal' U202-9 J13-LED4CTH # # Connect Bulk_3V3 power to the R213-16 LED Resistors and # connect each R213-16 LED Resistor to a J14 LED Cathode # NET 'BULK_3V3' R213-1 NET 'J13_LED1_Anode' R213-2 J13-LED1AND NET 'BULK_3V3' R214-1 NET 'J13_LED2_Anode' R214-2 J13-LED2AND NET 'BULK_3V3' R216-1 NET 'J13_LED3_Anode' R216-2 J13-LED3AND NET 'BULK_3V3' R215-1 NET 'J13_LED4_Anode' R215-2 J13-LED4AND # # Connect J14 LED Cathodes 1-4 to the U202 LED Driver Chip # NET 'J14_LED_1_Cathode_Push_Signal' U202-3 J14-LED1CTH NET 'J14_LED_2_Cathode_Push_Signal' U202-4 J14-LED2CTH NET 'J14_LED_3_Cathode_Push_Signal' U202-6 J14-LED3CTH NET 'J14_LED_4_Cathode_Push_Signal' U202-5 J14-LED4CTH # # Connect Bulk_3V3 power to the R209-12 LED Resistors and # connect each R209-12 LED Resistor to a J14 LED Cathode # NET 'BULK_3V3' R209-2 NET 'J14_LED1_Anode' R209-1 J14-LED1AND NET 'BULK_3V3' R210-2 NET 'J14_LED2_Anode' R210-1 J14-LED2AND NET 'BULK_3V3' R212-2 NET 'J14_LED3_Anode' R212-1 J14-LED3AND NET 'BULK_3V3' R211-2 NET 'J14_LED4_Anode' R211-1 J14-LED4AND # # Iso_12V Power LED # NET 'GROUND' LED17-1 NET 'LED17_Anode' LED17-2 R217-1 NET 'LED17_Drop_One' R217-2 R218-1 NET 'LED17_Drop_Two' R218-2 R219-1 NET 'ISO_12V' R219-2 # # Power to the LED Driver Chips # # and their ByPass Capacitors # # # Connect the Power and Ground and DIR and OE_B # to the U201 and U202 LED Driver Chips # # The input "B" side has 3V3 power. # The output "A" side has 3V3 power. # # U201 POWER AND GROUND NET 'BULK_3V3' U201-1 NET 'BULK_3V3' U201-23 U201-24 NET 'GROUND' U201-11 U201-12 U201-13 # U201 DIR and OE_B pins: NET 'GROUND' U201-2 U201-22 # U202 POWER AND GROUND NET 'BULK_3V3' U202-1 NET 'BULK_3V3' U202-23 U202-24 NET 'GROUND' U202-11 U202-12 U202-13 # U201 DIR and OE_B pins: NET 'GROUND' U202-2 U202-22 # # ByPass Capacitors for U201 & U202 LED Driver Chips # NET 'BULK_3V3' C201-1 C203-1 NET 'GROUND' C201-2 C203-2 NET 'BULK_3V3' C202-1 C204-1 NET 'GROUND' C202-2 C204-2 # # Hardware Address Nets # # HTM-0 Key-In Net List File # # # Original Rev. 9-Mar-2018 # Current Rev. 28-Mar-2018 # # # # # This nets files contains all of the connections # on the HTM Card that are associated with the # ATCA Hardware Address signals. # # # # # Slot Number Hardware Address Lines # from the ATCA Backplane # NET 'HW_ADRS_0' P10-5 NET 'HW_ADRS_1' P10-6 NET 'HW_ADRS_2' P10-7 NET 'HW_ADRS_3' P10-8 NET 'HW_ADRS_4' P10-9 NET 'HW_ADRS_5' P10-10 NET 'HW_ADRS_6' P10-11 NET 'HW_ADRS_7' P10-12 # # Filters on the # Slot Number Hardware Address # NET 'HW_ADRS_1' C171-2 R171-1 NET 'HW_ADRS_3' C172-2 R172-1 NET 'HW_ADRS_0' C173-2 R173-1 NET 'HW_ADRS_2' C174-2 R174-1 NET 'HW_ADRS_4' C175-2 R175-1 NET 'HW_ADRS_6' C176-2 R176-1 NET 'HW_ADRS_5' C177-2 R177-1 NET 'HW_ADRS_7' C178-2 R178-1 NET 'GROUND' C171-1 C172-1 NET 'GROUND' C173-1 C174-1 NET 'GROUND' C175-1 C176-1 NET 'GROUND' C177-1 C178-1 NET 'BULK_3V3' R171-2 R172-2 NET 'BULK_3V3' R173-2 R174-2 NET 'BULK_3V3' R175-2 R176-2 NET 'BULK_3V3' R177-2 R178-2 # # Send Slot Number Hardware # Address to FPGA Mezzanine # NET 'HW_ADRS_0' J3-83 NET 'HW_ADRS_1' J3-89 NET 'HW_ADRS_2' J3-53 NET 'HW_ADRS_3' J3-47 NET 'HW_ADRS_4' J3-77 NET 'HW_ADRS_5' J3-71 NET 'HW_ADRS_6' J3-59 NET 'HW_ADRS_7' J3-65 # # HTM Card Net List File # # Clock Generation and Associated Nets # ----------------------------------------- # # # Initial Rev. 4-Feb-2018 # Current Rev. 23-Apr-2018 # # # This file holds all of the nets associated with the # Clock Generation on the HTM circuit board and # associated circuits such as Spare Crystal Oscillator # and Buffers. # # # Note that all differential pairs in this section are # wired right-side-up except for the Ref Clk feed to the # Si Labs chip on the FPGA Mezz. # # The Ref Clk feed to the Si Labs chip on the FPGA Mezz will # appear to be wired up-side-down because of the way that # they designed the FPGA Mezz card, i.e. they have a flip # in their naming, e.g. FPGA Mezz pin J3-40 is labeled # Si5328_Clk1_N but it goes to pin #1 of the Si5338 # which is its non-inverting Ref Clk input. # # To help keep things straight I put all the chip pin # number pin name information here: # # CDC LVD 1204 # # In 0 Dir pin 6 In 1 Dir pin 3 # In 0 Cmp pin 7 In 1 Cmp pin 4 # # Out 0 Dir pin 9 Out 1 Dir pin 11 # Out 0 Cmp pin 10 Out 1 Cmp pin 12 # # Out 2 Dir pin 13 Out 3 Dir pin 15 # Out 2 Cmp pin 14 Out 3 Cmp pin 16 # # 65 LVDS 2 # # In Dir pin 3 Out pin 5 # In Cmp pin 4 Vcc pin 1 Gnd pin 2 # # SFX-524G-CRN1 PLL # # Output_Dir U253-6 # Output_Cmp U253-7 # # Logic Clk feed to the FPGA 40.08 MHz via FPGA Mezz card # # J3-156 goes to FPGA pin AE22 which is IO_L12P_T1_MRCC_11 # J3-158 goes to FPGA pin AF22 which is IO_L12N_T1_MRCC_11 # # Si Labs 5338 Ref Clk feed 40.08 MHz via FPGA Mezz card # # J3-38 Si5328_Clk1_P U2-2 IN2 Cmp # J3-40 Si5328_Clk1_N U2-1 IN1 Dir # # # # Generation of the 40.0787 MHz Clock on the HTM # # # Receive the Hub #1 LHC Reference Clock # NET 'Hub_1_Ref_Clk_Dir' J23-C4 R261-1 U252-3 NET 'Hub_1_Ref_Clk_Cmp' J23-D4 R262-1 U252-4 NET 'Hub_1_Ref_Clk_CMM' R261-2 R262-2 R263-2 R264-2 C254-1 NET 'CLK_3V3' U252-1 C253-1 R263-1 NET 'GROUND' U252-2 C253-2 R264-1 C254-2 NET 'Recvd_Hub_1_Ref_Clk' U252-5 R265-1 # # 40.0787 MHz PLL # NET 'Bk_Trm_Rcvd_Hub_1_Ref_Clk' R265-2 U253-1 NET 'PLL_40_Clk_Out_Dir' U253-6 R266-1 NET 'PLL_40_Clk_Out_Cmp' U253-7 R267-1 NET 'RC_PLL_40_Clk_Out_Dir' R266-2 C256-1 NET 'RC_PLL_40_Clk_Out_Cmp' R267-2 C257-1 NET 'Raw_PLL_40_MHz_Locked' U253-10 R268-1 NET 'PLL_40_MHz_Locked_Mon' J3-101 R268-2 NET 'CLK_3V3' U253-9 C258-1 C259-1 C260-1 NET 'GROUND' U253-2 U253-8 NET 'GROUND' C258-2 C259-2 C260-2 NET 'No_Conn_PLL_pin_3' U253-3 NET 'No_Conn_PLL_pin_4' U253-4 NET 'No_Conn_PLL_pin_5' U253-5 # # 40.0787 MHz 4x Buffer FanOut # NET 'PLL_40_MHz_Signal_Dir' C256-2 U254-6 R271-1 NET 'PLL_40_MHz_Signal_Cmp' C257-2 U254-7 R272-1 NET 'FanOut_Input_CMM_Ref' U254-8 U254-4 R271-2 R272-2 C255-1 NET 'GROUND' U254-1 C255-2 NET 'GROUND' U254-17 U254-18 U254-19 U254-20 NET 'CLK_2V5' U254-5 C262-1 C263-1 NET 'GROUND' C262-2 C263-2 NET 'Fan_40_MHz_In_Sel' U254-2 R273-1 NET 'Fan_40_MHz_In_2_Bias' U254-3 R274-1 NET 'GROUND' R273-2 R274-2 NET 'No_Conn_Clk_Fanout_9' U254-9 NET 'No_Conn_Clk_Fanout_10' U254-10 # # 40.0787 MHz FanOut Feed to FPGA Global Logic Clock # # The 40.08 MHz Logic Clock goes to the FPGA Mezz on # its pins J3-156 & J3-158. These connect to # FPGA pins AE22 & AF22 which are IO_L12P_T1_MRCC_11 # and IO_L12N_T1_MRCC_11 Bank #11 Multi Region # 3V3 Clock Inputs to the FPGA. # NET 'Pre_Cap_FPGA_40_MHz_Logic_Clk_Dir' U254-13 C266-1 NET 'Pre_Cap_FPGA_40_MHz_Logic_Clk_Cmp' U254-14 C267-1 NET 'FPGA_40_MHz_Logic_Clk_Dir' C266-2 J3-156 NET 'FPGA_40_MHz_Logic_Clk_Cmp' C267-2 J3-158 # # 40.0787 MHz FanOut Feed to SiLab 5338A # # Note that based on the FPGA Mezz card's pin names # there would appear to be a polarity flip but there # is not one. The Dir output from the Fanout chip # goes to the Reference Dir input on the Si Labs Si5338. # # FPGA Mezz pin J3-40 goes to the Ref Dir input on Si5338. # NET 'Pre_Cap_40_MHz_SiLab_Dir' U254-15 R275-1 C264-1 NET 'Pre_Cap_40_MHz_SiLab_Cmp' U254-16 R275-2 C265-1 NET 'Ref_40_MHz_to_SiLab_Dir' C264-2 J3-40 NET 'Ref_40_MHz_to_SiLab_Cmp' C265-2 J3-38 # # 40.0787 MHz FanOut Feed to Front Panel Monitor Buffer # NET 'Mon_Cp_40_Clk_Dir' U254-11 NET 'Mon_Cp_40_Clk_Cmp' U254-12 # # Buffered Copy of the HTM's 40.0787 MHz Clock # for Front Panel Monitoring # NET 'Mon_Cp_40_Clk_Dir' U255-3 R276-1 NET 'Mon_Cp_40_Clk_Cmp' U255-4 R276-2 NET 'BULK_3V3' U255-1 C268-1 NET 'GROUND' U255-2 C268-2 NET 'Bufd_Mon_40_Clk' U255-5 R277-1 NET 'FP_Mon_40_Clk_Hub_1' R277-2 J15-5 NET 'GROUND' J15-1 J15-2 J15-3 J15-4 # # Receive the Hub #2 LHC Reference Clock Just for Monitoring # NET 'Hub_2_Ref_Clk_Dir' J23-C2 R251-1 U251-3 NET 'Hub_2_Ref_Clk_Cmp' J23-D2 R252-1 U251-4 NET 'Hub_2_Ref_Clk_CMM' R251-2 R252-2 R253-2 R254-2 C252-1 NET 'BULK_3V3' U251-1 C251-1 R253-1 NET 'GROUND' U251-2 C251-2 R254-1 C252-2 NET 'Recvd_Hub_2_Ref_Clk' U251-5 R255-1 R256-1 NET 'Hub_2_Ref_Mon_to_FP' R255-2 J16-5 NET 'GROUND' J16-1 J16-2 J16-3 J16-4 NET 'Hub_2_Ref_Mon_to_FPGA' R256-2 J2-53 # # Spare LVDS Output Crystal Oscillator # # The Spare Clock goes to the FPGA Mezz on # its pins J2-156 & J2-158. These connect to # FPGA pins AC28 & AD28 which are IO_L12P_T1_MRCC_12 # and IO_L12N_T1_MRCC_12 Bank #12 Multi Region # 3V3 Clock Inputs to the FPGA. # NET 'Xtal_Osc_1_to_Cap_Dir' U256-4 C271-1 NET 'Xtal_Osc_1_to_Cap_Cmp' U256-5 C272-1 NET 'Spare_Osc_to_FPGA_Dir' C271-2 J2-156 NET 'Spare_Osc_to_FPGA_Cmp' C272-2 J2-158 NET 'CLK_3V3' U256-6 C269-2 C270-2 NET 'GROUND' U256-3 C269-1 C270-1 Net 'NO_CONN_U271_Pin_1' U256-1 Net 'NO_CONN_U271_Pin_2' U256-2 # # CLK_3V3 Power Filter for the Clock Generation, # Buffers, Crystal Oscillator, and associated components # NET 'BULK_3V3' C275-1 L251-2 NET 'CLK_3V3' L251-1 C276-1 C277-1 C261-1 NET 'GROUND' C275-2 C276-2 C277-2 C261-2 # # CLK_2V5 Power Filter for the 40.08 MHz Clock # LVDS Fanout Buffer U254 # NET 'BULK_2V5' C281-1 L281-2 NET 'CLK_2V5' L281-1 C282-1 NET 'GROUND' C281-2 C282-2 # # This is the Key In Net List file for the # # HTM Module Shelf Ground Nets # ---------------------============--------------- # # # Original Rev. 4-Feb-2018 # Most Recent Rev. 4-Apr-2018 # # # # This file includes the SHELF_GND connections # # SHELF_GND starts with pin #25 on the Zone 1 backplane # connector. This net connection is in the nets file: # atca_power_entry_nets # # # Shelf_GND to: Front ESD Strip, RJ45s, Alignment Pin # NET 'SHELF_GND' ESD_Strip_FO-3 NET 'SHELF_GND' J13-M1 J13-M2 J13-M3 J13-M4 J13-GC1 NET 'SHELF_GND' J14-M1 J14-M2 J14-M3 J14-M4 J14-GC1 NET 'SHELF_GND' K1-1 K1-2 K1-3 # # Shelf_GND to: Rear ESD Strip, Logic_Gnd # NET 'SHELF_GND' R958-2 NET 'ESD_STRIP_ONE' R958-1 ESD_Strip_MB-1 NET 'SHELF_GND' R959-1 NET 'GROUND' R959-2 # # LOGIC Ground to ESD Strip # NET 'ESD_STRIP_TWO' ESD_Strip_MB-2 R957-1 NET 'GROUND' R957-2 # # Shelf_GND to: Horz and Vert Air Baffels # NET 'SHELF_GND' Horz_Air_Baffle-1 NET 'SHELF_GND' Horz_Air_Baffle-2 NET 'SHELF_GND' Horz_Air_Baffle-3 NET 'SHELF_GND' Horz_Air_Baffle-4 NET 'SHELF_GND' Vert_Air_Baffle-1 NET 'SHELF_GND' Vert_Air_Baffle-2 NET 'SHELF_GND' Vert_Air_Baffle-3 # # HTM Card Net List File # # Backplane Connector J23 Ground Pins # --------------------------------------- # # Initial Rev. 1-Feb-2018 # Current Rev. 28-Feb-2018 # # # This file holds all of the Ground connections for # the Zone 2 connector J23. # # Each of the Zone 2 ADFplus connectors has 80 ground # connections pins and 80 signal pins that make # up 40 differential pairs. # # There can be up to 5 Zone 2 connectors with # Reference Designators J20 through J24. # # The HTM card has only one Zone 2 connector J23. # # # Connector J23 # NET 'GROUND' J23-AG1 J23-AG2 J23-AG3 J23-AG4 J23-AG5 NET 'GROUND' J23-AG6 J23-AG7 J23-AG8 J23-AG9 J23-AG10 NET 'GROUND' J23-BG1 J23-BG2 J23-BG3 J23-BG4 J23-BG5 NET 'GROUND' J23-BG6 J23-BG7 J23-BG8 J23-BG9 J23-BG10 NET 'GROUND' J23-CG1 J23-CG2 J23-CG3 J23-CG4 J23-CG5 NET 'GROUND' J23-CG6 J23-CG7 J23-CG8 J23-CG9 J23-CG10 NET 'GROUND' J23-DG1 J23-DG2 J23-DG3 J23-DG4 J23-DG5 NET 'GROUND' J23-DG6 J23-DG7 J23-DG8 J23-DG9 J23-DG10 NET 'GROUND' J23-EG1 J23-EG2 J23-EG3 J23-EG4 J23-EG5 NET 'GROUND' J23-EG6 J23-EG7 J23-EG8 J23-EG9 J23-EG10 NET 'GROUND' J23-FG1 J23-FG2 J23-FG3 J23-FG4 J23-FG5 NET 'GROUND' J23-FG6 J23-FG7 J23-FG8 J23-FG9 J23-FG10 NET 'GROUND' J23-GG1 J23-GG2 J23-GG3 J23-GG4 J23-GG5 NET 'GROUND' J23-GG6 J23-GG7 J23-GG8 J23-GG9 J23-GG10 NET 'GROUND' J23-HG1 J23-HG2 J23-HG3 J23-HG4 J23-HG5 NET 'GROUND' J23-HG6 J23-HG7 J23-HG8 J23-HG9 J23-HG10 # # Unused Pins # NET 'No_Conn_J23_pin_A7' J23-A7 NET 'No_Conn_J23_pin_B7' J23-B7 NET 'No_Conn_J23_pin_C7' J23-C7 NET 'No_Conn_J23_pin_D7' J23-D7 NET 'No_Conn_J23_pin_E7' J23-E7 NET 'No_Conn_J23_pin_F7' J23-F7 NET 'No_Conn_J23_pin_G7' J23-G7 NET 'No_Conn_J23_pin_H7' J23-H7 NET 'No_Conn_J23_pin_A8' J23-A8 NET 'No_Conn_J23_pin_B8' J23-B8 NET 'No_Conn_J23_pin_C8' J23-C8 NET 'No_Conn_J23_pin_D8' J23-D8 NET 'No_Conn_J23_pin_E8' J23-E8 NET 'No_Conn_J23_pin_F8' J23-F8 NET 'No_Conn_J23_pin_G8' J23-G8 NET 'No_Conn_J23_pin_H8' J23-H8 NET 'No_Conn_J23_pin_A9' J23-A9 NET 'No_Conn_J23_pin_B9' J23-B9 NET 'No_Conn_J23_pin_C9' J23-C9 NET 'No_Conn_J23_pin_D9' J23-D9 NET 'No_Conn_J23_pin_E9' J23-E9 NET 'No_Conn_J23_pin_F9' J23-F9 NET 'No_Conn_J23_pin_G9' J23-G9 NET 'No_Conn_J23_pin_H9' J23-H9 NET 'No_Conn_J23_pin_A10' J23-A10 NET 'No_Conn_J23_pin_B10' J23-B10 NET 'No_Conn_J23_pin_C10' J23-C10 NET 'No_Conn_J23_pin_D10' J23-D10 NET 'No_Conn_J23_pin_E10' J23-E10 NET 'No_Conn_J23_pin_F10' J23-F10 NET 'No_Conn_J23_pin_G10' J23-G10 NET 'No_Conn_J23_pin_H10' J23-H10 # # HTM Card Net List File # # FPGA Mezzanine J1 Connector Power and Ground Pins # ----------------------------------------------------- # # Initial Rev. 1-Feb-2018 # Current Rev. 5-Feb-2018 # # # This file holds all of the Power and Ground connections for # the FPGA Mezzanine connector J1. # # # # FPGA Connector J1 Power Pins # # # FPGA Mezzanine J1 Connector 1V8 and 3V3 Pins # NET 'MEZZ_1V8' J1-169 J1-171 NET 'MEZZ_1V8' J1-170 J1-172 # # FPGA Connector J1 Ground Pins # NET 'GROUND' J1-51 J1-57 J1-63 J1-69 J1-75 NET 'GROUND' J1-81 J1-87 J1-93 J1-111 J1-117 NET 'GROUND' J1-123 J1-129 J1-135 J1-141 J1-147 NET 'GROUND' J1-153 J1-161 J1-163 J1-165 J1-167 NET 'GROUND' J1-52 J1-58 J1-64 J1-70 J1-76 NET 'GROUND' J1-82 J1-88 J1-94 J1-112 J1-118 NET 'GROUND' J1-124 J1-130 J1-136 J1-142 J1-148 NET 'GROUND' J1-154 J1-162 J1-164 J1-166 J1-168 # # HTM Card Net List File # # FPGA Mezzanine J2 Connector Power and Ground Pins # ----------------------------------------------------- # # Initial Rev. 1-Feb-2018 # Current Rev. 5-Feb-2018 # # # This file holds all of the Power and Ground connections for # the FPGA Mezzanine connector J2. # # # # FPGA Connector J2 Power Pins # NET 'ISO_12V' J2-165 J2-167 NET 'ISO_12V' J2-166 J2-168 # # FPGA Connector J2 Bulk 3V3 Pins # NET 'BULK_3V3' J2-147 J2-148 # # FPGA Mezzanine J2 Connector 1V8 and 3V3 Pins # NET 'MEZZ_3V3' J2-111 J2-123 J2-135 J2-169 J2-171 NET 'MEZZ_3V3' J2-112 J2-124 J2-136 J2-170 J2-172 # # FPGA Connector J2 Ground Pins # NET 'GROUND' J2-45 J2-93 J2-105 J2-117 J2-129 NET 'GROUND' J2-141 J2-153 J2-161 J2-163 NET 'GROUND' J2-46 J2-52 J2-58 J2-64 J2-70 NET 'GROUND' J2-76 J2-82 J2-88 J2-94 J2-106 NET 'GROUND' J2-118 J2-130 J2-142 J2-154 J2-162 NET 'GROUND' J2-164 # # HTM Card Net List File # # FPGA Mezzanine J3 Connector Power and Ground Pins # ----------------------------------------------------- # # Initial Rev. 1-Feb-2018 # Current Rev. 5-Feb-2018 # # # This file holds all of the Power and Ground connections for # the FPGA Mezzanine connector J2. # # # # FPGA Connector J3 Power Pins # # # FPGA Mezzanine J3 Connector 1V8 and 3V3 Pins # # # FPGA Connector J3 Ground Pins # NET 'GROUND' J3-45 J3-51 J3-57 J3-63 J3-69 NET 'GROUND' J3-75 J3-93 J3-105 J3-111 J3-117 NET 'GROUND' J3-123 J3-153 J3-161 J3-163 J3-165 NET 'GROUND' J3-167 J3-169 J3-171 NET 'GROUND' J3-46 J3-52 J3-58 J3-64 J3-70 NET 'GROUND' J3-94 J3-106 J3-112 J3-118 J3-154 NET 'GROUND' J3-162 J3-164 J3-166 J3-168 J3-170 NET 'GROUND' J3-172 # # Net List File # # J23 Combined Data from Hubs 1 and 2 to FPGA Mezzanine J3 # -------------------------------------------------------------- # # # Initial Rev. 16-Feb-2018 # Current Rev. 9-Aprr-2018 # # # This net list file contains the connections for the # HTM to receive Combined Data from both Hub 1 and Hub 2. # # # # # # Note that the Combined Data from Hub 1 # is being received with a Polarity Flip. # The J23 connector pins have been swapped. # NET 'Combined_Data_from_HUB1_to_MGT_RX_9_DIR' J23-H4 J1-5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Combined_Data_from_HUB1_to_MGT_RX_9_CMP' J23-G4 J1-7 (NET_TYPE, 'DIFF_PAIR_HS') # # J23 pin G4 is a DIR Combined Data signal from the backplane. # J23 pin H4 is a CMP Combined Data signal from the backplane. # # # Note that the Combined Data from Hub 2 # is being received with a Polarity Flip. # The J23 connector pins have been swapped. # NET 'Combined_Data_from_HUB2_to_MGT_RX_6_DIR' J23-H2 J3-8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Combined_Data_from_HUB2_to_MGT_RX_6_CMP' J23-G2 J3-6 (NET_TYPE, 'DIFF_PAIR_HS') # # J23 pin G2 is a DIR Combined Data signal from the backplane. # J23 pin H2 is a CMP Combined Data signal from the backplane. # # # Mini_POD Net List File # # Mini_POD Receiver and Transmitter Nets # ----------------------------------------------------- # # Initial Rev. 16-Feb-2018 # Current Rev. 10-Apr-2018 # # # This file holds all nets associated the MiniPOD receiver and # and transmitter modules # # # # MiniPOD Receiver Module Nets # -------==========----------- # # # Connect MiniPOD Receiver Outputs for # Fibers: 1,3,5,7,9,11 to J1 MGT Receivers # # Fibers: 1, 7, 9 have Polarity Flips # # Polarity Flips are implemented by # swapping pins at the J1 connector. # NET 'Mini_POD_Rec_D1_to_Cap_DIR' Rec_MP-F1 C27-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D1_to_Cap_CMP' Rec_MP-F2 C28-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D1_to_MGT_DIR' C27-2 J1-31 (NET_TYPE, 'DIFF_PAIR_HS') # Polarity NET 'Mini_POD_Cap_D1_to_MGT_CMP' C28-2 J1-29 (NET_TYPE, 'DIFF_PAIR_HS') # Flip NET 'Mini_POD_Rec_D3_to_Cap_DIR' Rec_MP-J2 C31-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D3_to_Cap_CMP' Rec_MP-H2 C32-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D3_to_MGT_DIR' C31-2 J1-25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D3_to_MGT_CMP' C32-2 J1-27 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D5_to_Cap_DIR' Rec_MP-J4 C35-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D5_to_Cap_CMP' Rec_MP-H4 C36-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D5_to_MGT_DIR' C35-2 J1-21 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D5_to_MGT_CMP' C36-2 J1-23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D7_to_Cap_DIR' Rec_MP-J6 C39-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D7_to_Cap_CMP' Rec_MP-H6 C40-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D7_to_MGT_DIR' C39-2 J1-19 (NET_TYPE, 'DIFF_PAIR_HS') # Polarity NET 'Mini_POD_Cap_D7_to_MGT_CMP' C40-2 J1-17 (NET_TYPE, 'DIFF_PAIR_HS') # Flip NET 'Mini_POD_Rec_D9_to_Cap_DIR' Rec_MP-J8 C43-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D9_to_Cap_CMP' Rec_MP-H8 C44-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D9_to_MGT_DIR' C43-2 J1-15 (NET_TYPE, 'DIFF_PAIR_HS') # Polarity NET 'Mini_POD_Cap_D9_to_MGT_CMP' C44-2 J1-13 (NET_TYPE, 'DIFF_PAIR_HS') # Flip NET 'Mini_POD_Rec_D11_to_Cap_DIR' Rec_MP-F9 C47-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D11_to_Cap_CMP' Rec_MP-F8 C48-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D11_to_MGT_DIR' C47-2 J1-9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D11_to_MGT_CMP' C48-2 J1-11 (NET_TYPE, 'DIFF_PAIR_HS') # # Connect MiniPOD Receiver Outputs for # Fibers: 0,2,4,6,8,10 to J3 MGT Receivers # # Fiber 2 has Polarity Flip # # Polarity Flips are implemented by # swapping pins at the J3 connector. # NET 'Mini_POD_Rec_D10_to_Cap_DIR' Rec_MP-D9 C45-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D10_to_Cap_CMP' Rec_MP-D8 C46-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D10_to_MGT_DIR' C45-2 J3-12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D10_to_MGT_CMP' C46-2 J3-10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D8_to_Cap_DIR' Rec_MP-A8 C41-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D8_to_Cap_CMP' Rec_MP-B8 C42-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D8_to_MGT_DIR' C41-2 J3-16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D8_to_MGT_CMP' C42-2 J3-14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D6_to_Cap_DIR' Rec_MP-A6 C37-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D6_to_Cap_CMP' Rec_MP-B6 C38-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D6_to_MGT_DIR' C37-2 J3-20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D6_to_MGT_CMP' C38-2 J3-18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D4_to_Cap_DIR' Rec_MP-A4 C33-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D4_to_Cap_CMP' Rec_MP-B4 C34-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D4_to_MGT_DIR' C33-2 J3-24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D4_to_MGT_CMP' C34-2 J3-22 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D2_to_Cap_DIR' Rec_MP-A2 C29-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D2_to_Cap_CMP' Rec_MP-B2 C30-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D2_to_MGT_DIR' C29-2 J3-26 (NET_TYPE, 'DIFF_PAIR_HS') # Polarity NET 'Mini_POD_Cap_D2_to_MGT_CMP' C30-2 J3-28 (NET_TYPE, 'DIFF_PAIR_HS') # Flip NET 'Mini_POD_Rec_D0_to_Cap_DIR' Rec_MP-D1 C25-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Rec_D0_to_Cap_CMP' Rec_MP-D2 C26-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D0_to_MGT_DIR' C25-2 J3-32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Cap_D0_to_MGT_CMP' C26-2 J3-30 (NET_TYPE, 'DIFF_PAIR_HS') # # Receiver MiniPOD Ground Pin Connections # NET 'GROUND' Rec_MP-A1 Rec_MP-B1 NET 'GROUND' Rec_MP-A3 Rec_MP-B3 NET 'GROUND' Rec_MP-A5 Rec_MP-B5 NET 'GROUND' Rec_MP-A7 Rec_MP-B7 NET 'GROUND' Rec_MP-A9 Rec_MP-B9 NET 'GROUND' Rec_MP-C1 Rec_MP-C2 NET 'GROUND' Rec_MP-C8 Rec_MP-C9 NET 'GROUND' Rec_MP-D3 Rec_MP-D7 NET 'GROUND' Rec_MP-E1 Rec_MP-E2 NET 'GROUND' Rec_MP-E8 Rec_MP-E9 NET 'GROUND' Rec_MP-F3 Rec_MP-F7 NET 'GROUND' Rec_MP-G1 Rec_MP-G2 NET 'GROUND' Rec_MP-G8 Rec_MP-G9 NET 'GROUND' Rec_MP-H1 Rec_MP-J1 NET 'GROUND' Rec_MP-H3 Rec_MP-J3 NET 'GROUND' Rec_MP-H5 Rec_MP-J5 NET 'GROUND' Rec_MP-H7 Rec_MP-J7 NET 'GROUND' Rec_MP-H9 Rec_MP-J9 NET 'GROUND' Rec_MP-SCRW1 Rec_MP-SCRW2 # # Receiver Module TWS Bus Address Signals # # Address 0 NET 'GROUND' Rec_MP-G3 # Address 1 NET 'GROUND' Rec_MP-E3 # Address 2 NET 'GROUND' Rec_MP-C3 # # Receiver: Reset, SDA, SCL, and Interrupt Signals # # Pull-Up Resistors and FPGA Mezz Connections # NET 'MP_Rec_INTR' Rec_MP-D6 R445-1 J3-80 NET 'MP_Rec_SDA' Rec_MP-D4 R446-1 J3-78 NET 'MP_Rec_SCL' Rec_MP-E6 R447-1 J3-74 NET 'MP_Rec_RESET' Rec_MP-E4 R448-1 J3-72 NET 'MP_Rec_3V3' R445-2 R446-2 R447-2 R448-2 # # Receiver MiniPOD Power Supply Nets # NET 'MP_Rec_3V3' Rec_MP-C4 Rec_MP-C5 Rec_MP-C6 NET 'MP_Rec_2V5' Rec_MP-F4 NET 'MP_Rec_2V5' Rec_MP-G4 Rec_MP-G5 Rec_MP-G6 # # Receiver MiniPOD 2.5 Volt Power Filter NET 'BULK_2V5' L431-1 C431-1 C432-2 C433-1 NET 'GROUND' C431-2 C432-1 C433-2 NET 'MP_Rec_2V5' L431-2 C434-2 C435-1 C436-1 NET 'GROUND' C434-1 C435-2 R431-1 NET 'MP_Rec_2V5_FLT_RES' C436-2 R431-2 # # Receiver MiniPOD 3.3 Volt Power Filter NET 'BULK_3V3' L441-1 C441-1 C442-2 C443-1 NET 'GROUND' C441-2 C442-1 C443-2 NET 'MP_Rec_3V3' L441-2 C444-2 C445-1 C446-1 NET 'GROUND' C444-1 C445-2 R441-1 NET 'MP_Rec_3V3_FLT_RES' C446-2 R441-2 # # Now the Do Not Connect Pins # on the Receiver MiniPOD # NET 'No_Conn_Rec_MP_C7' Rec_MP-C7 NET 'No_Conn_Rec_MP_D5' Rec_MP-D5 NET 'No_Conn_Rec_MP_E5' Rec_MP-E5 NET 'No_Conn_Rec_MP_E7' Rec_MP-E7 NET 'No_Conn_Rec_MP_F5' Rec_MP-F5 NET 'No_Conn_Rec_MP_F6' Rec_MP-F6 NET 'No_Conn_Rec_MP_G7' Rec_MP-G7 ########################################### # # # Receive Above Transmit Below # # # ########################################### # # # MiniPOD Transmitter Module Nets # -------=============----------- # # Connect MiniPOD Transmitter Data Inputs for # Fibers 0 through 3 to J1 MGT Transmitters # # Fiber 0 has a Polarity Flips # # Polarity Flips are implemented by # swapping pins at the J1 connector. # NET 'Mini_POD_Trans_D2_DIR' Trans_MP-A2 J1-18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Trans_D2_CMP' Trans_MP-B2 J1-20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Trans_D0_DIR' Trans_MP-D1 J1-24 (NET_TYPE, 'DIFF_PAIR_HS') # Polarity NET 'Mini_POD_Trans_D0_CMP' Trans_MP-D2 J1-22 (NET_TYPE, 'DIFF_PAIR_HS') # Flip NET 'Mini_POD_Trans_D1_DIR' Trans_MP-F1 J1-26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Trans_D1_CMP' Trans_MP-F2 J1-28 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Trans_D3_DIR' Trans_MP-H2 J1-30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'Mini_POD_Trans_D3_CMP' Trans_MP-J2 J1-32 (NET_TYPE, 'DIFF_PAIR_HS') # # Transmitter MiniPOD Ground Pin Connections # NET 'GROUND' Trans_MP-A1 Trans_MP-B1 NET 'GROUND' Trans_MP-A3 Trans_MP-B3 NET 'GROUND' Trans_MP-A5 Trans_MP-B5 NET 'GROUND' Trans_MP-A7 Trans_MP-B7 NET 'GROUND' Trans_MP-A9 Trans_MP-B9 NET 'GROUND' Trans_MP-C1 Trans_MP-C2 NET 'GROUND' Trans_MP-C8 Trans_MP-C9 NET 'GROUND' Trans_MP-D3 Trans_MP-D7 NET 'GROUND' Trans_MP-E1 Trans_MP-E2 NET 'GROUND' Trans_MP-E8 Trans_MP-E9 NET 'GROUND' Trans_MP-F3 Trans_MP-F7 NET 'GROUND' Trans_MP-G1 Trans_MP-G2 NET 'GROUND' Trans_MP-G8 Trans_MP-G9 NET 'GROUND' Trans_MP-H1 Trans_MP-J1 NET 'GROUND' Trans_MP-H3 Trans_MP-J3 NET 'GROUND' Trans_MP-H5 Trans_MP-J5 NET 'GROUND' Trans_MP-H7 Trans_MP-J7 NET 'GROUND' Trans_MP-H9 Trans_MP-J9 NET 'GROUND' Trans_MP-SCRW1 Trans_MP-SCRW2 # # Transmitter Module TWS Bus Address Signals # # Address 0 NET 'GROUND' Trans_MP-G3 # Address 1 NET 'GROUND' Trans_MP-E3 # Address 2 NET 'GROUND' Trans_MP-C3 # # Transmitter: Reset, SDA, SCL, and Interrupt Signals # # Pull-Up Resistors and FPGA Mezz Connections # NET 'MP_Trans_INTR' Trans_MP-D6 R425-1 J3-66 NET 'MP_Trans_SDA' Trans_MP-D4 R426-1 J3-60 NET 'MP_Trans_SCL' Trans_MP-E6 R427-1 J3-54 NET 'MP_Trans_RESET' Trans_MP-E4 R428-1 J3-48 NET 'MP_Trans_3V3' R425-2 R426-2 R427-2 R428-2 # # Transmitter MiniPOD Power Supply Nets # NET 'MP_Trans_3V3' Trans_MP-C4 Trans_MP-C5 Trans_MP-C6 NET 'MP_Trans_2V5' Trans_MP-F4 NET 'MP_Trans_2V5' Trans_MP-G4 Trans_MP-G5 Trans_MP-G6 # # Transmitter MiniPOD 2.5 Volt Power Filter NET 'BULK_2V5' L411-1 C411-1 C412-2 C413-1 NET 'GROUND' C411-2 C412-1 C413-2 NET 'MP_Trans_2V5' L411-2 C414-2 C415-1 C416-1 NET 'GROUND' C414-1 C415-2 R411-1 NET 'MP_Trans_2V5_FLT_RES' C416-2 R411-2 # # Transmitter MiniPOD 3.3 Volt Power Filter NET 'BULK_3V3' L421-1 C421-1 C422-2 C423-1 NET 'GROUND' C421-2 C422-1 C423-2 NET 'MP_Trans_3V3' L421-2 C424-2 C425-1 C426-1 NET 'GROUND' C424-1 C425-2 R421-1 NET 'MP_Trans_3V3_FLT_RES' C426-2 R421-2 # # Now the Do Not Connect Pins # on the Transmitter MiniPOD # NET 'No_Conn_Trans_MP_C7' Trans_MP-C7 NET 'No_Conn_Trans_MP_D5' Trans_MP-D5 NET 'No_Conn_Trans_MP_E5' Trans_MP-E5 NET 'No_Conn_Trans_MP_E7' Trans_MP-E7 NET 'No_Conn_Trans_MP_F5' Trans_MP-F5 NET 'No_Conn_Trans_MP_F6' Trans_MP-F6 NET 'No_Conn_Trans_MP_G7' Trans_MP-G7 # # We are only using 4 of the 12 Channels/Fibers # in the Transmitter MiniPOD because we only # have 4 MGT Transmitters available to drive the # Transmitter MiniPOD. # # The 4 Fibers that we are using are # MiniPOD Fiber numbers: 0, 1, 2, 3 # # The Data Input pins for the other 8 Fibers are # not connected in the HTM design and thus need to # be "No_Conn" pins in the HTM NetList. # NET 'No_Conn_Trans_MP_A4' Trans_MP-A4 NET 'No_Conn_Trans_MP_B4' Trans_MP-B4 NET 'No_Conn_Trans_MP_H4' Trans_MP-H4 NET 'No_Conn_Trans_MP_J4' Trans_MP-J4 NET 'No_Conn_Trans_MP_A6' Trans_MP-A6 NET 'No_Conn_Trans_MP_B6' Trans_MP-B6 NET 'No_Conn_Trans_MP_H6' Trans_MP-H6 NET 'No_Conn_Trans_MP_J6' Trans_MP-J6 NET 'No_Conn_Trans_MP_A8' Trans_MP-A8 NET 'No_Conn_Trans_MP_B8' Trans_MP-B8 NET 'No_Conn_Trans_MP_H8' Trans_MP-H8 NET 'No_Conn_Trans_MP_J8' Trans_MP-J8 NET 'No_Conn_Trans_MP_D8' Trans_MP-D8 NET 'No_Conn_Trans_MP_D9' Trans_MP-D9 NET 'No_Conn_Trans_MP_F8' Trans_MP-F8 NET 'No_Conn_Trans_MP_F9' Trans_MP-F9 # # BULK_3V3 Supply # # HTM Net List File # --------------------- # # # Original Rev. 4-Feb-2018 # Current Rev. 5-Apr-2018 # # # # This file holds all of the nets for the # BULK_3V3 supply. # # This is a 3 Amps. # # This HTM card supply uses a LT1764A linear # regulator for this supply. # # # Connect the regulator's V_Input, V_Output, and Ground terminals: # NET 'FLTR_12V_INPUT_ONE' U101-2 NET 'BULK_3V3' U101-4 NET 'GROUND' U101-3 # # Connect the regulator's 35 Thermal Pad Vias + 4 Heatsink Vias # NET 'GROUND' U101-6 U101-7 U101-8 U101-9 U101-10 NET 'GROUND' U101-11 U101-12 U101-13 U101-14 U101-15 NET 'GROUND' U101-16 U101-17 U101-18 U101-19 U101-20 NET 'GROUND' U101-21 U101-22 U101-23 U101-24 U101-25 NET 'GROUND' U101-26 U101-27 U101-28 U101-29 U101-30 NET 'GROUND' U101-31 U101-32 U101-33 U101-34 U101-35 NET 'GROUND' U101-36 U101-37 U101-38 U101-39 U101-40 NET 'GROUND' U101-41 U101-42 U101-43 U101-44 # # Connect this regulator's Input Filter: # NET 'FLTR_12V_INPUT_ONE' C101-2 C102-2 C106-1 C107-1 NET 'GROUND' C101-1 C102-1 C106-2 C107-2 # # Connect this regulator's Output Filter: # NET 'BULK_3V3' C104-1 C105-1 DZ101-1 NET 'GROUND' C104-2 C105-2 DZ101-2 # # Connect this regulator's SHUT_DOWN_B terminal: # NET 'BULK_3V3_SHDN_B' U101-1 R101-2 NET 'FLTR_12V_INPUT_ONE' R101-1 # # Connect this regulator's SENSE_ADJUST terminal: # NET 'BULK_3V3_ADJUST' U101-5 R103-2 C103-1 NET 'BULK_3V3' R102-2 NET 'BULK_3V3_TRM_TOP' R102-1 R103-1 C103-2 NET 'BULK_3V3_TRM_BOT' R104-1 R103-3 NET 'GROUND' R104-2 # # Input Filter for Voltage Drop and High Frequency Noise # NET 'ISO_12V' R105-1 C100-2 NET 'FLTR_Step_1_ONE' R105-2 R106-1 NET 'FLTR_Step_2_ONE' R106-2 L101-1 NET 'FLTR_12V_INPUT_ONE' L101-2 NET 'GROUND' C100-1 # # BULK_2V5 Supply # # HTM Net List File # --------------------- # # # Original Rev. 26-Feb-2018 # Current Rev. 5-Apr-2018 # # # # This file holds all of the nets for the # BULK_2V5 supply. # # This is a 3 Amps. # # This HTM card supply uses a LT1764A linear # regulator for this supply. # # # Connect the regulator's V_Input, V_Output, and Ground terminals: # NET 'FLTR_12V_INPUT_TWO' U111-2 NET 'BULK_2V5' U111-4 NET 'GROUND' U111-3 # # Connect the regulator's 35 Thermal Pad Vias + 4 Heatsink Vias # NET 'GROUND' U111-6 U111-7 U111-8 U111-9 U111-10 NET 'GROUND' U111-11 U111-12 U111-13 U111-14 U111-15 NET 'GROUND' U111-16 U111-17 U111-18 U111-19 U111-20 NET 'GROUND' U111-21 U111-22 U111-23 U111-24 U111-25 NET 'GROUND' U111-26 U111-27 U111-28 U111-29 U111-30 NET 'GROUND' U111-31 U111-32 U111-33 U111-34 U111-35 NET 'GROUND' U111-36 U111-37 U111-38 U111-39 U111-40 NET 'GROUND' U111-41 U111-42 U111-43 U111-44 # # Connect this regulator's Input Filter: # NET 'FLTR_12V_INPUT_TWO' C111-2 C112-2 C116-1 C117-1 NET 'GROUND' C111-1 C112-1 C116-2 C117-2 # # Connect this regulator's Output Filter: # NET 'BULK_2V5' C114-1 C115-1 DZ111-1 NET 'GROUND' C114-2 C115-2 DZ111-2 # # Connect this regulator's SHUT_DOWN_B terminal: # NET 'BULK_2V5_SHDN_B' U111-1 R111-2 NET 'FLTR_12V_INPUT_TWO' R111-1 # # Connect this regulator's SENSE_ADJUST terminal: # NET 'BULK_2V5_ADJUST' U111-5 R113-2 C113-1 NET 'BULK_2V5' R112-2 NET 'BULK_2V5_TRM_TOP' R112-1 R113-1 C113-2 NET 'BULK_2V5_TRM_BOT' R114-1 R113-3 NET 'GROUND' R114-2 # # Input Filter for Voltage Drop and High Frequency Noise # NET 'ISO_12V' R115-1 C110-2 NET 'FLTR_Step_1_TWO' R115-2 R116-1 NET 'FLTR_Step_2_TWO' R116-2 L111-1 NET 'FLTR_12V_INPUT_TWO' L111-2 NET 'GROUND' C110-1 # # HTM Card Net List File # # FPGA Vcco Power Nets # ----------------------- # # # Initial Rev. 27-Feb-2018 # Current Rev. 28-Feb-2018 # # # This file holds all of the nets associated with # supplying Vcco power to the various FPGA Banks. # # Many of the Select I/O Banks on the FPGA Mezz card # have fixed Vcco supplies right on that card. # # The 6 FPGA Banks that provide the Select I/O signals # that come off of the FPGA Mezz card have their Vcco # pins routed to pins on the Mezz card's J1, J2, J3 # connectors. # # I believe that these Vcco connections are: # # Vcco Pins # ----------------- # # Banks: 10 J3-99 J3-100 3.3 Volt max # 11 J3-159 J3-160 I/O Banks # 12 J2-159 J2-160 # 13 J2-99 J2-100 # # # Banks: 33 J1-99 J1-100 1.8 Volt max # 34 J1-159 J1-160 I/O Banks # # # The intent is to power Banks 10,11,12,13 from # the 3.3 Volt power that is provided by the FPGA # Mezz card, net MEZZ_3V3.# # # The intent is to power Banks 33,34 from # the 1.8 Volt power that is provided by the # FPGA Mezz card, net MEZZ_1V8. # # # The connections to the Vcco pins for this 6 # FPGA Select I/O Banks will include bypass # capacitors on the HTM card (along with more # bypass capacitors on the FPGA Mezz card. # # # # Supply to 3.3V Select I/O Banks # NET 'Mezz_3V3' J3-99 J3-100 # Bank 10 Vcco NET 'Mezz_3V3' J3-159 J3-160 # Bank 11 Vcco NET 'Mezz_3V3' J2-159 J2-160 # Bank 12 Vcco NET 'Mezz_3V3' J2-99 J2-100 # Bank 13 Vcco # # Distributed ByPass Caps on the Mezz_3V3 Bus # NET 'Mezz_3V3' C80-1 C79-1 C78-1 C77-1 NET 'GROUND' C80-2 C79-2 C78-2 C77-2 # # Supply to 1.8V Select I/O Banks # NET 'Mezz_1V8' J1-99 J1-100 # Bank 33 Vcco NET 'Mezz_1V8' J1-159 J1-160 # Bank 34 Vcco # # Distributed ByPass Caps on the Mezz_1V8 Bus # NET 'Mezz_1V8' C76-1 C75-1 C74-1 C73-1 NET 'GROUND' C76-2 C75-2 C74-2 C73-2 # # HTM Card Net List File # # Distributed ByPass Capacitor Nets # ------------------------------------ # # # Initial Rev. 28-Feb-2018 # Current Rev. 28-Mar-2018 # # # This file holds all of the nets associated with # Distributed ByPass Capacitors for the power nets: # # ISO_12V BULK_3V3 BULK_2V5 # # # # For the ISO_12V power net. # NET 'ISO_12V' C99-1 C98-1 C97-1 C96-1 NET 'GROUND' C99-2 C98-2 C97-2 C96-2 NET 'ISO_12V' C95-1 C94-1 C93-1 C92-1 NET 'GROUND' C95-2 C94-2 C93-2 C92-2 NET 'ISO_12V' C91-1 C90-1 NET 'GROUND' C91-2 C90-2 # # For the BULK_3V3 power net. # NET 'BULK_3V3' C89-1 C88-1 C87-1 C86-1 NET 'GROUND' C89-2 C88-2 C87-2 C86-2 NET 'BULK_3V3' C85-1 C84-1 C83-1 C82-1 NET 'GROUND' C85-2 C84-2 C83-2 C82-2 # # For the BULK_2V5 power net. # NET 'BULK_2V5' C69-1 C68-1 C67-1 C66-1 NET 'GROUND' C69-2 C68-2 C67-2 C66-2 # # HTM Card Net List File # # Monitor Connector J11 Nets # ------------------------------ # # # Initial Rev. 2-Mar-2018 # Current Rev. 3-Apr-2018 # # # This file holds all of the Power Supply Monitoring nets # associated with Connector J11. # # # Starting at the low pin number end of the J11 # connector we have 5 power supply Voltage Monitor # connections. # NET 'ISO_12V' R501-1 NET 'BULK_3V3' R502-1 NET 'BULK_2V5' R503-1 NET 'MEZZ_3V3' R504-1 NET 'MEZZ_1V8' R505-1 NET 'ISO_12V_Monitor_Point' J11-1 R501-2 C501-1 NET 'BULK_3V3_Monitor_Point' J11-3 R502-2 C502-1 NET 'BULK_2V5_Monitor_Point' J11-5 R503-2 C503-1 NET 'MEZZ_3V3_Monitor_Point' J11-7 R504-2 C504-1 NET 'MEZZ_1V8_Monitor_Point' J11-9 R505-2 C505-1 NET 'GROUND' C501-2 C502-2 C503-2 C504-2 C505-2 NET 'GROUND' J11-2 J11-4 J11-6 J11-8 J11-10 # # HTM Card Net List File # # Life Boat Signal Nets # ------------------------- # # # Initial Rev. 3-Apr-2018 # Current Rev. 4-Apr-2018 # # # This file holds all of the Life Boat Signal nets. # # Most of the Life Boat nets on the HTM Card are # associated with the connector J11 which also # handles the power supply monitoring connections. # # # The Life Boat Signals include: # # The CPLD JTAG connection including Bulk_3V3 # power for this JTAG connection # # CPLD GPIO_3 # CPLD GPIO_4 # CPLD GPIO_5 # # JTAGENB for the CPLD JTAG Connection # BOOTMODE # RESIN Reset Input # CONFIGX Configure_X # VBAT_IN Backup Battery Input for Realtime Clock and FPGA Key # # Four FPGA Select I/O signals routed to the J11 connector # # # # At the high pin number end of the J11 # connector we have the CPLD JTAG nets # including some limited Bulk_3V3 power. # NET 'CPLD_M_TMS' J3-82 J11-16 NET 'CPLD_M_TCK' J3-81 J11-18 NET 'CPLD_M_TDO' J3-88 J11-20 NET 'CPLD_M_TDI' J3-87 J11-22 NET 'GROUND' J11-13 J11-15 J11-17 J11-19 J11-21 NET 'BULK_3V3' R509-1 NET 'CPLD_M_JTAG_POWER' R509-2 J11-14 # # Nets for the following 8 Life Boat Signals: # # CPLD GPIO_3 NET 'LB_CPLD_GPIO_3' J2-16 WTERM21-1 J11-40 R510-1 R511-1 # CPLD GPIO_4 NET 'LB_CPLD_GPIO_4' J2-18 WTERM22-1 J11-38 R520-1 R521-1 # CPLD GPIO_5 NET 'LB_CPLD_GPIO_5' J2-20 WTERM23-1 J11-36 R530-1 R531-1 # JTAGENB for the CPLD JTAG Connection NET 'LB_JTAGENB' J3-136 WTERM24-1 J11-34 R540-1 R541-1 # BOOTMODE NET 'LB_BOOTMODE' J3-135 WTERM25-1 J11-32 R550-1 R551-1 # RESIN Reset Input NET 'LB_RESIN' J3-130 WTERM26-1 J11-30 R560-1 R561-1 # CONFIGX Configure_X NET 'LB_CONFIGX' J3-129 WTERM27-1 J11-28 R570-1 R571-1 # VBAT_IN Backup Battery Input for Realtime Clock and FPGA Key NET 'LB_VBAT_IN' J3-124 WTERM28-1 J11-26 R580-1 R581-1 # # Connect the Pull-Up and Pull_Down Resistors # for these 8 Life Boat Signals to Bulk_3V3 # and Ground. # NET 'BULK_3V3' R510-2 R520-2 R530-2 R540-2 NET 'GROUND' R511-2 R521-2 R531-2 R541-2 NET 'BULK_3V3' R550-2 R560-2 R570-2 R580-2 NET 'GROUND' R551-2 R561-2 R571-2 R581-2 # # Connect 4 Select I/O lines from the FPGA # to the J11 Connector as Life Boats. # NET 'LB_FPGA_Sel_IO_1' J3-107 J11-25 WTERM31-1 NET 'LB_FPGA_Sel_IO_2' J3-113 J11-29 WTERM32-1 NET 'LB_FPGA_Sel_IO_3' J3-119 J11-33 WTERM33-1 NET 'LB_FPGA_Sel_IO_4' J3-125 J11-37 WTERM34-1 NET 'GROUND' J11-39 J11-35 J11-31 J11-27 # # FPGA Mezz No Conn Net List File # # FPGA Mezzanine J1, J2, and J3 No Connection Nets # ----------------------------------------------------- # # Initial Rev. 02-Apr-2018 # Current Rev. 06-Apr-2018 # # Contains nets for pins of J1, J2, and J3 which remain unconnected # to anything. # # J1 No Connection Nets # NET 'No_Conn_AC4_MGT_RX8_P' J1-1 NET 'No_Conn_AC3_MGT_RX8_N' J1-3 NET 'No_Conn_F3_J1_TX20_N' J1-33 NET 'No_Conn_F4_J1_TX20_P' J1-35 NET 'No_Conn_K6_J1_TX21_N' J1-37 NET 'No_Conn_J6_J1_TX21_P' J1-39 NET 'No_Conn_J1_J1_TX0_P' J1-41 NET 'No_Conn_H1_J1_TX0_N' J1-43 NET 'No_Conn_L4_J1_B33_VRP' J1-45 NET 'No_Conn_H2_J1_TX1_P' J1-47 NET 'No_Conn_G1_J1_TX1_N' J1-49 NET 'No_Conn_G2_J1_TX2_P' J1-53 NET 'No_Conn_F2_J1_TX2_N' J1-55 NET 'No_Conn_E3_J1_TX3_P' J1-59 NET 'No_Conn_E2_J1_TX3_N' J1-61 NET 'No_Conn_E1_J1_TX4_P' J1-65 NET 'No_Conn_D1_J1_TX4_N' J1-67 NET 'No_Conn_C2_J1_TX5_P' J1-71 NET 'No_Conn_C1_J1_TX5_N' J1-73 NET 'No_Conn_B2_J1_TX6_P' J1-77 NET 'No_Conn_B1_J1_TX6_N' J1-79 NET 'No_Conn_E6_J1_TX7_P' J1-83 NET 'No_Conn_D5_J1_TX7_N' J1-85 NET 'No_Conn_A3_J1_TX8_P' J1-89 NET 'No_Conn_A2_J1_TX8_N' J1-91 NET 'No_Conn_H4_J1_TX9_P' J1-95 NET 'No_Conn_H3_J1_TX9_N' J1-97 NET 'No_Conn_E7_J1_TX10_P' J1-101 NET 'No_Conn_D6_J1_TX10_N' J1-103 NET 'No_Conn_M10_J1_B34_VRP' J1-105 NET 'No_Conn_F8_J1_TX11_P' J1-107 NET 'No_Conn_F7_J1_TX11_N' J1-109 NET 'No_Conn_C7_J1_TX12_P' J1-113 NET 'No_Conn_B7_J1_TX12_N' J1-115 NET 'No_Conn_J8_J1_TX13_P' J1-119 NET 'No_Conn_H8_J1_TX13_N' J1-121 NET 'No_Conn_B9_J1_TX14_P' J1-125 NET 'No_Conn_A9_J1_TX14_N' J1-127 NET 'No_Conn_B10_J1_TX15_P' J1-131 NET 'No_Conn_A10_J1_TX15_N' J1-133 NET 'No_Conn_E10_J1_TX16_P' J1-137 NET 'No_Conn_D10_J1_TX16_N' J1-139 NET 'No_Conn_K11_J1_TX17_P' J1-143 NET 'No_Conn_K10_J1_TX17_N' J1-145 NET 'No_Conn_F9_J1_TX18_P' J1-149 NET 'No_Conn_E8_J1_TX18_N' J1-151 NET 'No_Conn_G10_J1_TX19_P' J1-155 NET 'No_Conn_F10_J1_TX19_N' J1-157 NET 'No_Conn_E5_J1_RX20_N' J1-34 NET 'No_Conn_F5_J1_RX20_P' J1-36 NET 'No_Conn_U7_MGT_CLK4_P' J1-38 NET 'No_Conn_U8_MGT_CLK4_N' J1-40 NET 'No_Conn_L3_J1_RX0_P' J1-42 NET 'No_Conn_L2_J1_RX0_N' J1-44 NET 'No_Conn_L5_J1_B33_VRN' J1-46 NET 'No_Conn_L1_J1_RX1_P' J1-48 NET 'No_Conn_K1_J1_RX1_N' J1-50 NET 'No_Conn_K3_J1_RX2_P' J1-54 NET 'No_Conn_K2_J1_RX2_N' J1-56 NET 'No_Conn_H6_J1_RX3_P' J1-60 NET 'No_Conn_G6_J1_RX3_N' J1-62 NET 'No_Conn_K5_J1_RX4_P' J1-66 NET 'No_Conn_J5_J1_RX4_N' J1-68 NET 'No_Conn_J4_J1_RX5_P' J1-72 NET 'No_Conn_J3_J1_RX5_N' J1-74 NET 'No_Conn_D4_J1_RX6_P' J1-78 NET 'No_Conn_D3_J1_RX6_N' J1-80 NET 'No_Conn_B5_J1_RX7_P' J1-84 NET 'No_Conn_B4_J1_RX7_N' J1-86 NET 'No_Conn_A5_J1_RX8_P' J1-90 NET 'No_Conn_A4_J1_RX8_N' J1-92 NET 'No_Conn_G5_J1_RX9_P' J1-96 NET 'No_Conn_G4_J1_RX9_N' J1-98 NET 'No_Conn_L8_J1_RX10_P' J1-102 NET 'No_Conn_K8_J1_RX10_N' J1-104 NET 'No_Conn_M12_J1_B34_VRN' J1-106 NET 'No_Conn_L10_J1_RX11_P' J1-108 NET 'No_Conn_L9_J1_RX11_N' J1-110 NET 'No_Conn_L12_J1_RX12_P' J1-114 NET 'No_Conn_K12_J1_RX12_N' J1-116 NET 'No_Conn_H7_J1_RX13_P' J1-120 NET 'No_Conn_G7_J1_RX13_N' J1-122 NET 'No_Conn_J10_J1_RX14_P' J1-126 NET 'No_Conn_J9_J1_RX14_N' J1-128 NET 'No_Conn_C6_J1_RX15_P' J1-132 NET 'No_Conn_B6_J1_RX15_N' J1-134 NET 'No_Conn_J11_J1_RX16_P' J1-138 NET 'No_Conn_H11_J1_RX16_N' J1-140 NET 'No_Conn_H12_J1_RX17_P' J1-144 NET 'No_Conn_G11_J1_RX17_N' J1-146 NET 'No_Conn_E11_J1_RX18_P' J1-150 NET 'No_Conn_D11_J1_RX18_N' J1-152 NET 'No_Conn_D9_J1_RX19_P' J1-156 NET 'No_Conn_D8_J1_RX19_N' J1-158 # # J2 No Connection Nets # NET 'No_Conn_J2_NC_Pin_1' J2-1 NET 'No_Conn_J2_NC_Pin_3' J2-3 NET 'No_Conn_J2_NC_Pin_5' J2-5 NET 'No_Conn_J2_NC_Pin_7' J2-7 NET 'No_Conn_N29_J2_TX0_P' J2-41 NET 'No_Conn_P29_J2_TX0_N' J2-43 NET 'No_Conn_U22_J2_TX1_P' J2-47 NET 'No_Conn_V22_J2_TX1_N' J2-49 NET 'No_Conn_J2_NC_Pin_51' J2-51 NET 'No_Conn_R30_J2_TX2_N' J2-55 NET 'No_Conn_J2_NC_Pin_57' J2-57 NET 'No_Conn_V23_J2_TX3_P' J2-59 NET 'No_Conn_W24_J2_TX3_N' J2-61 NET 'No_Conn_J2_NC_Pin_63' J2-63 NET 'No_Conn_T30_J2_TX4_P' J2-65 NET 'No_Conn_U30_J2_TX4_N' J2-67 NET 'No_Conn_J2_NC_Pin_69' J2-69 NET 'No_Conn_W25_J2_TX5_P' J2-71 NET 'No_Conn_W26_J2_TX5_N' J2-73 NET 'No_Conn_J2_NC_Pin_75' J2-75 NET 'No_Conn_V28_J2_TX6_P' J2-77 NET 'No_Conn_V29_J2_TX6_N' J2-79 NET 'No_Conn_J2_NC_Pin_81' J2-81 NET 'No_Conn_T29_J2_TX7_P' J2-83 NET 'No_Conn_U29_J2_TX7_N' J2-85 NET 'No_Conn_J2_NC_Pin_87' J2-87 NET 'No_Conn_W29_J2_TX8_P' J2-89 NET 'No_Conn_W30_J2_TX8_N' J2-91 NET 'No_Conn_U25_J2_TX9_P' J2-95 NET 'No_Conn_V26_J2_TX9_N' J2-97 NET 'No_Conn_AA27_J2_TX10_P' J2-101 NET 'No_Conn_AA28_J2_TX10_N' J2-103 NET 'No_Conn_AC29_J2_TX11_P' J2-107 NET 'No_Conn_AD29_J2_TX11_N' J2-109 NET 'No_Conn_AE25_J2_TX12_P' J2-113 NET 'No_Conn_AF25_J2_TX12_N' J2-115 NET 'No_Conn_AD30_J2_TX13_P' J2-119 NET 'No_Conn_AE30_J2_TX13_N' J2-121 NET 'No_Conn_AF29_J2_TX14_P' J2-125 NET 'No_Conn_AG29_J2_TX14_N' J2-127 NET 'No_Conn_AF30_J2_TX15_P' J2-131 NET 'No_Conn_AG30_J2_TX15_N' J2-133 NET 'No_Conn_AH26_J2_TX16_P' J2-137 NET 'No_Conn_AH27_J2_TX16_N' J2-139 NET 'No_Conn_AJ30_J2_TX17_P' J2-143 NET 'No_Conn_AK30_J2_TX17_N' J2-145 NET 'No_Conn_AK27_J2_TX18_P' J2-149 NET 'No_Conn_AK28_J2_TX18_N' J2-151 NET 'No_Conn_AB27_J2_TX19_P' J2-155 NET 'No_Conn_AC27_J2_TX19_N' J2-157 NET 'No_Conn_J2_TEMP_DCDC1' J2-2 NET 'No_Conn_J2_TEMP_DCDC2' J2-4 NET 'No_Conn_J2_TEMP_PCB' J2-6 NET 'No_Conn_J2_TEMP_ZYNQ' J2-8 NET 'No_Conn_J2_TEMP_GPI00' J2-10 NET 'No_Conn_J2_TEMP_GPI01' J2-12 NET 'No_Conn_J2_TEMP_GPI02' J2-14 NET 'No_Conn_J2_OTG2_ID' J2-22 NET 'No_Conn_J2_USB2_VBUS' J2-24 NET 'No_Conn_J2_USB2_D_N' J2-26 NET 'No_Conn_J2_USB2_D_P' J2-28 NET 'No_Conn_J2_VBUS2_V_EN' J2-30 NET 'No_Conn_J2_VBUS1_V_EN' J2-32 NET 'No_Conn_J2_OTG1_ID' J2-34 NET 'No_Conn_J2_USB1_VBUS' J2-36 NET 'No_Conn_J2_USB1_D_N' J2-38 NET 'No_Conn_J2_USB1_D_P' J2-40 NET 'No_Conn_P25_J2_RX0_P' J2-42 NET 'No_Conn_P26_J2_RX0_N' J2-44 NET 'No_Conn_N27_J2_RX1_N' J2-50 NET 'No_Conn_P28_J2_RX2_N' J2-56 NET 'No_Conn_P24_J2_RX3_N' J2-62 NET 'No_Conn_T25_J2_RX4_N' J2-68 NET 'No_Conn_R23_J2_RX5_N' J2-74 NET 'No_Conn_V24_J2_RX6_N' J2-80 NET 'No_Conn_T23_J2_RX7_N' J2-86 NET 'No_Conn_V27_J2_RX8_N' J2-92 NET 'No_Conn_U26_J2_RX9_P' J2-96 NET 'No_Conn_U27_J2_RX9_N' J2-98 NET 'No_Conn_Y26_J2_RX10_P' J2-102 NET 'No_Conn_Y27_J2_RX10_N' J2-104 NET 'No_Conn_AA29_J2_RX11_N' J2-110 NET 'No_Conn_AA30_J2_RX12_N' J2-116 NET 'No_Conn_AD26_J2_RX13_N' J2-122 NET 'No_Conn_AB30_J2_RX14_N' J2-128 NET 'No_Conn_AE26_J2_RX15_N' J2-134 NET 'No_Conn_AG27_J2_RX16_N' J2-140 NET 'No_Conn_AJ29_J2_RX17_N' J2-146 NET 'No_Conn_AK26_J2_RX18_N' J2-152 # # J3 No Connection Nets # NET 'No_Conn_AF13_J3_TX20_P' J3-33 NET 'No_Conn_AE13_J3_TX20_N' J3-35 NET 'No_Conn_AC7_J3_MGT_CLK1_P' J3-37 NET 'No_Conn_AC8_J3_MGT_CLK1_N' J3-39 NET 'No_Conn_AD13_J3_TX1_N' J3-49 NET 'No_Conn_AH12_J3_TX2_N' J3-55 NET 'No_Conn_AC12_J3_TX3_N' J3-61 NET 'No_Conn_AA14_J3_TX4_N' J3-67 NET 'No_Conn_AH13_J3_TX5_N' J3-73 NET 'No_Conn_AE15_J3_TX6_N' J3-79 NET 'No_Conn_AB14_J3_TX7_N' J3-85 NET 'No_Conn_AC16_J3_TX8_N' J3-91 NET 'No_Conn_AF15_J3_TX21_P' J3-95 NET 'No_Conn_AG15_J3_TX21_N' J3-97 NET 'No_Conn_AK18_J3_TX10_N' J3-103 NET 'No_Conn_AK23_J3_TX11_N' J3-109 NET 'No_Conn_AK20_J3_TX12_N' J3-115 NET 'No_Conn_AK21_J3_TX13_N' J3-121 NET 'No_Conn_AJ19_J3_TX14_N' J3-127 NET 'No_Conn_AF19_J3_TX15_P' J3-131 NET 'No_Conn_AG19_J3_TX15_N' J3-133 NET 'No_Conn_AF23_J3_TX16_P' J3-137 NET 'No_Conn_AF24_J3_TX16_N' J3-139 NET 'No_Conn_AH23_J3_TX17_P' J3-143 NET 'No_Conn_AH24_J3_TX17_N' J3-145 NET 'No_Conn_AC24_J3_TX18_P' J3-149 NET 'No_Conn_AD24_J3_TX18_N' J3-151 NET 'No_Conn_AD23_J3_TX19_P' J3-155 NET 'No_Conn_AE23_J3_TX19_N' J3-157 NET 'No_Conn_AD5_J3_MGT_RX7_N' J3-2 NET 'No_Conn_AD6_J3_MGT_RX7_P' J3-4 NET 'No_Conn_AG14_J3_MGT_RX6_N' J3-34 NET 'No_Conn_AF14_J3_MGT_RX6_P' J3-36 NET 'No_Conn_AJ15_J3_RX0_P' J3-42 NET 'No_Conn_AK15_J3_RX0_N' J3-44 NET 'No_Conn_AJ13_J3_RX1_N' J3-50 NET 'No_Conn_AK12_J3_RX2_N' J3-56 NET 'No_Conn_AK16_J3_RX3_N' J3-62 NET 'No_Conn_AF17_J3_RX4_N' J3-68 NET 'No_Conn_J3_NC_Pin_76' J3-76 NET 'No_Conn_AE18_J3_RX7_P' J3-84 NET 'No_Conn_AE17_J3_RX7_N' J3-86 NET 'No_Conn_AB16_J3_RX8_P' J3-90 NET 'No_Conn_AB17_J3_RX8_N' J3-92 NET 'No_Conn_AG17_J3_RX21_P' J3-96 NET 'No_Conn_AG16_J3_RX21_N' J3-98 NET 'No_Conn_AJ23_J3_RX10_P' J3-102 NET 'No_Conn_AJ24_J3_RX10_N' J3-104 NET 'No_Conn_AJ25_J3_RX11_P' J3-108 NET 'No_Conn_AK25_J3_RX11_N' J3-110 NET 'No_Conn_AG24_J3_RX12_P' J3-114 NET 'No_Conn_AG25_J3_RX12_N' J3-116 NET 'No_Conn_AC22_J3_RX13_P' J3-120 NET 'No_Conn_AC23_J3_RX13_N' J3-122 NET 'No_Conn_AD21_J3_RX14_P' J3-126 NET 'No_Conn_AE21_J3_RX14_N' J3-128 NET 'No_Conn_AA22_J3_RX15_P' J3-132 NET 'No_Conn_AA23_J3_RX15_N' J3-134 NET 'No_Conn_Y22_J3_RX16_P' J3-138 NET 'No_Conn_Y23_J3_RX16_N' J3-140 NET 'No_Conn_AA24_J3_RX17_P' J3-144 NET 'No_Conn_AB24_J3_RX17_N' J3-146 NET 'No_Conn_W21_J3_RX18_P' J3-150 NET 'No_Conn_Y21_J3_RX18_N' J3-152 # # Sundry HTM-0 Nets # # HTM-0 Key-In Net List File # # # Original Rev. 31-Jan-2018 # Current Rev. 12-Apr-2018 # # # # # Currently this Sundry Net List file contains: # # - Ground the FPGA Mezzanine Mounting Screw Holes # # - Ground the Ground Rivets and the Scope Loops # # - Shield Fill Resistor for the Iso_12V Power Supply # # # # # # Ground the FPGA Mezzanine Mounting Screw Holes # NET 'GROUND' FPGA_MEZZ-1 FPGA_MEZZ-2 NET 'GROUND' FPGA_MEZZ-3 FPGA_MEZZ-4 # # Ground the: Perimeter Rivets # Rivets Adjacent to High-Speed Traces # NET 'GROUND' GR1-1 GR2-1 GR3-1 GR4-1 GR5-1 NET 'GROUND' GR6-1 GR7-1 GR8-1 GR9-1 GR10-1 NET 'GROUND' GR11-1 GR12-1 GR13-1 GR14-1 GR15-1 NET 'GROUND' GR16-1 NET 'GROUND' GR21-1 GR22-1 GR23-1 GR24-1 GR25-1 NET 'GROUND' GR26-1 GR27-1 GR28-1 GR29-1 GR30-1 NET 'GROUND' GR41-1 GR42-1 GR43-1 GR44-1 GR45-1 NET 'GROUND' GR46-1 GR47-1 GR48-1 NET 'GROUND' GR51-1 GR52-1 GR53-1 GR54-1 GR55-1 NET 'GROUND' GR56-1 GR57-1 GR58-1 GR59-1 GR60-1 NET 'GROUND' GR61-1 GR62-1 NET 'GROUND' GR71-1 GR72-1 GR73-1 GR74-1 GR75-1 NET 'GROUND' GR76-1 GR77-1 GR78-1 GR79-1 GR80-1 NET 'GROUND' GR81-1 GR82-1 GR83-1 NET 'GROUND' GR91-1 GR92-1 GR93-1 GR94-1 GR95-1 NET 'GROUND' GR96-1 GR97-1 GR98-1 GR99-1 GR100-1 NET 'GROUND' GR101-1 GR102-1 GR103-1 GR104-1 GR105-1 NET 'GROUND' GR111-1 GR112-1 GR113-1 GR114-1 GR115-1 NET 'GROUND' GR116-1 GR117-1 NET 'GROUND' GR121-1 GR122-1 GR123-1 GR124-1 GR125-1 NET 'GROUND' GR126-1 # # Ground the: Scope Loops # NET 'GROUND' WTERM1-1 WTERM2-1 NET 'GROUND' WTERM3-1 WTERM4-1 # # Shield Fill for the Iso_12V Power Supply # NET 'SHIELD_ATCA_12V_MODULE' R961-1 NET 'GROUND' R961-2