# # HTM Card Net List File # # Clock Generation and Associated Nets # ----------------------------------------- # # # Initial Rev. 4-Feb-2018 # Current Rev. 23-Apr-2018 # # # This file holds all of the nets associated with the # Clock Generation on the HTM circuit board and # associated circuits such as Spare Crystal Oscillator # and Buffers. # # # Note that all differential pairs in this section are # wired right-side-up except for the Ref Clk feed to the # Si Labs chip on the FPGA Mezz. # # The Ref Clk feed to the Si Labs chip on the FPGA Mezz will # appear to be wired up-side-down because of the way that # they designed the FPGA Mezz card, i.e. they have a flip # in their naming, e.g. FPGA Mezz pin J3-40 is labeled # Si5328_Clk1_N but it goes to pin #1 of the Si5338 # which is its non-inverting Ref Clk input. # # To help keep things straight I put all the chip pin # number pin name information here: # # CDC LVD 1204 # # In 0 Dir pin 6 In 1 Dir pin 3 # In 0 Cmp pin 7 In 1 Cmp pin 4 # # Out 0 Dir pin 9 Out 1 Dir pin 11 # Out 0 Cmp pin 10 Out 1 Cmp pin 12 # # Out 2 Dir pin 13 Out 3 Dir pin 15 # Out 2 Cmp pin 14 Out 3 Cmp pin 16 # # 65 LVDS 2 # # In Dir pin 3 Out pin 5 # In Cmp pin 4 Vcc pin 1 Gnd pin 2 # # SFX-524G-CRN1 PLL # # Output_Dir U253-6 # Output_Cmp U253-7 # # Logic Clk feed to the FPGA 40.08 MHz via FPGA Mezz card # # J3-156 goes to FPGA pin AE22 which is IO_L12P_T1_MRCC_11 # J3-158 goes to FPGA pin AF22 which is IO_L12N_T1_MRCC_11 # # Si Labs 5338 Ref Clk feed 40.08 MHz via FPGA Mezz card # # J3-38 Si5328_Clk1_P U2-2 IN2 Cmp # J3-40 Si5328_Clk1_N U2-1 IN1 Dir # # # # Generation of the 40.0787 MHz Clock on the HTM # # # Receive the Hub #1 LHC Reference Clock # NET 'Hub_1_Ref_Clk_Dir' J23-C4 R261-1 U252-3 NET 'Hub_1_Ref_Clk_Cmp' J23-D4 R262-1 U252-4 NET 'Hub_1_Ref_Clk_CMM' R261-2 R262-2 R263-2 R264-2 C254-1 NET 'CLK_3V3' U252-1 C253-1 R263-1 NET 'GROUND' U252-2 C253-2 R264-1 C254-2 NET 'Recvd_Hub_1_Ref_Clk' U252-5 R265-1 # # 40.0787 MHz PLL # NET 'Bk_Trm_Rcvd_Hub_1_Ref_Clk' R265-2 U253-1 NET 'PLL_40_Clk_Out_Dir' U253-6 R266-1 NET 'PLL_40_Clk_Out_Cmp' U253-7 R267-1 NET 'RC_PLL_40_Clk_Out_Dir' R266-2 C256-1 NET 'RC_PLL_40_Clk_Out_Cmp' R267-2 C257-1 NET 'Raw_PLL_40_MHz_Locked' U253-10 R268-1 NET 'PLL_40_MHz_Locked_Mon' J3-101 R268-2 NET 'CLK_3V3' U253-9 C258-1 C259-1 C260-1 NET 'GROUND' U253-2 U253-8 NET 'GROUND' C258-2 C259-2 C260-2 NET 'No_Conn_PLL_pin_3' U253-3 NET 'No_Conn_PLL_pin_4' U253-4 NET 'No_Conn_PLL_pin_5' U253-5 # # 40.0787 MHz 4x Buffer FanOut # NET 'PLL_40_MHz_Signal_Dir' C256-2 U254-6 R271-1 NET 'PLL_40_MHz_Signal_Cmp' C257-2 U254-7 R272-1 NET 'FanOut_Input_CMM_Ref' U254-8 U254-4 R271-2 R272-2 C255-1 NET 'GROUND' U254-1 C255-2 NET 'GROUND' U254-17 U254-18 U254-19 U254-20 NET 'CLK_2V5' U254-5 C262-1 C263-1 NET 'GROUND' C262-2 C263-2 NET 'Fan_40_MHz_In_Sel' U254-2 R273-1 NET 'Fan_40_MHz_In_2_Bias' U254-3 R274-1 NET 'GROUND' R273-2 R274-2 NET 'No_Conn_Clk_Fanout_9' U254-9 NET 'No_Conn_Clk_Fanout_10' U254-10 # # 40.0787 MHz FanOut Feed to FPGA Global Logic Clock # # The 40.08 MHz Logic Clock goes to the FPGA Mezz on # its pins J3-156 & J3-158. These connect to # FPGA pins AE22 & AF22 which are IO_L12P_T1_MRCC_11 # and IO_L12N_T1_MRCC_11 Bank #11 Multi Region # 3V3 Clock Inputs to the FPGA. # NET 'Pre_Cap_FPGA_40_MHz_Logic_Clk_Dir' U254-13 C266-1 NET 'Pre_Cap_FPGA_40_MHz_Logic_Clk_Cmp' U254-14 C267-1 NET 'FPGA_40_MHz_Logic_Clk_Dir' C266-2 J3-156 NET 'FPGA_40_MHz_Logic_Clk_Cmp' C267-2 J3-158 # # 40.0787 MHz FanOut Feed to SiLab 5338A # # Note that based on the FPGA Mezz card's pin names # there would appear to be a polarity flip but there # is not one. The Dir output from the Fanout chip # goes to the Reference Dir input on the Si Labs Si5338. # # FPGA Mezz pin J3-40 goes to the Ref Dir input on Si5338. # NET 'Pre_Cap_40_MHz_SiLab_Dir' U254-15 R275-1 C264-1 NET 'Pre_Cap_40_MHz_SiLab_Cmp' U254-16 R275-2 C265-1 NET 'Ref_40_MHz_to_SiLab_Dir' C264-2 J3-40 NET 'Ref_40_MHz_to_SiLab_Cmp' C265-2 J3-38 # # 40.0787 MHz FanOut Feed to Front Panel Monitor Buffer # NET 'Mon_Cp_40_Clk_Dir' U254-11 NET 'Mon_Cp_40_Clk_Cmp' U254-12 # # Buffered Copy of the HTM's 40.0787 MHz Clock # for Front Panel Monitoring # NET 'Mon_Cp_40_Clk_Dir' U255-3 R276-1 NET 'Mon_Cp_40_Clk_Cmp' U255-4 R276-2 NET 'BULK_3V3' U255-1 C268-1 NET 'GROUND' U255-2 C268-2 NET 'Bufd_Mon_40_Clk' U255-5 R277-1 NET 'FP_Mon_40_Clk_Hub_1' R277-2 J15-5 NET 'GROUND' J15-1 J15-2 J15-3 J15-4 # # Receive the Hub #2 LHC Reference Clock Just for Monitoring # NET 'Hub_2_Ref_Clk_Dir' J23-C2 R251-1 U251-3 NET 'Hub_2_Ref_Clk_Cmp' J23-D2 R252-1 U251-4 NET 'Hub_2_Ref_Clk_CMM' R251-2 R252-2 R253-2 R254-2 C252-1 NET 'BULK_3V3' U251-1 C251-1 R253-1 NET 'GROUND' U251-2 C251-2 R254-1 C252-2 NET 'Recvd_Hub_2_Ref_Clk' U251-5 R255-1 R256-1 NET 'Hub_2_Ref_Mon_to_FP' R255-2 J16-5 NET 'GROUND' J16-1 J16-2 J16-3 J16-4 NET 'Hub_2_Ref_Mon_to_FPGA' R256-2 J2-53 # # Spare LVDS Output Crystal Oscillator # # The Spare Clock goes to the FPGA Mezz on # its pins J2-156 & J2-158. These connect to # FPGA pins AC28 & AD28 which are IO_L12P_T1_MRCC_12 # and IO_L12N_T1_MRCC_12 Bank #12 Multi Region # 3V3 Clock Inputs to the FPGA. # NET 'Xtal_Osc_1_to_Cap_Dir' U256-4 C271-1 NET 'Xtal_Osc_1_to_Cap_Cmp' U256-5 C272-1 NET 'Spare_Osc_to_FPGA_Dir' C271-2 J2-156 NET 'Spare_Osc_to_FPGA_Cmp' C272-2 J2-158 NET 'CLK_3V3' U256-6 C269-2 C270-2 NET 'GROUND' U256-3 C269-1 C270-1 Net 'NO_CONN_U271_Pin_1' U256-1 Net 'NO_CONN_U271_Pin_2' U256-2 # # CLK_3V3 Power Filter for the Clock Generation, # Buffers, Crystal Oscillator, and associated components # NET 'BULK_3V3' C275-1 L251-2 NET 'CLK_3V3' L251-1 C276-1 C277-1 C261-1 NET 'GROUND' C275-2 C276-2 C277-2 C261-2 # # CLK_2V5 Power Filter for the 40.08 MHz Clock # LVDS Fanout Buffer U254 # NET 'BULK_2V5' C281-1 L281-2 NET 'CLK_2V5' L281-1 C282-1 NET 'GROUND' C281-2 C282-2