#
#                HTM Card  Net List File
#
#            JTAG and all Associated J12 Nets
#         ----------------------------------
#
#
#                                     Initial  Rev.   4-Feb-2018
#                                     Current  Rev.   7-Apr-2018
#
#
#   This file holds all of the nets associated with the
#   JTAG circuit  and  the Front Panel Access Signals
#   on the HTM card,  that is all signals associated with
#   the  J12  Front Panel "Access Connector".
#
#
#
#   Recall the pinout of the  Front Panel  J12  connector on HTM:
#
#      Pin     Function
#      ---    ---------------
#
#       1      Ground
#       2      3V3 JTAG  Power
#       3      Ground
#       4      TMS       Input
#       5      Ground
#       6      TCK       Input
#       7      Ground
#       8      TDO       Output
#       9      Ground
#      10      TDI       Input
#
#      11      No Connect on HTM  (I2C SCL on Hub)      
#      12      No Connect on HTM  (I2C SDA on Hub)
#
#      13      Ground
#      14      Ground
#      15      Access Signal #1  Output from HTM
#      16      Access Signal #2  Output from HTM
#





#
#   Connect the 3V3 JTAG Reference power and Ground
#   to the front panel J12 connector JTAG pins.
#

NET  'BULK_3V3'           F5-2

NET  'FUSED_JTAG_POWER'   F5-1   J12-2

NET  'GROUND'             J12-1   J12-3   J12-5   J12-7   J12-9





#
#   JTAG connections to/from  J12  and the  "Level Translator"
#   Buffer chip.
#
#   Note that we are using the  "B" side to "A" side direction.
#
#      "B" data input   to   "A" data output.
#
#      Thus both the Direction pin and the OE_B pin are tied Low.
#
#      The  input "B" side has 3V3 power.
#      The output "A" side has 3V3 power.
#
#   R351, R352, R354  are the pull-up resistors  to hold
#   the  TMS, TCK, and TDI  JTAG signals in a default state
#   when JTAG is not being used.
#
#   R357, R358, R359  are the series terminators at the
#   buffer  (driving)  end of the  TMS, TCK, and TDI  JTAG
#   signals that then run to the FPGA Mezz.
#
#   R360, R353  are the series terminators at the input
#   and output of the buffer for the TDO  JTAG signal.
#


#
#   TMS, TCK, and TDI  from J12  into Buffer:
#

NET  'TMS_FROM_J12'     J12-4    R351-1   U351-14

NET  'TCK_FROM_J12'     J12-6    R352-1   U351-15

NET  'TDI_FROM_J12'     J12-10   R354-1   U351-16

NET  'BULK_3V3'                R351-2   R352-2   R354-2


#
#   TMS, TCK, and TDI  from Buffer  through Series Terminator
#   and to the FPGA Mezz connector:
#

NET  'TMS_TO_SERIES_RES'   U351-10  R357-2

NET  'TMS_TO_FPGA_MEZZ'             R357-1    J3-142


NET  'TCK_TO_SERIES_RES'   U351-9   R358-2

NET  'TCK_TO_FPGA_MEZZ'             R358-1    J3-141


NET  'TDI_TO_SERIES_RES'   U351-8   R359-2

NET  'TDI_TO_FPGA_MEZZ'             R359-1    J3-147


#
#   TDO  JTAG signal  from the FPGA Mezz  through a Series
#   Terminator  to the Buffer  through an output Series
#   Terminator  and then to the J12 connector.
#

NET  'TDO_From_FPGA_Mezz'         J3-148    R360-1

NET  'TDO_To_Buffer'                        R360-2    U351-17

NET  'TDO_To_Output_Series_Res'   U351-7    R353-1

NET  'TDO_To_J12'                           R353-2    J12-8






#
#   Now connect the Access Signals from their source on
#   the FPGA Mezz  then through the U351 buffer chip  and
#   then through the series back terminator resistors to
#   their pins on front panel J12:

NET  'Access_Signal_1_from_FPGA'    J3-41    R361-1
NET  'Access_Signal_2_from_FPGA'    J3-43    R362-1

NET  'Access_Signal_1_To_Buffer'             R361-2    U351-20
NET  'Access_Signal_2_To_Buffer'             R362-2    U351-21

NET  'Access_Signal_1_To_Out_Res'   U351-4   R355-1
NET  'Access_Signal_2_To_Out_Res'   U351-3   R356-1

NET  'Access_Signal_1'                       R355-2    J12-15
NET  'Access_Signal_2'                       R356-2    J12-16

NET  'GROUND'                      J12-13    J12-14






#
#   Connect the  Power and Ground and DIR and OE_B
#   to the  U351  Translator  Buffer  chip
#
#      The  input "B" side has 3V3 power.
#      The output "A" side has 3V3 power.
#

#   U351  POWER AND GROUND

NET  'BULK_3V3'   U351-1

NET  'BULK_3V3'   U351-23   U351-24

NET  'GROUND'     U351-11   U351-12   U351-13


#   U351  DIR  and  OE_B  pins:
#
#      DIR  pin #2  is LOW  -->  from "B" side  to "A" side
#      OE_B pin #22 is LOW  -->  Enable Outputs

NET  'GROUND'     U351-2    U351-22





#
#   ByPass Capacitors for U351 Translators
#

NET  'BULK_3V3'   C351-1   C353-1
NET  'GROUND'     C351-2   C353-2

NET  'BULK_3V3'   C352-1   C354-1
NET  'GROUND'     C352-2   C354-2





#
#   Define the  Un-Used  Inputs and Outputs
#   on the Translator Buffer chip  U351.
#

NET  'No_Conn_U351_Pin_5'    U351-5
NET  'No_Conn_U351_Pin_19'   U351-19

NET  'No_Conn_U351_Pin_6'    U351-6
NET  'No_Conn_U351_Pin_18'   U351-18





#
#   Finally define the  two  unused pins
#   on the front panel J12 connector:
#

NET  'No_Conn_FP_J12_pin_11'    J12-11
NET  'No_Conn_FP_J12_pin_12'    J12-12