####################################################### # Configuration file for the HTM project # for use with ListCompPinNets.py Version > =2.5 # Rev 18-Apr-2018 copy/snapshot of Components and NetList for final Release # Rev 23-Apr-2018 also generate files for resistors and capacitors # Rev 25-Apr-2018 run on final release (without Rs and Cs) ####################################################### ####################################################### # The list of netlist file names, as strings, to be read and parsed # The default is to read no netlist file, i.e. not very useful :-) # netfile_list = ( ) netfile_list = ( #aa_htm_0_mixed_case_net_list.txt #aa_htm_0_net_list.txt #aa_htm_0_net_list.txt.nls "in_From_Mentor_HTM/Net_List/atca_power_entry_nets", "in_From_Mentor_HTM/Net_List/backplane_j23_ground_pin_nets", "in_From_Mentor_HTM/Net_List/bulk_2v5_supply_nets", "in_From_Mentor_HTM/Net_List/bulk_3v3_supply_nets", "in_From_Mentor_HTM/Net_List/clock_generation_nets", "in_From_Mentor_HTM/Net_List/distributed_bypass_capacitor_nets", "in_From_Mentor_HTM/Net_List/enet_j13_backplane_j23_nets", "in_From_Mentor_HTM/Net_List/enet_j14_trans1_fpga_mezz_nets", "in_From_Mentor_HTM/Net_List/fex_readout_to_hub_nets", "in_From_Mentor_HTM/Net_List/fpga_j1_power_and_ground_nets", "in_From_Mentor_HTM/Net_List/fpga_j2_power_and_ground_nets", "in_From_Mentor_HTM/Net_List/fpga_j3_j23_combined_data_from_hubs_nets", "in_From_Mentor_HTM/Net_List/fpga_j3_power_and_ground_nets", "in_From_Mentor_HTM/Net_List/fpga_mezz_no_conn_nets", "in_From_Mentor_HTM/Net_List/fpga_vcco_nets", "in_From_Mentor_HTM/Net_List/hardware_address_nets", "in_From_Mentor_HTM/Net_List/htm_life_boat_nets", "in_From_Mentor_HTM/Net_List/jtag_and_j12_associated_nets", "in_From_Mentor_HTM/Net_List/led_all_signals_power_gnd_nets", "in_From_Mentor_HTM/Net_List/mini_POD_nets", "in_From_Mentor_HTM/Net_List/monitor_connector_j11_nets", "in_From_Mentor_HTM/Net_List/shelf_grounds_and_links_all_nets", "in_From_Mentor_HTM/Net_List/sundry_htm_nets", ) # Or we could instead have grabbed the whole netlist (either mixed case or uppercase) # but the index of pin name versus source file name and line number would be less useful # e.g. #netfile_list = ( #"Net_Lists\aa_hub_0_net_list.txt", # for windows #"../../Net_Lists/aa_hub_0_net_list.txt", # on moto #"../../aa_hub_0_mixed_case_net_list.txt", #) ####################################################### # This sets a path for all output files (the path must end with a /) # This path may be obsolute or relative, but must already exist. # This path does not apply to the logfile which is always opened # in the local working directory before this configuration file is executed. # This is optional and the default is the local working directory # output_dir_name = "./" output_dir_name = "out_Comp_Pin_Nets_HTM_%s/" % current_time_stamp ####################################################### # specify a list of component prefixes # for which the output file will be skipped # This is optional and the default is to skip nothing # The filter is case-NONsensitive but -> THIS LIST MUST USE UPPERCASE <- while any case combination is filtered out # skip_comp_prefix = () skip_comp_prefix = ( "R", # Resistor "C", # Capacitance "L", # Inductance "F", # Fuse "DZ", # Zerner Diode "LED", # LED "GR", # Not a part, used for grounding "DPV", # Differential Pair vias "WTERM", # Wire Terminal "AKA", # Remote Sense Connections "K", # Guide Pin "ESD_STRIP_FO", # ESD strip grounding "ESD_STRIP_MB", # ESD strip grounding "HORZ_AIR_BAFFLE",# Air Baffle bar "VERT_AIR_BAFFLE",# Air Baffle bar "FPGA_MEZZ", # FPGA mezzanine mounting screws and silkscreen # skip some connectors "J11", # Monitor and Lifeboat "J12", # Front Panel Access "J15", # Front Panel Lemo "J16", # Front Panel Lemo ) ####################################################### # If a Mentor component file is given here, # the name of the output files will include the component name. # e.g. U31_has_328_pins_is_IC_BCM53128.txt # This is optional and the default is to not read a component file # component_file_name = "" component_file_name = "in_From_Mentor_HTM/Components/aa_htm_0_comp_file.txt" # Note: some cheating here !!!!! be careful to match the intention # Override the component file for J20, J21, J22, J23 # In order to have tailored pin usage for each mezzanine connector comp_file_dict[ "J1" ] = "Samtec_ASP-122953-01-J1" comp_file_dict[ "J2" ] = "Samtec_ASP-122953-01-J2" comp_file_dict[ "J3" ] = "Samtec_ASP-122953-01-J3" # Override the component file for U256 # in order to have tailored pin usage for the spare oscillator comp_file_dict[ "U256" ] = "CW_Spare_Osc" ####################################################### # list of files defining component type pin name dictionaries called "comp_type_pin_name_dict_list" comp_type_pin_name_dict_list = ( "in_Datasheet_Pin_Names_HTM/PowerSupplies.dct", "in_Datasheet_Pin_Names_HTM/Clock_40MHz.dct", "in_Datasheet_Pin_Names_HTM/Eth_Transf.dct", "in_Datasheet_Pin_Names_HTM/Eth_RJ45.dct", "in_Datasheet_Pin_Names_HTM/MiniPOD.dct", "in_Datasheet_Pin_Names_HTM/LevelTranslators.dct", "in_Datasheet_Pin_Names_HTM/ATCA.dct", "in_Datasheet_Pin_Names_HTM/TwoPinParts.dct", "in_Datasheet_Pin_Names_HTM/Trenz_FPGA_Mezz.dct", ) ####################################################### # If this variable is set to True each output line that lists a pin name # will also show the pin name/description/usage for that component type, if it was made available # e.g.: # A6 = COMB_DATA_TO_CAP_TO_FEX_11_DIR MGTHTXN3_232 # This is optional and the default is to skip including pin names # include_pin_name = False include_pin_name = True ####################################################### # If this variable is set to True each output line that lists a pin name # will also show which line of which net file it was read from. # e.g.: # 1 = LED_30_Cath_Res from line 184 of led_connection_nets # This is optional and the default is skip generating an index #include_index = False include_index = True ####################################################### # If this variable is set to False the section listing the pins sorted by pin number will be omitted # e.g.: # 1 = LED_30_Cath_Res # 2 = No_Conn_SW_A_LEDP30_IMP_TXC_DELAY # 3 = BULK_3V3 # ... # This is optional and the default is to include this list. # include_sort_by_pin = True ####################################################### # If this variable is set to False the section listing the pins sorted by net tname will be omitted # e.g.: # ... # 202 = Chip_A_TRD0_0_CMP # 201 = Chip_A_TRD0_0_DIR # 222 = Chip_A_TRD0_1_CMP # ... # This is optional and the default is to include this list. # include_sort_by_name = True ####################################################### # Provide entries in a dictionary for component reference names for which a UCF Xilinx Constraint file should be created. # For each entry, specify the desired UCF file name. # # this output file will receive lines like # NET "P12_21" LOC = "B4"; # # The default is to generate no UCF file # Note: The Hub has only one Xilinx FPGA, one could create more than one constraint file for other projects # No longer useful # ucf_file_dict [ "U1" ] = "Hub_FPGA_ucf_%s.txt" % current_time_stamp # Provide entries in a dictionary for component reference names for which a XDC Xilinx Constraint file should be created. # For each entry, specify the desired XDC file name. # # this output file will receive lines like # set_property PACKAGE_PIN AU33 [get_ports "Phys_U21_CLK125_LED_MODE"] ; # # The default is to generate no XDC file # xdc_file_dict [ "U1" ] = "Hub_FPGA_xdc_%s.txt" % current_time_stamp # Provide a list of Net Names to be skipped when creating the UCF and XDC file(s) # e.g. ucfxdc_skip_net_name_lst = ( "GROUND", ) # The default is to skip nothing. #ucfxdc_skip_net_name_lst = \ #( # "GROUND", # "BULK_1V8", "BULK_3V3", "FPGA_CORE", "VBATT", # "MGT_AVAUX","MGT_AVCC", "MGT_AVTT", # "SysMon_Main_Input_VN", "SysMon_Main_Input_VP", # "FPGA_Config_DONE", "POR_OVERRIDE", "PROGRAM_B", # "SYSMON_1V8", "SYSMON_GND","SYSMON_VREFP", # "Temp_Diode_DXN", "Temp_Diode_DXP", # "CONFIG_M0", "CONFIG_M1", "CONFIG_M2", "PUDC_B", "CFGBVS", # "FLASH_OUTPUT_ENB_B", "FLASH_RESET_B", "FLASH_WRITE_ENB_B", "FLASH_CHIP_ENB_B", # "FLASH_A00", "FLASH_A01", "FLASH_A02", "FLASH_A03", "FLASH_A04", "FLASH_A05", "FLASH_A06", "FLASH_A07", "FLASH_A08", "FLASH_A09", # "FLASH_A10", "FLASH_A11", "FLASH_A12", "FLASH_A13", "FLASH_A14", "FLASH_A15", "FLASH_A16", "FLASH_A17", "FLASH_A18", "FLASH_A19", # "FLASH_A20", "FLASH_A21", "FLASH_A22", "FLASH_A23", "FLASH_A24", "FLASH_A25", # "FLASH_D00", "FLASH_D01", "FLASH_D02", "FLASH_D03", "FLASH_D04", "FLASH_D05", "FLASH_D06", "FLASH_D07", "FLASH_D08", "FLASH_D09", # "FLASH_D10", "FLASH_D11", "FLASH_D12", "FLASH_D13", "FLASH_D14", "FLASH_D15", # "Bank_65_VREF", "Bank_65_VRP_DCI", # "Bank_66_VREF", "Bank_66_VRP_DCI", # "Bank_67_VREF", "Bank_67_VRP_DCI", # "Bank_68_VREF", "Bank_68_VRP_DCI", # "Bank_71_VREF", "Bank_71_VRP_DCI", # "Bank_84_VREF", "Bank_94_VREF", # "QUAD_125_MGTRREF", "QUAD_130_MGTRREF", "QUAD_226_MGTRREF", "QUAD_231_MGTRREF", # "TCK_TO_HUB_FPGA", "TMS_TO_HUB_FPGA", "TDI_SERIES_TO_HUB_FPGA", "TD_HUB_FPGA_TO_JMP1", #) # Provide a list of Component Reference Designator with Pin Name to be skipped when creating the UCF and XDC file(s) # e.g. ucfxdc_skip_comp_pin_ref_lst = ( "U1-BE16", ) # The default is to skip nothing. #ucfxdc_skip_comp_pin_ref_lst = \ #( # "U1-BE16", # IO_L23P_T3U_N8_I2C_SCLK_65 repeats 'Hub_I2C_to_FPGA_SCL' # "U1-BF16", # IO_L23N_T3U_N9_I2C_SDA_65 repeats 'Hub_I2C_to_FPGA_SDA' #)