# # FEX READOUT TO HUB NET LIST FILE # # FPGA MEZZANINE J3/J1 MGT TRANSMITTERS, READOUT STREAMS, # AND CAPACITORS LINKS # ----------------------------------------------------- # # # INITIAL REV. 1-FEB-2018 # CURRENT REV. 10-APR-2018 # # # THIS FILE HOLDS ALL OF THE MGT TRANSMITTER, READOUT STREAM, # AND CAPACITOR CONNECTIONS FOR THE FPGA MEZZANINE CONNECTOR # J3, AND FOUR OF THESE CONNECTIONS FOR THE FPGA MEZZANINE CONNECTOR # J1. # # NET 'MGT_TX_0_TO_CAP_DIR' J3-31 C1-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_0_TO_CAP_CMP' J3-29 C2-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_2_DIR' J23-A1 C1-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_2_CMP' J23-B1 C2-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_1_TO_CAP_DIR' J3-27 C3-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_1_TO_CAP_CMP' J3-25 C4-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_2_DIR' J23-C1 C3-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_2_CMP' J23-D1 C4-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_2_TO_CAP_DIR' J3-23 C5-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_2_TO_CAP_CMP' J3-21 C6-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_2_DIR' J23-E1 C5-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_2_CMP' J23-F1 C6-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_3_TO_CAP_DIR' J3-19 C7-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_3_TO_CAP_CMP' J3-17 C8-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_2_DIR' J23-G1 C7-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_2_CMP' J23-H1 C8-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_4_TO_CAP_DIR' J3-15 C9-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_4_TO_CAP_CMP' J3-13 C10-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_2_DIR' J23-A2 C9-1 DPV9-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_2_CMP' J23-B2 C10-1 DPV9-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_5_TO_CAP_DIR' J3-11 C11-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_5_TO_CAP_CMP' J3-9 C12-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_2_DIR' J23-E2 C11-1 DPV11-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_2_CMP' J23-F2 C12-1 DPV11-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_6_TO_CAP_DIR' J3-7 C13-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_6_TO_CAP_CMP' J3-5 C14-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_1_DIR' J23-A3 C13-1 DPV13-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_3_HUB_1_CMP' J23-B3 C14-1 DPV13-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_7_TO_CAP_DIR' J3-3 C15-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_7_TO_CAP_CMP' J3-1 C16-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_1_DIR' J23-C3 C15-1 DPV15-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_5_HUB_1_CMP' J23-D3 C16-1 DPV15-2 (NET_TYPE, 'DIFF_PAIR_HS') # # THESE LAST 4 FEX READOUT DATA CONNECTIONS ALL CONTAIN # A POLARITY FLIP. THE FLIPS HAVE BEEN IMPLEMENTED BY # SWAPING THE DIR/CMP PINS ON THE J23 CONNECTOR. # # NOTE THAT ON THE J23 CONNECTOR # # PINS: E3, G3, A4, E4 ARE REALY THE DIR SIGNAL # PINS: F3, H3, B4, F4 ARE REALY THE CMP SIGNAL # NET 'MGT_TX_8_TO_CAP_DIR' J1-2 C17-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_8_TO_CAP_CMP' J1-4 C18-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_1_DIR' J23-F3 C17-1 DPV17-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_4_HUB_1_CMP' J23-E3 C18-1 DPV17-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_9_TO_CAP_DIR' J1-6 C19-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_9_TO_CAP_CMP' J1-8 C20-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_1_DIR' J23-H3 C19-1 DPV19-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_6_HUB_1_CMP' J23-G3 C20-1 DPV19-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_10_TO_CAP_DIR' J1-10 C21-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_10_TO_CAP_CMP' J1-12 C22-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_1_DIR' J23-B4 C21-1 DPV21-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_1_HUB_1_CMP' J23-A4 C22-1 DPV21-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_11_TO_CAP_DIR' J1-14 C23-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MGT_TX_11_TO_CAP_CMP' J1-16 C24-2 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_1_DIR' J23-F4 C23-1 DPV23-3 (NET_TYPE, 'DIFF_PAIR_HS') NET 'RO_STRM_2_HUB_1_CMP' J23-E4 C24-1 DPV23-2 (NET_TYPE, 'DIFF_PAIR_HS') # # GROUNDS ON THE DIFFERENTIAL VIA PAIRS # GROUND RETURN VIAS # NET 'GROUND' DPV9-1 DPV9-4 DPV11-1 DPV11-4 DPV13-1 DPV13-4 NET 'GROUND' DPV15-1 DPV15-4 NET 'GROUND' DPV17-1 DPV17-4 DPV19-1 DPV19-4 DPV21-1 DPV21-4 NET 'GROUND' DPV23-1 DPV23-4 # # THIS IS THE KEY IN NET LIST FILE FOR THE # # HTM MODULE POWER ENTRY NETS # ------------------------------------------------ # # # ORIGINAL REV. 2-FEB-2018 # MOST RECENT REV. 23-MAR-2018 # # # ATCA POWER ENTRY NETS: # # # SHELF GROUND # NET 'SHELF_GND' P10-25 # # LOGIC GROUND # NET 'GROUND' P10-26 # # -48V ENTRY A & B BUSES # NET 'A_BUS_N48V_BP' P10-33 F4-2 NET 'CARD_BUS_N48V' F4-1 L1-1 NET 'A_BUS_EARLY_48_BP' P10-30 R951-1 NET 'A_BUS_N48V_BP' R951-2 NET 'B_BUS_N48V_BP' P10-34 F3-2 NET 'CARD_BUS_N48V' F3-1 NET 'B_BUS_EARLY_48_BP' P10-31 R952-1 NET 'B_BUS_N48V_BP' R952-2 # # POWER RETURNS A & B BUSES # NET 'A_BUS_48V_RETURN_BP' P10-28 F2-2 NET 'CARD_48V_BUS_RETURN' F2-1 L1-4 NET 'B_BUS_48V_RETURN_BP' P10-29 F1-2 NET 'CARD_48V_BUS_RETURN' F1-1 # # ATCA "ENTERED" 48V POWER TO THE 12V CONVERTER # NET 'ENTERED_N48V' L1-2 NET 'ENTERED_48V_RTN' L1-3 NET 'ENTERED_N48V' C954-2 C955-2 C952-2 NET 'ENTERED_48V_RTN' C954-1 C955-1 C951-2 NET 'ENTERED_N48V' POWER_12V-3 NET 'ENTERED_48V_RTN' POWER_12V-1 NET 'SHELF_GND' C951-1 C952-1 # # PAY LOAD ENABLE SIGNAL TO THE ISOLATED +12V CONVERTER # NET 'ENABLE_ISO_12V_B' POWER_12V-2 WTERM12-1 NET 'ENTERED_N48V' WTERM11-1 # # ISOLATED +12V POWER FROM THE CONVERTER # NET 'ISO_12V' POWER_12V-8 NET 'GROUND' POWER_12V-4 # # REMOTE SENSE FEEDBACK CONNECTIONS: # # THE REMOTE SENSE FOR BOTH THE POSITIVE AND NEGATIVE SIDES # OF OF THE ISO_12V OUTPUT MUST BE ISOLATED FROM THE FILLS # AND GROUND PLANES THAT ARE DIRECTLY UNDER THESE PINS. # # I PROVIDE THIS ISOLATION BY GIVING THE REMOTE SENSE PINS # A UNIQUE NET NAME AND THEN CONNECTING THESE UNIQUE REMOTE # SENSE NETS TO THE ISO_12V AND GROUND NETS BY USING AN # "AKA" COMPONENT, I.E. STRAIGHT THROUGH AT THE SAME WIDTH # AS THE TRACE ON A BREAKOUT LAYER. # # IN THIS SECTION ALSO GIVE THE "TRIM" PIN ON THE ISO_12V # SUPPLY A NET NAME. # NET 'REMOTE_SENSE_GND_ISO_12V' POWER_12V-5 AKA1-2 NET 'GROUND' AKA1-1 NET 'NO_CONN_TRIM_12V' POWER_12V-6 NET 'REMOTE_SENSE_POS_ISO_12V' POWER_12V-7 AKA2-2 NET 'ISO_12V' AKA2-1 # # FILTER THE ISOLATED +12V POWER FROM THE CONVERTER # NET 'ISO_12V' C957-2 C958-2 C959-2 C960-2 NET 'ISO_12V' C961-1 C962-1 C963-1 C964-1 NET 'GROUND' C957-1 C958-1 C959-1 C960-1 NET 'GROUND' C961-2 C962-2 C963-2 C964-2 # # NO CONNECTION PINS ON THE P10 ZONE 1 CONNECTOR # NET 'NO_CONN_P10_PIN_13' P10-13 NET 'NO_CONN_P10_PIN_14' P10-14 NET 'NO_CONN_P10_PIN_15' P10-15 NET 'NO_CONN_P10_PIN_16' P10-16 NET 'NO_CONN_P10_PIN_27' P10-27 NET 'NO_CONN_P10_PIN_32' P10-32 # # J13 FRONT PANEL RJ-45 BACKPLANE J23 ENET NETS # ---------------------------------------------------- # # # ORIGINAL REV. 4-FEB-2018 # CURRENT REV. 4-FEB-2018 # # # THIS NET LIST FILE CONTAIN THE CONNECTIONS FROM THE # FPGA MEZZANINE TO THE FRONT PANEL RJ-45 CONNECTOR J14. # # J13 LOWER OR LEFT BACKPLANE J23 HUB #1 BI ENET # UPPER OR RIGHT BACKPLANE J23 HUB #2 BI ENET # # # # RECALL THE DEFAULT SETUP OF THE 4 LANES IN EACH # ETHERNET LINK: # # ATCA # PRI SEC ADFPLUS # ATCA ALT MAG MAG RJ-45 CONN. # LANE LANE PIN PIN PIN COLUMN # ------- ------- ----- ----- ----- ------- # # A-DIR 0_DIR 1 7 1 A # 2 CT 8 # A-CMP 0_CMP 3 9 2 B # # # B-DIR 1_DIR 4 10 3 C # 5 CT 11 # B-CMP 1_CMP 6 12 6 D # # # C-DIR 2_DIR 24 18 4 E # 23 CT 17 # C-CMP 2_CMP 22 16 5 F # # # D-DIR 3_DIR 21 15 7 G # 20 CT 14 # D-CMP 3_CMP 19 13 8 H # # # # # #------------------------------------------------------------ # # # FRONT PANEL J13 RIGHT-UPPER HUB #2 BASE INTERFACE ENET NET 'J13_U_A_0_DIR' J23-A6 J13-U1 NET 'J13_U_A_0_CMP' J23-B6 J13-U2 NET 'J13_U_B_1_DIR' J23-C6 J13-U3 NET 'J13_U_B_1_CMP' J23-D6 J13-U6 NET 'J13_U_C_2_DIR' J23-E6 J13-U4 NET 'J13_U_C_2_CMP' J23-F6 J13-U5 NET 'J13_U_D_3_DIR' J23-G6 J13-U7 NET 'J13_U_D_3_CMP' J23-H6 J13-U8 # #------------------------------------------------------------ # # # FRONT PANEL J13 LEFT-LOWER HUB #1 BASE INTERFACE ENET NET 'J13_L_A_0_DIR' J23-A5 J13-L1 NET 'J13_L_A_0_CMP' J23-B5 J13-L2 NET 'J13_L_B_1_DIR' J23-C5 J13-L3 NET 'J13_L_B_1_CMP' J23-D5 J13-L6 NET 'J13_L_C_2_DIR' J23-E5 J13-L4 NET 'J13_L_C_2_CMP' J23-F5 J13-L5 NET 'J13_L_D_3_DIR' J23-G5 J13-L7 NET 'J13_L_D_3_CMP' J23-H5 J13-L8 # #------------------------------------------------------------ # # # FPGA ETHERNET TRANS1 J14 FRONT PANEL RJ-45 NETS # ----------------------------------------------------- # # # ORIGINAL REV. 4-FEB-2018 # CURRENT REV. 5-FEB-2018 # # # THIS NET LIST FILE CONTAIN THE CONNECTIONS FROM THE # FPGA MEZZANINE TO THE FRONT PANEL RJ-45 CONNECTOR J14. # # J14 LOWER OR LEFT FPGA MEZZANINE PHY 2 # UPPER OR RIGHT FPGA MEZZANINE PHY 1 # # # TRANS1 LEFT J14 LOWER FPGA MEZZANINE PHY 2 # RIGHT J14 UPPER FPGA MEZZANINE PHY 1 # # # FPGA MEZZANINE PHY 1 IS BANK 501 OF THE ARM CORTEX # FPGA MEZZANINE PHY 2 IS BANK 9 OF THE FPGA FABRIC # # # # RECALL THE DEFAULT SETUP OF THE 4 LANES IN EACH # ETHERNET LINK: # # ATCA # PRI SEC ADFPLUS # ATCA ALT MAG MAG RJ-45 CONN. # LANE LANE PIN PIN PIN COLUMN # ------- ------- ----- ----- ----- ------- # # A-DIR 0_DIR 1 7 1 A # 2 CT 8 # A-CMP 0_CMP 3 9 2 B # # # B-DIR 1_DIR 4 10 3 C # 5 CT 11 # B-CMP 1_CMP 6 12 6 D # # # C-DIR 2_DIR 24 18 4 E # 23 CT 17 # C-CMP 2_CMP 22 16 5 F # # # D-DIR 3_DIR 21 15 7 G # 20 CT 14 # D-CMP 3_CMP 19 13 8 H # # # # TO FACILITATE ROUTING ONE MAY: # # - SWAP TRANSFORMERS WITHIN A GIVEN SIDE OF A MODULE. # FOR EXAMPLE R1, R3, R7, R9 COULD BE # SWAPPED WITH R4, R6, R10, R12. # # - IT IS PROBABLY BEST NOT TO WIRE THINGS UP SO THAT # FOR A GIVEN ETHERNET LINK SOME OF ITS TRANSFORMERS # ARE IN THE R SIDE OF THE MODULE AND SOME OF ITS # TRANSFORMERS ARE IN THE L SIDE OF THE MODULE. # # - SWAP THE POLARITY OF A GIVEN TRANSFORMER. FOR # EXAMPLE ONE MAY SWAP R1 WITH R3 WHILE ALSO # SWAPPING R7 WITH R9. # # # TO FACILITATE UNDERSTANDING HOW THE MAGNETICS FOR A # GIVEN ETHERNET LINK ARE WIRED UP I'M PUTTING THE NETS # FOR THE PRIMARY AND SECONDAY SIDES OF A GIVEN LINK # NEXT TO EACH OTHER IN THIS FILE. # # NOTE THAT THE RC COMPONENTS ATTACHED TO THE MAGNETICS # HAVE NET NAMES THAT ARE INDEPENDED OF THE ETHERENT LINK # THAT THEY SERVICE. THESE CENTER TAP (CT) NETS ARE # LISTED AT THE END OF THIS FILE. THESE MAGNETICS RC # NETS DO NOT HAVE TO BE DISTURBED IF THE PRIMARY AND # SECONDAY NETS ARE SWAPPED FOR ROUTING. # # # #------------------------------------------------------------ # # # TRANS1 RIGHT J14 UPPER/RIGHT FPGA MEZZANINE PHY 1 # # # PRIMARY NETS TRANS 1 R NET 'PHY_1_TRD0_6_DIR' J2-23 TRANS1-R1 NET 'PHY_1_TRD0_6_CMP' J2-21 TRANS1-R3 NET 'PHY_1_TRD1_6_DIR' J2-19 TRANS1-R4 NET 'PHY_1_TRD1_6_CMP' J2-17 TRANS1-R6 NET 'PHY_1_TRD2_6_DIR' J2-15 TRANS1-R24 NET 'PHY_1_TRD2_6_CMP' J2-13 TRANS1-R22 NET 'PHY_1_TRD3_6_DIR' J2-11 TRANS1-R21 NET 'PHY_1_TRD3_6_CMP' J2-9 TRANS1-R19 # # SECONDARY NETS TRANS 1 R FRONT PANEL J14 RIGHT-UPPER NET 'J14_U_A_0_DIR' TRANS1-R7 J14-U1 NET 'J14_U_A_0_CMP' TRANS1-R9 J14-U2 NET 'J14_U_B_1_DIR' TRANS1-R10 J14-U3 NET 'J14_U_B_1_CMP' TRANS1-R12 J14-U6 NET 'J14_U_C_2_DIR' TRANS1-R18 J14-U4 NET 'J14_U_C_2_CMP' TRANS1-R16 J14-U5 NET 'J14_U_D_3_DIR' TRANS1-R15 J14-U7 NET 'J14_U_D_3_CMP' TRANS1-R13 J14-U8 # #------------------------------------------------------------ # # # TRANS1 LEFT J14 LOWER/LEFT FPGA MEZZANINE PHY 2 # # # PRIMARY NETS TRANS 1 L NET 'PHY_2_TRD0_6_DIR' J2-39 TRANS1-L1 NET 'PHY_2_TRD0_6_CMP' J2-37 TRANS1-L3 NET 'PHY_2_TRD1_6_DIR' J2-35 TRANS1-L4 NET 'PHY_2_TRD1_6_CMP' J2-33 TRANS1-L6 NET 'PHY_2_TRD2_6_DIR' J2-31 TRANS1-L24 NET 'PHY_2_TRD2_6_CMP' J2-29 TRANS1-L22 NET 'PHY_2_TRD3_6_DIR' J2-27 TRANS1-L21 NET 'PHY_2_TRD3_6_CMP' J2-25 TRANS1-L19 # # SECONDARY NETS TRANS 1 L FRONT PANEL J14 LEFT-LOWER NET 'J14_L_A_0_DIR' TRANS1-L7 J14-L1 NET 'J14_L_A_0_CMP' TRANS1-L9 J14-L2 NET 'J14_L_B_1_DIR' TRANS1-L10 J14-L3 NET 'J14_L_B_1_CMP' TRANS1-L12 J14-L6 NET 'J14_L_C_2_DIR' TRANS1-L18 J14-L4 NET 'J14_L_C_2_CMP' TRANS1-L16 J14-L5 NET 'J14_L_D_3_DIR' TRANS1-L15 J14-L7 NET 'J14_L_D_3_CMP' TRANS1-L13 J14-L8 # #------------------------------------------------------------ # # # PRIMARY CENTER TAP NETS TRANS 1 R AND L # NET 'TRANS1_R_A_0_PRI_CT' TRANS1-R2 C301-2 NET 'TRANS1_R_B_1_PRI_CT' TRANS1-R5 C304-2 NET 'TRANS1_R_C_2_PRI_CT' TRANS1-R23 C302-2 NET 'TRANS1_R_D_3_PRI_CT' TRANS1-R20 C303-2 NET 'GROUND' C301-1 C302-1 C303-1 C304-1 NET 'TRANS1_L_A_0_PRI_CT' TRANS1-L2 C307-2 NET 'TRANS1_L_B_1_PRI_CT' TRANS1-L5 C308-2 NET 'TRANS1_L_C_2_PRI_CT' TRANS1-L23 C306-2 NET 'TRANS1_L_D_3_PRI_CT' TRANS1-L20 C309-2 NET 'GROUND' C306-1 C307-1 C308-1 C309-1 # # SECONDARY CENTER TAP NETS TRANS 1 R AND L # NET 'TRANS1_R_A_0_SEC_CT' TRANS1-R8 R302-1 NET 'TRANS1_R_B_1_SEC_CT' TRANS1-R11 R304-1 NET 'TRANS1_R_C_2_SEC_CT' TRANS1-R17 R301-1 NET 'TRANS1_R_D_3_SEC_CT' TRANS1-R14 R303-1 NET 'TRANS1_L_SEC_CT_TIE' R301-2 R302-2 R303-2 R304-2 NET 'TRANS1_L_SEC_CT_TIE' C305-1 NET 'GROUND' C305-2 NET 'TRANS1_L_A_0_SEC_CT' TRANS1-L8 R307-1 NET 'TRANS1_L_B_1_SEC_CT' TRANS1-L11 R308-1 NET 'TRANS1_L_C_2_SEC_CT' TRANS1-L17 R306-1 NET 'TRANS1_L_D_3_SEC_CT' TRANS1-L14 R309-1 NET 'TRANS1_R_SEC_CT_TIE' R306-2 R307-2 R308-2 R309-2 NET 'TRANS1_R_SEC_CT_TIE' C310-1 NET 'GROUND' C310-2 # # HTM CARD NET LIST FILE # # JTAG AND ALL ASSOCIATED J12 NETS # ---------------------------------- # # # INITIAL REV. 4-FEB-2018 # CURRENT REV. 7-APR-2018 # # # THIS FILE HOLDS ALL OF THE NETS ASSOCIATED WITH THE # JTAG CIRCUIT AND THE FRONT PANEL ACCESS SIGNALS # ON THE HTM CARD, THAT IS ALL SIGNALS ASSOCIATED WITH # THE J12 FRONT PANEL "ACCESS CONNECTOR". # # # # RECALL THE PINOUT OF THE FRONT PANEL J12 CONNECTOR ON HTM: # # PIN FUNCTION # --- --------------- # # 1 GROUND # 2 3V3 JTAG POWER # 3 GROUND # 4 TMS INPUT # 5 GROUND # 6 TCK INPUT # 7 GROUND # 8 TDO OUTPUT # 9 GROUND # 10 TDI INPUT # # 11 NO CONNECT ON HTM (I2C SCL ON HUB) # 12 NO CONNECT ON HTM (I2C SDA ON HUB) # # 13 GROUND # 14 GROUND # 15 ACCESS SIGNAL #1 OUTPUT FROM HTM # 16 ACCESS SIGNAL #2 OUTPUT FROM HTM # # # CONNECT THE 3V3 JTAG REFERENCE POWER AND GROUND # TO THE FRONT PANEL J12 CONNECTOR JTAG PINS. # NET 'BULK_3V3' F5-2 NET 'FUSED_JTAG_POWER' F5-1 J12-2 NET 'GROUND' J12-1 J12-3 J12-5 J12-7 J12-9 # # JTAG CONNECTIONS TO/FROM J12 AND THE "LEVEL TRANSLATOR" # BUFFER CHIP. # # NOTE THAT WE ARE USING THE "B" SIDE TO "A" SIDE DIRECTION. # # "B" DATA INPUT TO "A" DATA OUTPUT. # # THUS BOTH THE DIRECTION PIN AND THE OE_B PIN ARE TIED LOW. # # THE INPUT "B" SIDE HAS 3V3 POWER. # THE OUTPUT "A" SIDE HAS 3V3 POWER. # # R351, R352, R354 ARE THE PULL-UP RESISTORS TO HOLD # THE TMS, TCK, AND TDI JTAG SIGNALS IN A DEFAULT STATE # WHEN JTAG IS NOT BEING USED. # # R357, R358, R359 ARE THE SERIES TERMINATORS AT THE # BUFFER (DRIVING) END OF THE TMS, TCK, AND TDI JTAG # SIGNALS THAT THEN RUN TO THE FPGA MEZZ. # # R360, R353 ARE THE SERIES TERMINATORS AT THE INPUT # AND OUTPUT OF THE BUFFER FOR THE TDO JTAG SIGNAL. # # # TMS, TCK, AND TDI FROM J12 INTO BUFFER: # NET 'TMS_FROM_J12' J12-4 R351-1 U351-14 NET 'TCK_FROM_J12' J12-6 R352-1 U351-15 NET 'TDI_FROM_J12' J12-10 R354-1 U351-16 NET 'BULK_3V3' R351-2 R352-2 R354-2 # # TMS, TCK, AND TDI FROM BUFFER THROUGH SERIES TERMINATOR # AND TO THE FPGA MEZZ CONNECTOR: # NET 'TMS_TO_SERIES_RES' U351-10 R357-2 NET 'TMS_TO_FPGA_MEZZ' R357-1 J3-142 NET 'TCK_TO_SERIES_RES' U351-9 R358-2 NET 'TCK_TO_FPGA_MEZZ' R358-1 J3-141 NET 'TDI_TO_SERIES_RES' U351-8 R359-2 NET 'TDI_TO_FPGA_MEZZ' R359-1 J3-147 # # TDO JTAG SIGNAL FROM THE FPGA MEZZ THROUGH A SERIES # TERMINATOR TO THE BUFFER THROUGH AN OUTPUT SERIES # TERMINATOR AND THEN TO THE J12 CONNECTOR. # NET 'TDO_FROM_FPGA_MEZZ' J3-148 R360-1 NET 'TDO_TO_BUFFER' R360-2 U351-17 NET 'TDO_TO_OUTPUT_SERIES_RES' U351-7 R353-1 NET 'TDO_TO_J12' R353-2 J12-8 # # NOW CONNECT THE ACCESS SIGNALS FROM THEIR SOURCE ON # THE FPGA MEZZ THEN THROUGH THE U351 BUFFER CHIP AND # THEN THROUGH THE SERIES BACK TERMINATOR RESISTORS TO # THEIR PINS ON FRONT PANEL J12: NET 'ACCESS_SIGNAL_1_FROM_FPGA' J3-41 R361-1 NET 'ACCESS_SIGNAL_2_FROM_FPGA' J3-43 R362-1 NET 'ACCESS_SIGNAL_1_TO_BUFFER' R361-2 U351-20 NET 'ACCESS_SIGNAL_2_TO_BUFFER' R362-2 U351-21 NET 'ACCESS_SIGNAL_1_TO_OUT_RES' U351-4 R355-1 NET 'ACCESS_SIGNAL_2_TO_OUT_RES' U351-3 R356-1 NET 'ACCESS_SIGNAL_1' R355-2 J12-15 NET 'ACCESS_SIGNAL_2' R356-2 J12-16 NET 'GROUND' J12-13 J12-14 # # CONNECT THE POWER AND GROUND AND DIR AND OE_B # TO THE U351 TRANSLATOR BUFFER CHIP # # THE INPUT "B" SIDE HAS 3V3 POWER. # THE OUTPUT "A" SIDE HAS 3V3 POWER. # # U351 POWER AND GROUND NET 'BULK_3V3' U351-1 NET 'BULK_3V3' U351-23 U351-24 NET 'GROUND' U351-11 U351-12 U351-13 # U351 DIR AND OE_B PINS: # # DIR PIN #2 IS LOW --> FROM "B" SIDE TO "A" SIDE # OE_B PIN #22 IS LOW --> ENABLE OUTPUTS NET 'GROUND' U351-2 U351-22 # # BYPASS CAPACITORS FOR U351 TRANSLATORS # NET 'BULK_3V3' C351-1 C353-1 NET 'GROUND' C351-2 C353-2 NET 'BULK_3V3' C352-1 C354-1 NET 'GROUND' C352-2 C354-2 # # DEFINE THE UN-USED INPUTS AND OUTPUTS # ON THE TRANSLATOR BUFFER CHIP U351. # NET 'NO_CONN_U351_PIN_5' U351-5 NET 'NO_CONN_U351_PIN_19' U351-19 NET 'NO_CONN_U351_PIN_6' U351-6 NET 'NO_CONN_U351_PIN_18' U351-18 # # FINALLY DEFINE THE TWO UNUSED PINS # ON THE FRONT PANEL J12 CONNECTOR: # NET 'NO_CONN_FP_J12_PIN_11' J12-11 NET 'NO_CONN_FP_J12_PIN_12' J12-12 # # HTM CARD NET LIST FILE # # LED DRIVER AND ALL LED ASSOCIATED NETS # ---------------------------------------- # # # INITIAL REV. 4-FEB-2018 # CURRENT REV. 5-APR-2018 # # # THIS FILE HOLDS ALL OF THE NETS ASSOCIATED WITH THE # HTM CARD'S LEDS: # # DRIVER TO LED SIGNALS # CONTROL SIGNALS TO DRIVERS # SERIES RESISTORS # # # # CONNECT J2 SELECT IO PINS TO THE U201 LED DRIVER CHIP CONTROL INPUT # NET 'J2_RX11_P_U201_LED_DRIVER_CONTROL_INPUT_14' J2-108 U201-14 NET 'J2_RX12_P_U201_LED_DRIVER_CONTROL_INPUT_15' J2-114 U201-15 NET 'J2_RX13_P_U201_LED_DRIVER_CONTROL_INPUT_16' J2-120 U201-16 NET 'J2_RX14_P_U201_LED_DRIVER_CONTROL_INPUT_17' J2-126 U201-17 NET 'J2_RX15_P_U201_LED_DRIVER_CONTROL_INPUT_18' J2-132 U201-18 NET 'J2_RX16_P_U201_LED_DRIVER_CONTROL_INPUT_19' J2-138 U201-19 NET 'J2_RX17_P_U201_LED_DRIVER_CONTROL_INPUT_20' J2-144 U201-20 NET 'J2_RX18_P_U201_LED_DRIVER_CONTROL_INPUT_21' J2-150 U201-21 # # CONNECT LEDS 1-8 TO THE U201 LED DRIVER CHIP # NET 'LED_1_CATHODE_PUSH_SIGNAL' LED1-1 U201-3 NET 'LED_2_CATHODE_PUSH_SIGNAL' LED2-1 U201-4 NET 'LED_3_CATHODE_PUSH_SIGNAL' LED3-1 U201-5 NET 'LED_4_CATHODE_PUSH_SIGNAL' LED4-1 U201-6 NET 'LED_5_CATHODE_PUSH_SIGNAL' LED5-1 U201-7 NET 'LED_6_CATHODE_PUSH_SIGNAL' LED6-1 U201-8 NET 'LED_7_CATHODE_PUSH_SIGNAL' LED7-1 U201-9 NET 'LED_8_CATHODE_PUSH_SIGNAL' LED8-1 U201-10 # # CONNECT BULK_3V3 POWER TO THE R201-8 LED RESISTORS AND # CONNECT EACH R201-8 LED RESISTOR TO ONE OF LEDS 1-8 # NET 'BULK_3V3' R201-2 NET 'LED_1_PU_RES' R201-1 LED1-2 NET 'BULK_3V3' R202-2 NET 'LED_2_PU_RES' R202-1 LED2-2 NET 'BULK_3V3' R203-2 NET 'LED_3_PU_RES' R203-1 LED3-2 NET 'BULK_3V3' R204-2 NET 'LED_4_PU_RES' R204-1 LED4-2 NET 'BULK_3V3' R205-2 NET 'LED_5_PU_RES' R205-1 LED5-2 NET 'BULK_3V3' R206-2 NET 'LED_6_PU_RES' R206-1 LED6-2 NET 'BULK_3V3' R207-2 NET 'LED_7_PU_RES' R207-1 LED7-2 NET 'BULK_3V3' R208-2 NET 'LED_8_PU_RES' R208-1 LED8-2 # # BLOCKS J13 AND J14 # # # CONNECT J2 SELECT IO PINS TO THE U201 LED DRIVER CHIP CONTROL INPUT # NET 'J2_RX1_P_U202_LED_DRIVER_CONTROL_INPUT_14' J2-48 U202-14 NET 'J2_RX2_P_U202_LED_DRIVER_CONTROL_INPUT_15' J2-54 U202-15 NET 'J2_RX3_P_U202_LED_DRIVER_CONTROL_INPUT_16' J2-60 U202-16 NET 'J2_RX4_P_U202_LED_DRIVER_CONTROL_INPUT_17' J2-66 U202-17 NET 'J2_RX5_P_U202_LED_DRIVER_CONTROL_INPUT_18' J2-72 U202-18 NET 'J2_RX6_P_U202_LED_DRIVER_CONTROL_INPUT_19' J2-78 U202-19 NET 'J2_RX7_P_U202_LED_DRIVER_CONTROL_INPUT_20' J2-84 U202-20 NET 'J2_RX8_P_U202_LED_DRIVER_CONTROL_INPUT_21' J2-90 U202-21 # # CONNECT J13 LED CATHODES 1-4 TO THE U202 LED DRIVER CHIP # NET 'J13_LED_1_CATHODE_PUSH_SIGNAL' U202-7 J13-LED1CTH NET 'J13_LED_2_CATHODE_PUSH_SIGNAL' U202-8 J13-LED2CTH NET 'J13_LED_3_CATHODE_PUSH_SIGNAL' U202-10 J13-LED3CTH NET 'J13_LED_4_CATHODE_PUSH_SIGNAL' U202-9 J13-LED4CTH # # CONNECT BULK_3V3 POWER TO THE R213-16 LED RESISTORS AND # CONNECT EACH R213-16 LED RESISTOR TO A J14 LED CATHODE # NET 'BULK_3V3' R213-1 NET 'J13_LED1_ANODE' R213-2 J13-LED1AND NET 'BULK_3V3' R214-1 NET 'J13_LED2_ANODE' R214-2 J13-LED2AND NET 'BULK_3V3' R216-1 NET 'J13_LED3_ANODE' R216-2 J13-LED3AND NET 'BULK_3V3' R215-1 NET 'J13_LED4_ANODE' R215-2 J13-LED4AND # # CONNECT J14 LED CATHODES 1-4 TO THE U202 LED DRIVER CHIP # NET 'J14_LED_1_CATHODE_PUSH_SIGNAL' U202-3 J14-LED1CTH NET 'J14_LED_2_CATHODE_PUSH_SIGNAL' U202-4 J14-LED2CTH NET 'J14_LED_3_CATHODE_PUSH_SIGNAL' U202-6 J14-LED3CTH NET 'J14_LED_4_CATHODE_PUSH_SIGNAL' U202-5 J14-LED4CTH # # CONNECT BULK_3V3 POWER TO THE R209-12 LED RESISTORS AND # CONNECT EACH R209-12 LED RESISTOR TO A J14 LED CATHODE # NET 'BULK_3V3' R209-2 NET 'J14_LED1_ANODE' R209-1 J14-LED1AND NET 'BULK_3V3' R210-2 NET 'J14_LED2_ANODE' R210-1 J14-LED2AND NET 'BULK_3V3' R212-2 NET 'J14_LED3_ANODE' R212-1 J14-LED3AND NET 'BULK_3V3' R211-2 NET 'J14_LED4_ANODE' R211-1 J14-LED4AND # # ISO_12V POWER LED # NET 'GROUND' LED17-1 NET 'LED17_ANODE' LED17-2 R217-1 NET 'LED17_DROP_ONE' R217-2 R218-1 NET 'LED17_DROP_TWO' R218-2 R219-1 NET 'ISO_12V' R219-2 # # POWER TO THE LED DRIVER CHIPS # # AND THEIR BYPASS CAPACITORS # # # CONNECT THE POWER AND GROUND AND DIR AND OE_B # TO THE U201 AND U202 LED DRIVER CHIPS # # THE INPUT "B" SIDE HAS 3V3 POWER. # THE OUTPUT "A" SIDE HAS 3V3 POWER. # # U201 POWER AND GROUND NET 'BULK_3V3' U201-1 NET 'BULK_3V3' U201-23 U201-24 NET 'GROUND' U201-11 U201-12 U201-13 # U201 DIR AND OE_B PINS: NET 'GROUND' U201-2 U201-22 # U202 POWER AND GROUND NET 'BULK_3V3' U202-1 NET 'BULK_3V3' U202-23 U202-24 NET 'GROUND' U202-11 U202-12 U202-13 # U201 DIR AND OE_B PINS: NET 'GROUND' U202-2 U202-22 # # BYPASS CAPACITORS FOR U201 & U202 LED DRIVER CHIPS # NET 'BULK_3V3' C201-1 C203-1 NET 'GROUND' C201-2 C203-2 NET 'BULK_3V3' C202-1 C204-1 NET 'GROUND' C202-2 C204-2 # # HARDWARE ADDRESS NETS # # HTM-0 KEY-IN NET LIST FILE # # # ORIGINAL REV. 9-MAR-2018 # CURRENT REV. 28-MAR-2018 # # # # # THIS NETS FILES CONTAINS ALL OF THE CONNECTIONS # ON THE HTM CARD THAT ARE ASSOCIATED WITH THE # ATCA HARDWARE ADDRESS SIGNALS. # # # # # SLOT NUMBER HARDWARE ADDRESS LINES # FROM THE ATCA BACKPLANE # NET 'HW_ADRS_0' P10-5 NET 'HW_ADRS_1' P10-6 NET 'HW_ADRS_2' P10-7 NET 'HW_ADRS_3' P10-8 NET 'HW_ADRS_4' P10-9 NET 'HW_ADRS_5' P10-10 NET 'HW_ADRS_6' P10-11 NET 'HW_ADRS_7' P10-12 # # FILTERS ON THE # SLOT NUMBER HARDWARE ADDRESS # NET 'HW_ADRS_1' C171-2 R171-1 NET 'HW_ADRS_3' C172-2 R172-1 NET 'HW_ADRS_0' C173-2 R173-1 NET 'HW_ADRS_2' C174-2 R174-1 NET 'HW_ADRS_4' C175-2 R175-1 NET 'HW_ADRS_6' C176-2 R176-1 NET 'HW_ADRS_5' C177-2 R177-1 NET 'HW_ADRS_7' C178-2 R178-1 NET 'GROUND' C171-1 C172-1 NET 'GROUND' C173-1 C174-1 NET 'GROUND' C175-1 C176-1 NET 'GROUND' C177-1 C178-1 NET 'BULK_3V3' R171-2 R172-2 NET 'BULK_3V3' R173-2 R174-2 NET 'BULK_3V3' R175-2 R176-2 NET 'BULK_3V3' R177-2 R178-2 # # SEND SLOT NUMBER HARDWARE # ADDRESS TO FPGA MEZZANINE # NET 'HW_ADRS_0' J3-83 NET 'HW_ADRS_1' J3-89 NET 'HW_ADRS_2' J3-53 NET 'HW_ADRS_3' J3-47 NET 'HW_ADRS_4' J3-77 NET 'HW_ADRS_5' J3-71 NET 'HW_ADRS_6' J3-59 NET 'HW_ADRS_7' J3-65 # # HTM CARD NET LIST FILE # # CLOCK GENERATION AND ASSOCIATED NETS # ----------------------------------------- # # # INITIAL REV. 4-FEB-2018 # CURRENT REV. 23-APR-2018 # # # THIS FILE HOLDS ALL OF THE NETS ASSOCIATED WITH THE # CLOCK GENERATION ON THE HTM CIRCUIT BOARD AND # ASSOCIATED CIRCUITS SUCH AS SPARE CRYSTAL OSCILLATOR # AND BUFFERS. # # # NOTE THAT ALL DIFFERENTIAL PAIRS IN THIS SECTION ARE # WIRED RIGHT-SIDE-UP EXCEPT FOR THE REF CLK FEED TO THE # SI LABS CHIP ON THE FPGA MEZZ. # # THE REF CLK FEED TO THE SI LABS CHIP ON THE FPGA MEZZ WILL # APPEAR TO BE WIRED UP-SIDE-DOWN BECAUSE OF THE WAY THAT # THEY DESIGNED THE FPGA MEZZ CARD, I.E. THEY HAVE A FLIP # IN THEIR NAMING, E.G. FPGA MEZZ PIN J3-40 IS LABELED # SI5328_CLK1_N BUT IT GOES TO PIN #1 OF THE SI5338 # WHICH IS ITS NON-INVERTING REF CLK INPUT. # # TO HELP KEEP THINGS STRAIGHT I PUT ALL THE CHIP PIN # NUMBER PIN NAME INFORMATION HERE: # # CDC LVD 1204 # # IN 0 DIR PIN 6 IN 1 DIR PIN 3 # IN 0 CMP PIN 7 IN 1 CMP PIN 4 # # OUT 0 DIR PIN 9 OUT 1 DIR PIN 11 # OUT 0 CMP PIN 10 OUT 1 CMP PIN 12 # # OUT 2 DIR PIN 13 OUT 3 DIR PIN 15 # OUT 2 CMP PIN 14 OUT 3 CMP PIN 16 # # 65 LVDS 2 # # IN DIR PIN 3 OUT PIN 5 # IN CMP PIN 4 VCC PIN 1 GND PIN 2 # # SFX-524G-CRN1 PLL # # OUTPUT_DIR U253-6 # OUTPUT_CMP U253-7 # # LOGIC CLK FEED TO THE FPGA 40.08 MHZ VIA FPGA MEZZ CARD # # J3-156 GOES TO FPGA PIN AE22 WHICH IS IO_L12P_T1_MRCC_11 # J3-158 GOES TO FPGA PIN AF22 WHICH IS IO_L12N_T1_MRCC_11 # # SI LABS 5338 REF CLK FEED 40.08 MHZ VIA FPGA MEZZ CARD # # J3-38 SI5328_CLK1_P U2-2 IN2 CMP # J3-40 SI5328_CLK1_N U2-1 IN1 DIR # # # # GENERATION OF THE 40.0787 MHZ CLOCK ON THE HTM # # # RECEIVE THE HUB #1 LHC REFERENCE CLOCK # NET 'HUB_1_REF_CLK_DIR' J23-C4 R261-1 U252-3 NET 'HUB_1_REF_CLK_CMP' J23-D4 R262-1 U252-4 NET 'HUB_1_REF_CLK_CMM' R261-2 R262-2 R263-2 R264-2 C254-1 NET 'CLK_3V3' U252-1 C253-1 R263-1 NET 'GROUND' U252-2 C253-2 R264-1 C254-2 NET 'RECVD_HUB_1_REF_CLK' U252-5 R265-1 # # 40.0787 MHZ PLL # NET 'BK_TRM_RCVD_HUB_1_REF_CLK' R265-2 U253-1 NET 'PLL_40_CLK_OUT_DIR' U253-6 R266-1 NET 'PLL_40_CLK_OUT_CMP' U253-7 R267-1 NET 'RC_PLL_40_CLK_OUT_DIR' R266-2 C256-1 NET 'RC_PLL_40_CLK_OUT_CMP' R267-2 C257-1 NET 'RAW_PLL_40_MHZ_LOCKED' U253-10 R268-1 NET 'PLL_40_MHZ_LOCKED_MON' J3-101 R268-2 NET 'CLK_3V3' U253-9 C258-1 C259-1 C260-1 NET 'GROUND' U253-2 U253-8 NET 'GROUND' C258-2 C259-2 C260-2 NET 'NO_CONN_PLL_PIN_3' U253-3 NET 'NO_CONN_PLL_PIN_4' U253-4 NET 'NO_CONN_PLL_PIN_5' U253-5 # # 40.0787 MHZ 4X BUFFER FANOUT # NET 'PLL_40_MHZ_SIGNAL_DIR' C256-2 U254-6 R271-1 NET 'PLL_40_MHZ_SIGNAL_CMP' C257-2 U254-7 R272-1 NET 'FANOUT_INPUT_CMM_REF' U254-8 U254-4 R271-2 R272-2 C255-1 NET 'GROUND' U254-1 C255-2 NET 'GROUND' U254-17 U254-18 U254-19 U254-20 NET 'CLK_2V5' U254-5 C262-1 C263-1 NET 'GROUND' C262-2 C263-2 NET 'FAN_40_MHZ_IN_SEL' U254-2 R273-1 NET 'FAN_40_MHZ_IN_2_BIAS' U254-3 R274-1 NET 'GROUND' R273-2 R274-2 NET 'NO_CONN_CLK_FANOUT_9' U254-9 NET 'NO_CONN_CLK_FANOUT_10' U254-10 # # 40.0787 MHZ FANOUT FEED TO FPGA GLOBAL LOGIC CLOCK # # THE 40.08 MHZ LOGIC CLOCK GOES TO THE FPGA MEZZ ON # ITS PINS J3-156 & J3-158. THESE CONNECT TO # FPGA PINS AE22 & AF22 WHICH ARE IO_L12P_T1_MRCC_11 # AND IO_L12N_T1_MRCC_11 BANK #11 MULTI REGION # 3V3 CLOCK INPUTS TO THE FPGA. # NET 'PRE_CAP_FPGA_40_MHZ_LOGIC_CLK_DIR' U254-13 C266-1 NET 'PRE_CAP_FPGA_40_MHZ_LOGIC_CLK_CMP' U254-14 C267-1 NET 'FPGA_40_MHZ_LOGIC_CLK_DIR' C266-2 J3-156 NET 'FPGA_40_MHZ_LOGIC_CLK_CMP' C267-2 J3-158 # # 40.0787 MHZ FANOUT FEED TO SILAB 5338A # # NOTE THAT BASED ON THE FPGA MEZZ CARD'S PIN NAMES # THERE WOULD APPEAR TO BE A POLARITY FLIP BUT THERE # IS NOT ONE. THE DIR OUTPUT FROM THE FANOUT CHIP # GOES TO THE REFERENCE DIR INPUT ON THE SI LABS SI5338. # # FPGA MEZZ PIN J3-40 GOES TO THE REF DIR INPUT ON SI5338. # NET 'PRE_CAP_40_MHZ_SILAB_DIR' U254-15 R275-1 C264-1 NET 'PRE_CAP_40_MHZ_SILAB_CMP' U254-16 R275-2 C265-1 NET 'REF_40_MHZ_TO_SILAB_DIR' C264-2 J3-40 NET 'REF_40_MHZ_TO_SILAB_CMP' C265-2 J3-38 # # 40.0787 MHZ FANOUT FEED TO FRONT PANEL MONITOR BUFFER # NET 'MON_CP_40_CLK_DIR' U254-11 NET 'MON_CP_40_CLK_CMP' U254-12 # # BUFFERED COPY OF THE HTM'S 40.0787 MHZ CLOCK # FOR FRONT PANEL MONITORING # NET 'MON_CP_40_CLK_DIR' U255-3 R276-1 NET 'MON_CP_40_CLK_CMP' U255-4 R276-2 NET 'BULK_3V3' U255-1 C268-1 NET 'GROUND' U255-2 C268-2 NET 'BUFD_MON_40_CLK' U255-5 R277-1 NET 'FP_MON_40_CLK_HUB_1' R277-2 J15-5 NET 'GROUND' J15-1 J15-2 J15-3 J15-4 # # RECEIVE THE HUB #2 LHC REFERENCE CLOCK JUST FOR MONITORING # NET 'HUB_2_REF_CLK_DIR' J23-C2 R251-1 U251-3 NET 'HUB_2_REF_CLK_CMP' J23-D2 R252-1 U251-4 NET 'HUB_2_REF_CLK_CMM' R251-2 R252-2 R253-2 R254-2 C252-1 NET 'BULK_3V3' U251-1 C251-1 R253-1 NET 'GROUND' U251-2 C251-2 R254-1 C252-2 NET 'RECVD_HUB_2_REF_CLK' U251-5 R255-1 R256-1 NET 'HUB_2_REF_MON_TO_FP' R255-2 J16-5 NET 'GROUND' J16-1 J16-2 J16-3 J16-4 NET 'HUB_2_REF_MON_TO_FPGA' R256-2 J2-53 # # SPARE LVDS OUTPUT CRYSTAL OSCILLATOR # # THE SPARE CLOCK GOES TO THE FPGA MEZZ ON # ITS PINS J2-156 & J2-158. THESE CONNECT TO # FPGA PINS AC28 & AD28 WHICH ARE IO_L12P_T1_MRCC_12 # AND IO_L12N_T1_MRCC_12 BANK #12 MULTI REGION # 3V3 CLOCK INPUTS TO THE FPGA. # NET 'XTAL_OSC_1_TO_CAP_DIR' U256-4 C271-1 NET 'XTAL_OSC_1_TO_CAP_CMP' U256-5 C272-1 NET 'SPARE_OSC_TO_FPGA_DIR' C271-2 J2-156 NET 'SPARE_OSC_TO_FPGA_CMP' C272-2 J2-158 NET 'CLK_3V3' U256-6 C269-2 C270-2 NET 'GROUND' U256-3 C269-1 C270-1 NET 'NO_CONN_U271_PIN_1' U256-1 NET 'NO_CONN_U271_PIN_2' U256-2 # # CLK_3V3 POWER FILTER FOR THE CLOCK GENERATION, # BUFFERS, CRYSTAL OSCILLATOR, AND ASSOCIATED COMPONENTS # NET 'BULK_3V3' C275-1 L251-2 NET 'CLK_3V3' L251-1 C276-1 C277-1 C261-1 NET 'GROUND' C275-2 C276-2 C277-2 C261-2 # # CLK_2V5 POWER FILTER FOR THE 40.08 MHZ CLOCK # LVDS FANOUT BUFFER U254 # NET 'BULK_2V5' C281-1 L281-2 NET 'CLK_2V5' L281-1 C282-1 NET 'GROUND' C281-2 C282-2 # # THIS IS THE KEY IN NET LIST FILE FOR THE # # HTM MODULE SHELF GROUND NETS # ---------------------============--------------- # # # ORIGINAL REV. 4-FEB-2018 # MOST RECENT REV. 4-APR-2018 # # # # THIS FILE INCLUDES THE SHELF_GND CONNECTIONS # # SHELF_GND STARTS WITH PIN #25 ON THE ZONE 1 BACKPLANE # CONNECTOR. THIS NET CONNECTION IS IN THE NETS FILE: # ATCA_POWER_ENTRY_NETS # # # SHELF_GND TO: FRONT ESD STRIP, RJ45S, ALIGNMENT PIN # NET 'SHELF_GND' ESD_STRIP_FO-3 NET 'SHELF_GND' J13-M1 J13-M2 J13-M3 J13-M4 J13-GC1 NET 'SHELF_GND' J14-M1 J14-M2 J14-M3 J14-M4 J14-GC1 NET 'SHELF_GND' K1-1 K1-2 K1-3 # # SHELF_GND TO: REAR ESD STRIP, LOGIC_GND # NET 'SHELF_GND' R958-2 NET 'ESD_STRIP_ONE' R958-1 ESD_STRIP_MB-1 NET 'SHELF_GND' R959-1 NET 'GROUND' R959-2 # # LOGIC GROUND TO ESD STRIP # NET 'ESD_STRIP_TWO' ESD_STRIP_MB-2 R957-1 NET 'GROUND' R957-2 # # SHELF_GND TO: HORZ AND VERT AIR BAFFELS # NET 'SHELF_GND' HORZ_AIR_BAFFLE-1 NET 'SHELF_GND' HORZ_AIR_BAFFLE-2 NET 'SHELF_GND' HORZ_AIR_BAFFLE-3 NET 'SHELF_GND' HORZ_AIR_BAFFLE-4 NET 'SHELF_GND' VERT_AIR_BAFFLE-1 NET 'SHELF_GND' VERT_AIR_BAFFLE-2 NET 'SHELF_GND' VERT_AIR_BAFFLE-3 # # HTM CARD NET LIST FILE # # BACKPLANE CONNECTOR J23 GROUND PINS # --------------------------------------- # # INITIAL REV. 1-FEB-2018 # CURRENT REV. 28-FEB-2018 # # # THIS FILE HOLDS ALL OF THE GROUND CONNECTIONS FOR # THE ZONE 2 CONNECTOR J23. # # EACH OF THE ZONE 2 ADFPLUS CONNECTORS HAS 80 GROUND # CONNECTIONS PINS AND 80 SIGNAL PINS THAT MAKE # UP 40 DIFFERENTIAL PAIRS. # # THERE CAN BE UP TO 5 ZONE 2 CONNECTORS WITH # REFERENCE DESIGNATORS J20 THROUGH J24. # # THE HTM CARD HAS ONLY ONE ZONE 2 CONNECTOR J23. # # # CONNECTOR J23 # NET 'GROUND' J23-AG1 J23-AG2 J23-AG3 J23-AG4 J23-AG5 NET 'GROUND' J23-AG6 J23-AG7 J23-AG8 J23-AG9 J23-AG10 NET 'GROUND' J23-BG1 J23-BG2 J23-BG3 J23-BG4 J23-BG5 NET 'GROUND' J23-BG6 J23-BG7 J23-BG8 J23-BG9 J23-BG10 NET 'GROUND' J23-CG1 J23-CG2 J23-CG3 J23-CG4 J23-CG5 NET 'GROUND' J23-CG6 J23-CG7 J23-CG8 J23-CG9 J23-CG10 NET 'GROUND' J23-DG1 J23-DG2 J23-DG3 J23-DG4 J23-DG5 NET 'GROUND' J23-DG6 J23-DG7 J23-DG8 J23-DG9 J23-DG10 NET 'GROUND' J23-EG1 J23-EG2 J23-EG3 J23-EG4 J23-EG5 NET 'GROUND' J23-EG6 J23-EG7 J23-EG8 J23-EG9 J23-EG10 NET 'GROUND' J23-FG1 J23-FG2 J23-FG3 J23-FG4 J23-FG5 NET 'GROUND' J23-FG6 J23-FG7 J23-FG8 J23-FG9 J23-FG10 NET 'GROUND' J23-GG1 J23-GG2 J23-GG3 J23-GG4 J23-GG5 NET 'GROUND' J23-GG6 J23-GG7 J23-GG8 J23-GG9 J23-GG10 NET 'GROUND' J23-HG1 J23-HG2 J23-HG3 J23-HG4 J23-HG5 NET 'GROUND' J23-HG6 J23-HG7 J23-HG8 J23-HG9 J23-HG10 # # UNUSED PINS # NET 'NO_CONN_J23_PIN_A7' J23-A7 NET 'NO_CONN_J23_PIN_B7' J23-B7 NET 'NO_CONN_J23_PIN_C7' J23-C7 NET 'NO_CONN_J23_PIN_D7' J23-D7 NET 'NO_CONN_J23_PIN_E7' J23-E7 NET 'NO_CONN_J23_PIN_F7' J23-F7 NET 'NO_CONN_J23_PIN_G7' J23-G7 NET 'NO_CONN_J23_PIN_H7' J23-H7 NET 'NO_CONN_J23_PIN_A8' J23-A8 NET 'NO_CONN_J23_PIN_B8' J23-B8 NET 'NO_CONN_J23_PIN_C8' J23-C8 NET 'NO_CONN_J23_PIN_D8' J23-D8 NET 'NO_CONN_J23_PIN_E8' J23-E8 NET 'NO_CONN_J23_PIN_F8' J23-F8 NET 'NO_CONN_J23_PIN_G8' J23-G8 NET 'NO_CONN_J23_PIN_H8' J23-H8 NET 'NO_CONN_J23_PIN_A9' J23-A9 NET 'NO_CONN_J23_PIN_B9' J23-B9 NET 'NO_CONN_J23_PIN_C9' J23-C9 NET 'NO_CONN_J23_PIN_D9' J23-D9 NET 'NO_CONN_J23_PIN_E9' J23-E9 NET 'NO_CONN_J23_PIN_F9' J23-F9 NET 'NO_CONN_J23_PIN_G9' J23-G9 NET 'NO_CONN_J23_PIN_H9' J23-H9 NET 'NO_CONN_J23_PIN_A10' J23-A10 NET 'NO_CONN_J23_PIN_B10' J23-B10 NET 'NO_CONN_J23_PIN_C10' J23-C10 NET 'NO_CONN_J23_PIN_D10' J23-D10 NET 'NO_CONN_J23_PIN_E10' J23-E10 NET 'NO_CONN_J23_PIN_F10' J23-F10 NET 'NO_CONN_J23_PIN_G10' J23-G10 NET 'NO_CONN_J23_PIN_H10' J23-H10 # # HTM CARD NET LIST FILE # # FPGA MEZZANINE J1 CONNECTOR POWER AND GROUND PINS # ----------------------------------------------------- # # INITIAL REV. 1-FEB-2018 # CURRENT REV. 5-FEB-2018 # # # THIS FILE HOLDS ALL OF THE POWER AND GROUND CONNECTIONS FOR # THE FPGA MEZZANINE CONNECTOR J1. # # # # FPGA CONNECTOR J1 POWER PINS # # # FPGA MEZZANINE J1 CONNECTOR 1V8 AND 3V3 PINS # NET 'MEZZ_1V8' J1-169 J1-171 NET 'MEZZ_1V8' J1-170 J1-172 # # FPGA CONNECTOR J1 GROUND PINS # NET 'GROUND' J1-51 J1-57 J1-63 J1-69 J1-75 NET 'GROUND' J1-81 J1-87 J1-93 J1-111 J1-117 NET 'GROUND' J1-123 J1-129 J1-135 J1-141 J1-147 NET 'GROUND' J1-153 J1-161 J1-163 J1-165 J1-167 NET 'GROUND' J1-52 J1-58 J1-64 J1-70 J1-76 NET 'GROUND' J1-82 J1-88 J1-94 J1-112 J1-118 NET 'GROUND' J1-124 J1-130 J1-136 J1-142 J1-148 NET 'GROUND' J1-154 J1-162 J1-164 J1-166 J1-168 # # HTM CARD NET LIST FILE # # FPGA MEZZANINE J2 CONNECTOR POWER AND GROUND PINS # ----------------------------------------------------- # # INITIAL REV. 1-FEB-2018 # CURRENT REV. 5-FEB-2018 # # # THIS FILE HOLDS ALL OF THE POWER AND GROUND CONNECTIONS FOR # THE FPGA MEZZANINE CONNECTOR J2. # # # # FPGA CONNECTOR J2 POWER PINS # NET 'ISO_12V' J2-165 J2-167 NET 'ISO_12V' J2-166 J2-168 # # FPGA CONNECTOR J2 BULK 3V3 PINS # NET 'BULK_3V3' J2-147 J2-148 # # FPGA MEZZANINE J2 CONNECTOR 1V8 AND 3V3 PINS # NET 'MEZZ_3V3' J2-111 J2-123 J2-135 J2-169 J2-171 NET 'MEZZ_3V3' J2-112 J2-124 J2-136 J2-170 J2-172 # # FPGA CONNECTOR J2 GROUND PINS # NET 'GROUND' J2-45 J2-93 J2-105 J2-117 J2-129 NET 'GROUND' J2-141 J2-153 J2-161 J2-163 NET 'GROUND' J2-46 J2-52 J2-58 J2-64 J2-70 NET 'GROUND' J2-76 J2-82 J2-88 J2-94 J2-106 NET 'GROUND' J2-118 J2-130 J2-142 J2-154 J2-162 NET 'GROUND' J2-164 # # HTM CARD NET LIST FILE # # FPGA MEZZANINE J3 CONNECTOR POWER AND GROUND PINS # ----------------------------------------------------- # # INITIAL REV. 1-FEB-2018 # CURRENT REV. 5-FEB-2018 # # # THIS FILE HOLDS ALL OF THE POWER AND GROUND CONNECTIONS FOR # THE FPGA MEZZANINE CONNECTOR J2. # # # # FPGA CONNECTOR J3 POWER PINS # # # FPGA MEZZANINE J3 CONNECTOR 1V8 AND 3V3 PINS # # # FPGA CONNECTOR J3 GROUND PINS # NET 'GROUND' J3-45 J3-51 J3-57 J3-63 J3-69 NET 'GROUND' J3-75 J3-93 J3-105 J3-111 J3-117 NET 'GROUND' J3-123 J3-153 J3-161 J3-163 J3-165 NET 'GROUND' J3-167 J3-169 J3-171 NET 'GROUND' J3-46 J3-52 J3-58 J3-64 J3-70 NET 'GROUND' J3-94 J3-106 J3-112 J3-118 J3-154 NET 'GROUND' J3-162 J3-164 J3-166 J3-168 J3-170 NET 'GROUND' J3-172 # # NET LIST FILE # # J23 COMBINED DATA FROM HUBS 1 AND 2 TO FPGA MEZZANINE J3 # -------------------------------------------------------------- # # # INITIAL REV. 16-FEB-2018 # CURRENT REV. 9-APRR-2018 # # # THIS NET LIST FILE CONTAINS THE CONNECTIONS FOR THE # HTM TO RECEIVE COMBINED DATA FROM BOTH HUB 1 AND HUB 2. # # # # # # NOTE THAT THE COMBINED DATA FROM HUB 1 # IS BEING RECEIVED WITH A POLARITY FLIP. # THE J23 CONNECTOR PINS HAVE BEEN SWAPPED. # NET 'COMBINED_DATA_FROM_HUB1_TO_MGT_RX_9_DIR' J23-H4 J1-5 (NET_TYPE, 'DIFF_PAIR_HS') NET 'COMBINED_DATA_FROM_HUB1_TO_MGT_RX_9_CMP' J23-G4 J1-7 (NET_TYPE, 'DIFF_PAIR_HS') # # J23 PIN G4 IS A DIR COMBINED DATA SIGNAL FROM THE BACKPLANE. # J23 PIN H4 IS A CMP COMBINED DATA SIGNAL FROM THE BACKPLANE. # # # NOTE THAT THE COMBINED DATA FROM HUB 2 # IS BEING RECEIVED WITH A POLARITY FLIP. # THE J23 CONNECTOR PINS HAVE BEEN SWAPPED. # NET 'COMBINED_DATA_FROM_HUB2_TO_MGT_RX_6_DIR' J23-H2 J3-8 (NET_TYPE, 'DIFF_PAIR_HS') NET 'COMBINED_DATA_FROM_HUB2_TO_MGT_RX_6_CMP' J23-G2 J3-6 (NET_TYPE, 'DIFF_PAIR_HS') # # J23 PIN G2 IS A DIR COMBINED DATA SIGNAL FROM THE BACKPLANE. # J23 PIN H2 IS A CMP COMBINED DATA SIGNAL FROM THE BACKPLANE. # # # MINI_POD NET LIST FILE # # MINI_POD RECEIVER AND TRANSMITTER NETS # ----------------------------------------------------- # # INITIAL REV. 16-FEB-2018 # CURRENT REV. 10-APR-2018 # # # THIS FILE HOLDS ALL NETS ASSOCIATED THE MINIPOD RECEIVER AND # AND TRANSMITTER MODULES # # # # MINIPOD RECEIVER MODULE NETS # -------==========----------- # # # CONNECT MINIPOD RECEIVER OUTPUTS FOR # FIBERS: 1,3,5,7,9,11 TO J1 MGT RECEIVERS # # FIBERS: 1, 7, 9 HAVE POLARITY FLIPS # # POLARITY FLIPS ARE IMPLEMENTED BY # SWAPPING PINS AT THE J1 CONNECTOR. # NET 'MINI_POD_REC_D1_TO_CAP_DIR' REC_MP-F1 C27-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D1_TO_CAP_CMP' REC_MP-F2 C28-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D1_TO_MGT_DIR' C27-2 J1-31 (NET_TYPE, 'DIFF_PAIR_HS') # POLARITY NET 'MINI_POD_CAP_D1_TO_MGT_CMP' C28-2 J1-29 (NET_TYPE, 'DIFF_PAIR_HS') # FLIP NET 'MINI_POD_REC_D3_TO_CAP_DIR' REC_MP-J2 C31-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D3_TO_CAP_CMP' REC_MP-H2 C32-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D3_TO_MGT_DIR' C31-2 J1-25 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D3_TO_MGT_CMP' C32-2 J1-27 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D5_TO_CAP_DIR' REC_MP-J4 C35-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D5_TO_CAP_CMP' REC_MP-H4 C36-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D5_TO_MGT_DIR' C35-2 J1-21 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D5_TO_MGT_CMP' C36-2 J1-23 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D7_TO_CAP_DIR' REC_MP-J6 C39-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D7_TO_CAP_CMP' REC_MP-H6 C40-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D7_TO_MGT_DIR' C39-2 J1-19 (NET_TYPE, 'DIFF_PAIR_HS') # POLARITY NET 'MINI_POD_CAP_D7_TO_MGT_CMP' C40-2 J1-17 (NET_TYPE, 'DIFF_PAIR_HS') # FLIP NET 'MINI_POD_REC_D9_TO_CAP_DIR' REC_MP-J8 C43-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D9_TO_CAP_CMP' REC_MP-H8 C44-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D9_TO_MGT_DIR' C43-2 J1-15 (NET_TYPE, 'DIFF_PAIR_HS') # POLARITY NET 'MINI_POD_CAP_D9_TO_MGT_CMP' C44-2 J1-13 (NET_TYPE, 'DIFF_PAIR_HS') # FLIP NET 'MINI_POD_REC_D11_TO_CAP_DIR' REC_MP-F9 C47-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D11_TO_CAP_CMP' REC_MP-F8 C48-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D11_TO_MGT_DIR' C47-2 J1-9 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D11_TO_MGT_CMP' C48-2 J1-11 (NET_TYPE, 'DIFF_PAIR_HS') # # CONNECT MINIPOD RECEIVER OUTPUTS FOR # FIBERS: 0,2,4,6,8,10 TO J3 MGT RECEIVERS # # FIBER 2 HAS POLARITY FLIP # # POLARITY FLIPS ARE IMPLEMENTED BY # SWAPPING PINS AT THE J3 CONNECTOR. # NET 'MINI_POD_REC_D10_TO_CAP_DIR' REC_MP-D9 C45-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D10_TO_CAP_CMP' REC_MP-D8 C46-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D10_TO_MGT_DIR' C45-2 J3-12 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D10_TO_MGT_CMP' C46-2 J3-10 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D8_TO_CAP_DIR' REC_MP-A8 C41-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D8_TO_CAP_CMP' REC_MP-B8 C42-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D8_TO_MGT_DIR' C41-2 J3-16 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D8_TO_MGT_CMP' C42-2 J3-14 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D6_TO_CAP_DIR' REC_MP-A6 C37-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D6_TO_CAP_CMP' REC_MP-B6 C38-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D6_TO_MGT_DIR' C37-2 J3-20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D6_TO_MGT_CMP' C38-2 J3-18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D4_TO_CAP_DIR' REC_MP-A4 C33-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D4_TO_CAP_CMP' REC_MP-B4 C34-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D4_TO_MGT_DIR' C33-2 J3-24 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D4_TO_MGT_CMP' C34-2 J3-22 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D2_TO_CAP_DIR' REC_MP-A2 C29-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D2_TO_CAP_CMP' REC_MP-B2 C30-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D2_TO_MGT_DIR' C29-2 J3-26 (NET_TYPE, 'DIFF_PAIR_HS') # POLARITY NET 'MINI_POD_CAP_D2_TO_MGT_CMP' C30-2 J3-28 (NET_TYPE, 'DIFF_PAIR_HS') # FLIP NET 'MINI_POD_REC_D0_TO_CAP_DIR' REC_MP-D1 C25-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_REC_D0_TO_CAP_CMP' REC_MP-D2 C26-1 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D0_TO_MGT_DIR' C25-2 J3-32 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_CAP_D0_TO_MGT_CMP' C26-2 J3-30 (NET_TYPE, 'DIFF_PAIR_HS') # # RECEIVER MINIPOD GROUND PIN CONNECTIONS # NET 'GROUND' REC_MP-A1 REC_MP-B1 NET 'GROUND' REC_MP-A3 REC_MP-B3 NET 'GROUND' REC_MP-A5 REC_MP-B5 NET 'GROUND' REC_MP-A7 REC_MP-B7 NET 'GROUND' REC_MP-A9 REC_MP-B9 NET 'GROUND' REC_MP-C1 REC_MP-C2 NET 'GROUND' REC_MP-C8 REC_MP-C9 NET 'GROUND' REC_MP-D3 REC_MP-D7 NET 'GROUND' REC_MP-E1 REC_MP-E2 NET 'GROUND' REC_MP-E8 REC_MP-E9 NET 'GROUND' REC_MP-F3 REC_MP-F7 NET 'GROUND' REC_MP-G1 REC_MP-G2 NET 'GROUND' REC_MP-G8 REC_MP-G9 NET 'GROUND' REC_MP-H1 REC_MP-J1 NET 'GROUND' REC_MP-H3 REC_MP-J3 NET 'GROUND' REC_MP-H5 REC_MP-J5 NET 'GROUND' REC_MP-H7 REC_MP-J7 NET 'GROUND' REC_MP-H9 REC_MP-J9 NET 'GROUND' REC_MP-SCRW1 REC_MP-SCRW2 # # RECEIVER MODULE TWS BUS ADDRESS SIGNALS # # ADDRESS 0 NET 'GROUND' REC_MP-G3 # ADDRESS 1 NET 'GROUND' REC_MP-E3 # ADDRESS 2 NET 'GROUND' REC_MP-C3 # # RECEIVER: RESET, SDA, SCL, AND INTERRUPT SIGNALS # # PULL-UP RESISTORS AND FPGA MEZZ CONNECTIONS # NET 'MP_REC_INTR' REC_MP-D6 R445-1 J3-80 NET 'MP_REC_SDA' REC_MP-D4 R446-1 J3-78 NET 'MP_REC_SCL' REC_MP-E6 R447-1 J3-74 NET 'MP_REC_RESET' REC_MP-E4 R448-1 J3-72 NET 'MP_REC_3V3' R445-2 R446-2 R447-2 R448-2 # # RECEIVER MINIPOD POWER SUPPLY NETS # NET 'MP_REC_3V3' REC_MP-C4 REC_MP-C5 REC_MP-C6 NET 'MP_REC_2V5' REC_MP-F4 NET 'MP_REC_2V5' REC_MP-G4 REC_MP-G5 REC_MP-G6 # # RECEIVER MINIPOD 2.5 VOLT POWER FILTER NET 'BULK_2V5' L431-1 C431-1 C432-2 C433-1 NET 'GROUND' C431-2 C432-1 C433-2 NET 'MP_REC_2V5' L431-2 C434-2 C435-1 C436-1 NET 'GROUND' C434-1 C435-2 R431-1 NET 'MP_REC_2V5_FLT_RES' C436-2 R431-2 # # RECEIVER MINIPOD 3.3 VOLT POWER FILTER NET 'BULK_3V3' L441-1 C441-1 C442-2 C443-1 NET 'GROUND' C441-2 C442-1 C443-2 NET 'MP_REC_3V3' L441-2 C444-2 C445-1 C446-1 NET 'GROUND' C444-1 C445-2 R441-1 NET 'MP_REC_3V3_FLT_RES' C446-2 R441-2 # # NOW THE DO NOT CONNECT PINS # ON THE RECEIVER MINIPOD # NET 'NO_CONN_REC_MP_C7' REC_MP-C7 NET 'NO_CONN_REC_MP_D5' REC_MP-D5 NET 'NO_CONN_REC_MP_E5' REC_MP-E5 NET 'NO_CONN_REC_MP_E7' REC_MP-E7 NET 'NO_CONN_REC_MP_F5' REC_MP-F5 NET 'NO_CONN_REC_MP_F6' REC_MP-F6 NET 'NO_CONN_REC_MP_G7' REC_MP-G7 ########################################### # # # RECEIVE ABOVE TRANSMIT BELOW # # # ########################################### # # # MINIPOD TRANSMITTER MODULE NETS # -------=============----------- # # CONNECT MINIPOD TRANSMITTER DATA INPUTS FOR # FIBERS 0 THROUGH 3 TO J1 MGT TRANSMITTERS # # FIBER 0 HAS A POLARITY FLIPS # # POLARITY FLIPS ARE IMPLEMENTED BY # SWAPPING PINS AT THE J1 CONNECTOR. # NET 'MINI_POD_TRANS_D2_DIR' TRANS_MP-A2 J1-18 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_TRANS_D2_CMP' TRANS_MP-B2 J1-20 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_TRANS_D0_DIR' TRANS_MP-D1 J1-24 (NET_TYPE, 'DIFF_PAIR_HS') # POLARITY NET 'MINI_POD_TRANS_D0_CMP' TRANS_MP-D2 J1-22 (NET_TYPE, 'DIFF_PAIR_HS') # FLIP NET 'MINI_POD_TRANS_D1_DIR' TRANS_MP-F1 J1-26 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_TRANS_D1_CMP' TRANS_MP-F2 J1-28 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_TRANS_D3_DIR' TRANS_MP-H2 J1-30 (NET_TYPE, 'DIFF_PAIR_HS') NET 'MINI_POD_TRANS_D3_CMP' TRANS_MP-J2 J1-32 (NET_TYPE, 'DIFF_PAIR_HS') # # TRANSMITTER MINIPOD GROUND PIN CONNECTIONS # NET 'GROUND' TRANS_MP-A1 TRANS_MP-B1 NET 'GROUND' TRANS_MP-A3 TRANS_MP-B3 NET 'GROUND' TRANS_MP-A5 TRANS_MP-B5 NET 'GROUND' TRANS_MP-A7 TRANS_MP-B7 NET 'GROUND' TRANS_MP-A9 TRANS_MP-B9 NET 'GROUND' TRANS_MP-C1 TRANS_MP-C2 NET 'GROUND' TRANS_MP-C8 TRANS_MP-C9 NET 'GROUND' TRANS_MP-D3 TRANS_MP-D7 NET 'GROUND' TRANS_MP-E1 TRANS_MP-E2 NET 'GROUND' TRANS_MP-E8 TRANS_MP-E9 NET 'GROUND' TRANS_MP-F3 TRANS_MP-F7 NET 'GROUND' TRANS_MP-G1 TRANS_MP-G2 NET 'GROUND' TRANS_MP-G8 TRANS_MP-G9 NET 'GROUND' TRANS_MP-H1 TRANS_MP-J1 NET 'GROUND' TRANS_MP-H3 TRANS_MP-J3 NET 'GROUND' TRANS_MP-H5 TRANS_MP-J5 NET 'GROUND' TRANS_MP-H7 TRANS_MP-J7 NET 'GROUND' TRANS_MP-H9 TRANS_MP-J9 NET 'GROUND' TRANS_MP-SCRW1 TRANS_MP-SCRW2 # # TRANSMITTER MODULE TWS BUS ADDRESS SIGNALS # # ADDRESS 0 NET 'GROUND' TRANS_MP-G3 # ADDRESS 1 NET 'GROUND' TRANS_MP-E3 # ADDRESS 2 NET 'GROUND' TRANS_MP-C3 # # TRANSMITTER: RESET, SDA, SCL, AND INTERRUPT SIGNALS # # PULL-UP RESISTORS AND FPGA MEZZ CONNECTIONS # NET 'MP_TRANS_INTR' TRANS_MP-D6 R425-1 J3-66 NET 'MP_TRANS_SDA' TRANS_MP-D4 R426-1 J3-60 NET 'MP_TRANS_SCL' TRANS_MP-E6 R427-1 J3-54 NET 'MP_TRANS_RESET' TRANS_MP-E4 R428-1 J3-48 NET 'MP_TRANS_3V3' R425-2 R426-2 R427-2 R428-2 # # TRANSMITTER MINIPOD POWER SUPPLY NETS # NET 'MP_TRANS_3V3' TRANS_MP-C4 TRANS_MP-C5 TRANS_MP-C6 NET 'MP_TRANS_2V5' TRANS_MP-F4 NET 'MP_TRANS_2V5' TRANS_MP-G4 TRANS_MP-G5 TRANS_MP-G6 # # TRANSMITTER MINIPOD 2.5 VOLT POWER FILTER NET 'BULK_2V5' L411-1 C411-1 C412-2 C413-1 NET 'GROUND' C411-2 C412-1 C413-2 NET 'MP_TRANS_2V5' L411-2 C414-2 C415-1 C416-1 NET 'GROUND' C414-1 C415-2 R411-1 NET 'MP_TRANS_2V5_FLT_RES' C416-2 R411-2 # # TRANSMITTER MINIPOD 3.3 VOLT POWER FILTER NET 'BULK_3V3' L421-1 C421-1 C422-2 C423-1 NET 'GROUND' C421-2 C422-1 C423-2 NET 'MP_TRANS_3V3' L421-2 C424-2 C425-1 C426-1 NET 'GROUND' C424-1 C425-2 R421-1 NET 'MP_TRANS_3V3_FLT_RES' C426-2 R421-2 # # NOW THE DO NOT CONNECT PINS # ON THE TRANSMITTER MINIPOD # NET 'NO_CONN_TRANS_MP_C7' TRANS_MP-C7 NET 'NO_CONN_TRANS_MP_D5' TRANS_MP-D5 NET 'NO_CONN_TRANS_MP_E5' TRANS_MP-E5 NET 'NO_CONN_TRANS_MP_E7' TRANS_MP-E7 NET 'NO_CONN_TRANS_MP_F5' TRANS_MP-F5 NET 'NO_CONN_TRANS_MP_F6' TRANS_MP-F6 NET 'NO_CONN_TRANS_MP_G7' TRANS_MP-G7 # # WE ARE ONLY USING 4 OF THE 12 CHANNELS/FIBERS # IN THE TRANSMITTER MINIPOD BECAUSE WE ONLY # HAVE 4 MGT TRANSMITTERS AVAILABLE TO DRIVE THE # TRANSMITTER MINIPOD. # # THE 4 FIBERS THAT WE ARE USING ARE # MINIPOD FIBER NUMBERS: 0, 1, 2, 3 # # THE DATA INPUT PINS FOR THE OTHER 8 FIBERS ARE # NOT CONNECTED IN THE HTM DESIGN AND THUS NEED TO # BE "NO_CONN" PINS IN THE HTM NETLIST. # NET 'NO_CONN_TRANS_MP_A4' TRANS_MP-A4 NET 'NO_CONN_TRANS_MP_B4' TRANS_MP-B4 NET 'NO_CONN_TRANS_MP_H4' TRANS_MP-H4 NET 'NO_CONN_TRANS_MP_J4' TRANS_MP-J4 NET 'NO_CONN_TRANS_MP_A6' TRANS_MP-A6 NET 'NO_CONN_TRANS_MP_B6' TRANS_MP-B6 NET 'NO_CONN_TRANS_MP_H6' TRANS_MP-H6 NET 'NO_CONN_TRANS_MP_J6' TRANS_MP-J6 NET 'NO_CONN_TRANS_MP_A8' TRANS_MP-A8 NET 'NO_CONN_TRANS_MP_B8' TRANS_MP-B8 NET 'NO_CONN_TRANS_MP_H8' TRANS_MP-H8 NET 'NO_CONN_TRANS_MP_J8' TRANS_MP-J8 NET 'NO_CONN_TRANS_MP_D8' TRANS_MP-D8 NET 'NO_CONN_TRANS_MP_D9' TRANS_MP-D9 NET 'NO_CONN_TRANS_MP_F8' TRANS_MP-F8 NET 'NO_CONN_TRANS_MP_F9' TRANS_MP-F9 # # BULK_3V3 SUPPLY # # HTM NET LIST FILE # --------------------- # # # ORIGINAL REV. 4-FEB-2018 # CURRENT REV. 5-APR-2018 # # # # THIS FILE HOLDS ALL OF THE NETS FOR THE # BULK_3V3 SUPPLY. # # THIS IS A 3 AMPS. # # THIS HTM CARD SUPPLY USES A LT1764A LINEAR # REGULATOR FOR THIS SUPPLY. # # # CONNECT THE REGULATOR'S V_INPUT, V_OUTPUT, AND GROUND TERMINALS: # NET 'FLTR_12V_INPUT_ONE' U101-2 NET 'BULK_3V3' U101-4 NET 'GROUND' U101-3 # # CONNECT THE REGULATOR'S 35 THERMAL PAD VIAS + 4 HEATSINK VIAS # NET 'GROUND' U101-6 U101-7 U101-8 U101-9 U101-10 NET 'GROUND' U101-11 U101-12 U101-13 U101-14 U101-15 NET 'GROUND' U101-16 U101-17 U101-18 U101-19 U101-20 NET 'GROUND' U101-21 U101-22 U101-23 U101-24 U101-25 NET 'GROUND' U101-26 U101-27 U101-28 U101-29 U101-30 NET 'GROUND' U101-31 U101-32 U101-33 U101-34 U101-35 NET 'GROUND' U101-36 U101-37 U101-38 U101-39 U101-40 NET 'GROUND' U101-41 U101-42 U101-43 U101-44 # # CONNECT THIS REGULATOR'S INPUT FILTER: # NET 'FLTR_12V_INPUT_ONE' C101-2 C102-2 C106-1 C107-1 NET 'GROUND' C101-1 C102-1 C106-2 C107-2 # # CONNECT THIS REGULATOR'S OUTPUT FILTER: # NET 'BULK_3V3' C104-1 C105-1 DZ101-1 NET 'GROUND' C104-2 C105-2 DZ101-2 # # CONNECT THIS REGULATOR'S SHUT_DOWN_B TERMINAL: # NET 'BULK_3V3_SHDN_B' U101-1 R101-2 NET 'FLTR_12V_INPUT_ONE' R101-1 # # CONNECT THIS REGULATOR'S SENSE_ADJUST TERMINAL: # NET 'BULK_3V3_ADJUST' U101-5 R103-2 C103-1 NET 'BULK_3V3' R102-2 NET 'BULK_3V3_TRM_TOP' R102-1 R103-1 C103-2 NET 'BULK_3V3_TRM_BOT' R104-1 R103-3 NET 'GROUND' R104-2 # # INPUT FILTER FOR VOLTAGE DROP AND HIGH FREQUENCY NOISE # NET 'ISO_12V' R105-1 C100-2 NET 'FLTR_STEP_1_ONE' R105-2 R106-1 NET 'FLTR_STEP_2_ONE' R106-2 L101-1 NET 'FLTR_12V_INPUT_ONE' L101-2 NET 'GROUND' C100-1 # # BULK_2V5 SUPPLY # # HTM NET LIST FILE # --------------------- # # # ORIGINAL REV. 26-FEB-2018 # CURRENT REV. 5-APR-2018 # # # # THIS FILE HOLDS ALL OF THE NETS FOR THE # BULK_2V5 SUPPLY. # # THIS IS A 3 AMPS. # # THIS HTM CARD SUPPLY USES A LT1764A LINEAR # REGULATOR FOR THIS SUPPLY. # # # CONNECT THE REGULATOR'S V_INPUT, V_OUTPUT, AND GROUND TERMINALS: # NET 'FLTR_12V_INPUT_TWO' U111-2 NET 'BULK_2V5' U111-4 NET 'GROUND' U111-3 # # CONNECT THE REGULATOR'S 35 THERMAL PAD VIAS + 4 HEATSINK VIAS # NET 'GROUND' U111-6 U111-7 U111-8 U111-9 U111-10 NET 'GROUND' U111-11 U111-12 U111-13 U111-14 U111-15 NET 'GROUND' U111-16 U111-17 U111-18 U111-19 U111-20 NET 'GROUND' U111-21 U111-22 U111-23 U111-24 U111-25 NET 'GROUND' U111-26 U111-27 U111-28 U111-29 U111-30 NET 'GROUND' U111-31 U111-32 U111-33 U111-34 U111-35 NET 'GROUND' U111-36 U111-37 U111-38 U111-39 U111-40 NET 'GROUND' U111-41 U111-42 U111-43 U111-44 # # CONNECT THIS REGULATOR'S INPUT FILTER: # NET 'FLTR_12V_INPUT_TWO' C111-2 C112-2 C116-1 C117-1 NET 'GROUND' C111-1 C112-1 C116-2 C117-2 # # CONNECT THIS REGULATOR'S OUTPUT FILTER: # NET 'BULK_2V5' C114-1 C115-1 DZ111-1 NET 'GROUND' C114-2 C115-2 DZ111-2 # # CONNECT THIS REGULATOR'S SHUT_DOWN_B TERMINAL: # NET 'BULK_2V5_SHDN_B' U111-1 R111-2 NET 'FLTR_12V_INPUT_TWO' R111-1 # # CONNECT THIS REGULATOR'S SENSE_ADJUST TERMINAL: # NET 'BULK_2V5_ADJUST' U111-5 R113-2 C113-1 NET 'BULK_2V5' R112-2 NET 'BULK_2V5_TRM_TOP' R112-1 R113-1 C113-2 NET 'BULK_2V5_TRM_BOT' R114-1 R113-3 NET 'GROUND' R114-2 # # INPUT FILTER FOR VOLTAGE DROP AND HIGH FREQUENCY NOISE # NET 'ISO_12V' R115-1 C110-2 NET 'FLTR_STEP_1_TWO' R115-2 R116-1 NET 'FLTR_STEP_2_TWO' R116-2 L111-1 NET 'FLTR_12V_INPUT_TWO' L111-2 NET 'GROUND' C110-1 # # HTM CARD NET LIST FILE # # FPGA VCCO POWER NETS # ----------------------- # # # INITIAL REV. 27-FEB-2018 # CURRENT REV. 28-FEB-2018 # # # THIS FILE HOLDS ALL OF THE NETS ASSOCIATED WITH # SUPPLYING VCCO POWER TO THE VARIOUS FPGA BANKS. # # MANY OF THE SELECT I/O BANKS ON THE FPGA MEZZ CARD # HAVE FIXED VCCO SUPPLIES RIGHT ON THAT CARD. # # THE 6 FPGA BANKS THAT PROVIDE THE SELECT I/O SIGNALS # THAT COME OFF OF THE FPGA MEZZ CARD HAVE THEIR VCCO # PINS ROUTED TO PINS ON THE MEZZ CARD'S J1, J2, J3 # CONNECTORS. # # I BELIEVE THAT THESE VCCO CONNECTIONS ARE: # # VCCO PINS # ----------------- # # BANKS: 10 J3-99 J3-100 3.3 VOLT MAX # 11 J3-159 J3-160 I/O BANKS # 12 J2-159 J2-160 # 13 J2-99 J2-100 # # # BANKS: 33 J1-99 J1-100 1.8 VOLT MAX # 34 J1-159 J1-160 I/O BANKS # # # THE INTENT IS TO POWER BANKS 10,11,12,13 FROM # THE 3.3 VOLT POWER THAT IS PROVIDED BY THE FPGA # MEZZ CARD, NET MEZZ_3V3.# # # THE INTENT IS TO POWER BANKS 33,34 FROM # THE 1.8 VOLT POWER THAT IS PROVIDED BY THE # FPGA MEZZ CARD, NET MEZZ_1V8. # # # THE CONNECTIONS TO THE VCCO PINS FOR THIS 6 # FPGA SELECT I/O BANKS WILL INCLUDE BYPASS # CAPACITORS ON THE HTM CARD (ALONG WITH MORE # BYPASS CAPACITORS ON THE FPGA MEZZ CARD. # # # # SUPPLY TO 3.3V SELECT I/O BANKS # NET 'MEZZ_3V3' J3-99 J3-100 # BANK 10 VCCO NET 'MEZZ_3V3' J3-159 J3-160 # BANK 11 VCCO NET 'MEZZ_3V3' J2-159 J2-160 # BANK 12 VCCO NET 'MEZZ_3V3' J2-99 J2-100 # BANK 13 VCCO # # DISTRIBUTED BYPASS CAPS ON THE MEZZ_3V3 BUS # NET 'MEZZ_3V3' C80-1 C79-1 C78-1 C77-1 NET 'GROUND' C80-2 C79-2 C78-2 C77-2 # # SUPPLY TO 1.8V SELECT I/O BANKS # NET 'MEZZ_1V8' J1-99 J1-100 # BANK 33 VCCO NET 'MEZZ_1V8' J1-159 J1-160 # BANK 34 VCCO # # DISTRIBUTED BYPASS CAPS ON THE MEZZ_1V8 BUS # NET 'MEZZ_1V8' C76-1 C75-1 C74-1 C73-1 NET 'GROUND' C76-2 C75-2 C74-2 C73-2 # # HTM CARD NET LIST FILE # # DISTRIBUTED BYPASS CAPACITOR NETS # ------------------------------------ # # # INITIAL REV. 28-FEB-2018 # CURRENT REV. 28-MAR-2018 # # # THIS FILE HOLDS ALL OF THE NETS ASSOCIATED WITH # DISTRIBUTED BYPASS CAPACITORS FOR THE POWER NETS: # # ISO_12V BULK_3V3 BULK_2V5 # # # # FOR THE ISO_12V POWER NET. # NET 'ISO_12V' C99-1 C98-1 C97-1 C96-1 NET 'GROUND' C99-2 C98-2 C97-2 C96-2 NET 'ISO_12V' C95-1 C94-1 C93-1 C92-1 NET 'GROUND' C95-2 C94-2 C93-2 C92-2 NET 'ISO_12V' C91-1 C90-1 NET 'GROUND' C91-2 C90-2 # # FOR THE BULK_3V3 POWER NET. # NET 'BULK_3V3' C89-1 C88-1 C87-1 C86-1 NET 'GROUND' C89-2 C88-2 C87-2 C86-2 NET 'BULK_3V3' C85-1 C84-1 C83-1 C82-1 NET 'GROUND' C85-2 C84-2 C83-2 C82-2 # # FOR THE BULK_2V5 POWER NET. # NET 'BULK_2V5' C69-1 C68-1 C67-1 C66-1 NET 'GROUND' C69-2 C68-2 C67-2 C66-2 # # HTM CARD NET LIST FILE # # MONITOR CONNECTOR J11 NETS # ------------------------------ # # # INITIAL REV. 2-MAR-2018 # CURRENT REV. 3-APR-2018 # # # THIS FILE HOLDS ALL OF THE POWER SUPPLY MONITORING NETS # ASSOCIATED WITH CONNECTOR J11. # # # STARTING AT THE LOW PIN NUMBER END OF THE J11 # CONNECTOR WE HAVE 5 POWER SUPPLY VOLTAGE MONITOR # CONNECTIONS. # NET 'ISO_12V' R501-1 NET 'BULK_3V3' R502-1 NET 'BULK_2V5' R503-1 NET 'MEZZ_3V3' R504-1 NET 'MEZZ_1V8' R505-1 NET 'ISO_12V_MONITOR_POINT' J11-1 R501-2 C501-1 NET 'BULK_3V3_MONITOR_POINT' J11-3 R502-2 C502-1 NET 'BULK_2V5_MONITOR_POINT' J11-5 R503-2 C503-1 NET 'MEZZ_3V3_MONITOR_POINT' J11-7 R504-2 C504-1 NET 'MEZZ_1V8_MONITOR_POINT' J11-9 R505-2 C505-1 NET 'GROUND' C501-2 C502-2 C503-2 C504-2 C505-2 NET 'GROUND' J11-2 J11-4 J11-6 J11-8 J11-10 # # HTM CARD NET LIST FILE # # LIFE BOAT SIGNAL NETS # ------------------------- # # # INITIAL REV. 3-APR-2018 # CURRENT REV. 4-APR-2018 # # # THIS FILE HOLDS ALL OF THE LIFE BOAT SIGNAL NETS. # # MOST OF THE LIFE BOAT NETS ON THE HTM CARD ARE # ASSOCIATED WITH THE CONNECTOR J11 WHICH ALSO # HANDLES THE POWER SUPPLY MONITORING CONNECTIONS. # # # THE LIFE BOAT SIGNALS INCLUDE: # # THE CPLD JTAG CONNECTION INCLUDING BULK_3V3 # POWER FOR THIS JTAG CONNECTION # # CPLD GPIO_3 # CPLD GPIO_4 # CPLD GPIO_5 # # JTAGENB FOR THE CPLD JTAG CONNECTION # BOOTMODE # RESIN RESET INPUT # CONFIGX CONFIGURE_X # VBAT_IN BACKUP BATTERY INPUT FOR REALTIME CLOCK AND FPGA KEY # # FOUR FPGA SELECT I/O SIGNALS ROUTED TO THE J11 CONNECTOR # # # # AT THE HIGH PIN NUMBER END OF THE J11 # CONNECTOR WE HAVE THE CPLD JTAG NETS # INCLUDING SOME LIMITED BULK_3V3 POWER. # NET 'CPLD_M_TMS' J3-82 J11-16 NET 'CPLD_M_TCK' J3-81 J11-18 NET 'CPLD_M_TDO' J3-88 J11-20 NET 'CPLD_M_TDI' J3-87 J11-22 NET 'GROUND' J11-13 J11-15 J11-17 J11-19 J11-21 NET 'BULK_3V3' R509-1 NET 'CPLD_M_JTAG_POWER' R509-2 J11-14 # # NETS FOR THE FOLLOWING 8 LIFE BOAT SIGNALS: # # CPLD GPIO_3 NET 'LB_CPLD_GPIO_3' J2-16 WTERM21-1 J11-40 R510-1 R511-1 # CPLD GPIO_4 NET 'LB_CPLD_GPIO_4' J2-18 WTERM22-1 J11-38 R520-1 R521-1 # CPLD GPIO_5 NET 'LB_CPLD_GPIO_5' J2-20 WTERM23-1 J11-36 R530-1 R531-1 # JTAGENB FOR THE CPLD JTAG CONNECTION NET 'LB_JTAGENB' J3-136 WTERM24-1 J11-34 R540-1 R541-1 # BOOTMODE NET 'LB_BOOTMODE' J3-135 WTERM25-1 J11-32 R550-1 R551-1 # RESIN RESET INPUT NET 'LB_RESIN' J3-130 WTERM26-1 J11-30 R560-1 R561-1 # CONFIGX CONFIGURE_X NET 'LB_CONFIGX' J3-129 WTERM27-1 J11-28 R570-1 R571-1 # VBAT_IN BACKUP BATTERY INPUT FOR REALTIME CLOCK AND FPGA KEY NET 'LB_VBAT_IN' J3-124 WTERM28-1 J11-26 R580-1 R581-1 # # CONNECT THE PULL-UP AND PULL_DOWN RESISTORS # FOR THESE 8 LIFE BOAT SIGNALS TO BULK_3V3 # AND GROUND. # NET 'BULK_3V3' R510-2 R520-2 R530-2 R540-2 NET 'GROUND' R511-2 R521-2 R531-2 R541-2 NET 'BULK_3V3' R550-2 R560-2 R570-2 R580-2 NET 'GROUND' R551-2 R561-2 R571-2 R581-2 # # CONNECT 4 SELECT I/O LINES FROM THE FPGA # TO THE J11 CONNECTOR AS LIFE BOATS. # NET 'LB_FPGA_SEL_IO_1' J3-107 J11-25 WTERM31-1 NET 'LB_FPGA_SEL_IO_2' J3-113 J11-29 WTERM32-1 NET 'LB_FPGA_SEL_IO_3' J3-119 J11-33 WTERM33-1 NET 'LB_FPGA_SEL_IO_4' J3-125 J11-37 WTERM34-1 NET 'GROUND' J11-39 J11-35 J11-31 J11-27 # # FPGA MEZZ NO CONN NET LIST FILE # # FPGA MEZZANINE J1, J2, AND J3 NO CONNECTION NETS # ----------------------------------------------------- # # INITIAL REV. 02-APR-2018 # CURRENT REV. 06-APR-2018 # # CONTAINS NETS FOR PINS OF J1, J2, AND J3 WHICH REMAIN UNCONNECTED # TO ANYTHING. # # J1 NO CONNECTION NETS # NET 'NO_CONN_AC4_MGT_RX8_P' J1-1 NET 'NO_CONN_AC3_MGT_RX8_N' J1-3 NET 'NO_CONN_F3_J1_TX20_N' J1-33 NET 'NO_CONN_F4_J1_TX20_P' J1-35 NET 'NO_CONN_K6_J1_TX21_N' J1-37 NET 'NO_CONN_J6_J1_TX21_P' J1-39 NET 'NO_CONN_J1_J1_TX0_P' J1-41 NET 'NO_CONN_H1_J1_TX0_N' J1-43 NET 'NO_CONN_L4_J1_B33_VRP' J1-45 NET 'NO_CONN_H2_J1_TX1_P' J1-47 NET 'NO_CONN_G1_J1_TX1_N' J1-49 NET 'NO_CONN_G2_J1_TX2_P' J1-53 NET 'NO_CONN_F2_J1_TX2_N' J1-55 NET 'NO_CONN_E3_J1_TX3_P' J1-59 NET 'NO_CONN_E2_J1_TX3_N' J1-61 NET 'NO_CONN_E1_J1_TX4_P' J1-65 NET 'NO_CONN_D1_J1_TX4_N' J1-67 NET 'NO_CONN_C2_J1_TX5_P' J1-71 NET 'NO_CONN_C1_J1_TX5_N' J1-73 NET 'NO_CONN_B2_J1_TX6_P' J1-77 NET 'NO_CONN_B1_J1_TX6_N' J1-79 NET 'NO_CONN_E6_J1_TX7_P' J1-83 NET 'NO_CONN_D5_J1_TX7_N' J1-85 NET 'NO_CONN_A3_J1_TX8_P' J1-89 NET 'NO_CONN_A2_J1_TX8_N' J1-91 NET 'NO_CONN_H4_J1_TX9_P' J1-95 NET 'NO_CONN_H3_J1_TX9_N' J1-97 NET 'NO_CONN_E7_J1_TX10_P' J1-101 NET 'NO_CONN_D6_J1_TX10_N' J1-103 NET 'NO_CONN_M10_J1_B34_VRP' J1-105 NET 'NO_CONN_F8_J1_TX11_P' J1-107 NET 'NO_CONN_F7_J1_TX11_N' J1-109 NET 'NO_CONN_C7_J1_TX12_P' J1-113 NET 'NO_CONN_B7_J1_TX12_N' J1-115 NET 'NO_CONN_J8_J1_TX13_P' J1-119 NET 'NO_CONN_H8_J1_TX13_N' J1-121 NET 'NO_CONN_B9_J1_TX14_P' J1-125 NET 'NO_CONN_A9_J1_TX14_N' J1-127 NET 'NO_CONN_B10_J1_TX15_P' J1-131 NET 'NO_CONN_A10_J1_TX15_N' J1-133 NET 'NO_CONN_E10_J1_TX16_P' J1-137 NET 'NO_CONN_D10_J1_TX16_N' J1-139 NET 'NO_CONN_K11_J1_TX17_P' J1-143 NET 'NO_CONN_K10_J1_TX17_N' J1-145 NET 'NO_CONN_F9_J1_TX18_P' J1-149 NET 'NO_CONN_E8_J1_TX18_N' J1-151 NET 'NO_CONN_G10_J1_TX19_P' J1-155 NET 'NO_CONN_F10_J1_TX19_N' J1-157 NET 'NO_CONN_E5_J1_RX20_N' J1-34 NET 'NO_CONN_F5_J1_RX20_P' J1-36 NET 'NO_CONN_U7_MGT_CLK4_P' J1-38 NET 'NO_CONN_U8_MGT_CLK4_N' J1-40 NET 'NO_CONN_L3_J1_RX0_P' J1-42 NET 'NO_CONN_L2_J1_RX0_N' J1-44 NET 'NO_CONN_L5_J1_B33_VRN' J1-46 NET 'NO_CONN_L1_J1_RX1_P' J1-48 NET 'NO_CONN_K1_J1_RX1_N' J1-50 NET 'NO_CONN_K3_J1_RX2_P' J1-54 NET 'NO_CONN_K2_J1_RX2_N' J1-56 NET 'NO_CONN_H6_J1_RX3_P' J1-60 NET 'NO_CONN_G6_J1_RX3_N' J1-62 NET 'NO_CONN_K5_J1_RX4_P' J1-66 NET 'NO_CONN_J5_J1_RX4_N' J1-68 NET 'NO_CONN_J4_J1_RX5_P' J1-72 NET 'NO_CONN_J3_J1_RX5_N' J1-74 NET 'NO_CONN_D4_J1_RX6_P' J1-78 NET 'NO_CONN_D3_J1_RX6_N' J1-80 NET 'NO_CONN_B5_J1_RX7_P' J1-84 NET 'NO_CONN_B4_J1_RX7_N' J1-86 NET 'NO_CONN_A5_J1_RX8_P' J1-90 NET 'NO_CONN_A4_J1_RX8_N' J1-92 NET 'NO_CONN_G5_J1_RX9_P' J1-96 NET 'NO_CONN_G4_J1_RX9_N' J1-98 NET 'NO_CONN_L8_J1_RX10_P' J1-102 NET 'NO_CONN_K8_J1_RX10_N' J1-104 NET 'NO_CONN_M12_J1_B34_VRN' J1-106 NET 'NO_CONN_L10_J1_RX11_P' J1-108 NET 'NO_CONN_L9_J1_RX11_N' J1-110 NET 'NO_CONN_L12_J1_RX12_P' J1-114 NET 'NO_CONN_K12_J1_RX12_N' J1-116 NET 'NO_CONN_H7_J1_RX13_P' J1-120 NET 'NO_CONN_G7_J1_RX13_N' J1-122 NET 'NO_CONN_J10_J1_RX14_P' J1-126 NET 'NO_CONN_J9_J1_RX14_N' J1-128 NET 'NO_CONN_C6_J1_RX15_P' J1-132 NET 'NO_CONN_B6_J1_RX15_N' J1-134 NET 'NO_CONN_J11_J1_RX16_P' J1-138 NET 'NO_CONN_H11_J1_RX16_N' J1-140 NET 'NO_CONN_H12_J1_RX17_P' J1-144 NET 'NO_CONN_G11_J1_RX17_N' J1-146 NET 'NO_CONN_E11_J1_RX18_P' J1-150 NET 'NO_CONN_D11_J1_RX18_N' J1-152 NET 'NO_CONN_D9_J1_RX19_P' J1-156 NET 'NO_CONN_D8_J1_RX19_N' J1-158 # # J2 NO CONNECTION NETS # NET 'NO_CONN_J2_NC_PIN_1' J2-1 NET 'NO_CONN_J2_NC_PIN_3' J2-3 NET 'NO_CONN_J2_NC_PIN_5' J2-5 NET 'NO_CONN_J2_NC_PIN_7' J2-7 NET 'NO_CONN_N29_J2_TX0_P' J2-41 NET 'NO_CONN_P29_J2_TX0_N' J2-43 NET 'NO_CONN_U22_J2_TX1_P' J2-47 NET 'NO_CONN_V22_J2_TX1_N' J2-49 NET 'NO_CONN_J2_NC_PIN_51' J2-51 NET 'NO_CONN_R30_J2_TX2_N' J2-55 NET 'NO_CONN_J2_NC_PIN_57' J2-57 NET 'NO_CONN_V23_J2_TX3_P' J2-59 NET 'NO_CONN_W24_J2_TX3_N' J2-61 NET 'NO_CONN_J2_NC_PIN_63' J2-63 NET 'NO_CONN_T30_J2_TX4_P' J2-65 NET 'NO_CONN_U30_J2_TX4_N' J2-67 NET 'NO_CONN_J2_NC_PIN_69' J2-69 NET 'NO_CONN_W25_J2_TX5_P' J2-71 NET 'NO_CONN_W26_J2_TX5_N' J2-73 NET 'NO_CONN_J2_NC_PIN_75' J2-75 NET 'NO_CONN_V28_J2_TX6_P' J2-77 NET 'NO_CONN_V29_J2_TX6_N' J2-79 NET 'NO_CONN_J2_NC_PIN_81' J2-81 NET 'NO_CONN_T29_J2_TX7_P' J2-83 NET 'NO_CONN_U29_J2_TX7_N' J2-85 NET 'NO_CONN_J2_NC_PIN_87' J2-87 NET 'NO_CONN_W29_J2_TX8_P' J2-89 NET 'NO_CONN_W30_J2_TX8_N' J2-91 NET 'NO_CONN_U25_J2_TX9_P' J2-95 NET 'NO_CONN_V26_J2_TX9_N' J2-97 NET 'NO_CONN_AA27_J2_TX10_P' J2-101 NET 'NO_CONN_AA28_J2_TX10_N' J2-103 NET 'NO_CONN_AC29_J2_TX11_P' J2-107 NET 'NO_CONN_AD29_J2_TX11_N' J2-109 NET 'NO_CONN_AE25_J2_TX12_P' J2-113 NET 'NO_CONN_AF25_J2_TX12_N' J2-115 NET 'NO_CONN_AD30_J2_TX13_P' J2-119 NET 'NO_CONN_AE30_J2_TX13_N' J2-121 NET 'NO_CONN_AF29_J2_TX14_P' J2-125 NET 'NO_CONN_AG29_J2_TX14_N' J2-127 NET 'NO_CONN_AF30_J2_TX15_P' J2-131 NET 'NO_CONN_AG30_J2_TX15_N' J2-133 NET 'NO_CONN_AH26_J2_TX16_P' J2-137 NET 'NO_CONN_AH27_J2_TX16_N' J2-139 NET 'NO_CONN_AJ30_J2_TX17_P' J2-143 NET 'NO_CONN_AK30_J2_TX17_N' J2-145 NET 'NO_CONN_AK27_J2_TX18_P' J2-149 NET 'NO_CONN_AK28_J2_TX18_N' J2-151 NET 'NO_CONN_AB27_J2_TX19_P' J2-155 NET 'NO_CONN_AC27_J2_TX19_N' J2-157 NET 'NO_CONN_J2_TEMP_DCDC1' J2-2 NET 'NO_CONN_J2_TEMP_DCDC2' J2-4 NET 'NO_CONN_J2_TEMP_PCB' J2-6 NET 'NO_CONN_J2_TEMP_ZYNQ' J2-8 NET 'NO_CONN_J2_TEMP_GPI00' J2-10 NET 'NO_CONN_J2_TEMP_GPI01' J2-12 NET 'NO_CONN_J2_TEMP_GPI02' J2-14 NET 'NO_CONN_J2_OTG2_ID' J2-22 NET 'NO_CONN_J2_USB2_VBUS' J2-24 NET 'NO_CONN_J2_USB2_D_N' J2-26 NET 'NO_CONN_J2_USB2_D_P' J2-28 NET 'NO_CONN_J2_VBUS2_V_EN' J2-30 NET 'NO_CONN_J2_VBUS1_V_EN' J2-32 NET 'NO_CONN_J2_OTG1_ID' J2-34 NET 'NO_CONN_J2_USB1_VBUS' J2-36 NET 'NO_CONN_J2_USB1_D_N' J2-38 NET 'NO_CONN_J2_USB1_D_P' J2-40 NET 'NO_CONN_P25_J2_RX0_P' J2-42 NET 'NO_CONN_P26_J2_RX0_N' J2-44 NET 'NO_CONN_N27_J2_RX1_N' J2-50 NET 'NO_CONN_P28_J2_RX2_N' J2-56 NET 'NO_CONN_P24_J2_RX3_N' J2-62 NET 'NO_CONN_T25_J2_RX4_N' J2-68 NET 'NO_CONN_R23_J2_RX5_N' J2-74 NET 'NO_CONN_V24_J2_RX6_N' J2-80 NET 'NO_CONN_T23_J2_RX7_N' J2-86 NET 'NO_CONN_V27_J2_RX8_N' J2-92 NET 'NO_CONN_U26_J2_RX9_P' J2-96 NET 'NO_CONN_U27_J2_RX9_N' J2-98 NET 'NO_CONN_Y26_J2_RX10_P' J2-102 NET 'NO_CONN_Y27_J2_RX10_N' J2-104 NET 'NO_CONN_AA29_J2_RX11_N' J2-110 NET 'NO_CONN_AA30_J2_RX12_N' J2-116 NET 'NO_CONN_AD26_J2_RX13_N' J2-122 NET 'NO_CONN_AB30_J2_RX14_N' J2-128 NET 'NO_CONN_AE26_J2_RX15_N' J2-134 NET 'NO_CONN_AG27_J2_RX16_N' J2-140 NET 'NO_CONN_AJ29_J2_RX17_N' J2-146 NET 'NO_CONN_AK26_J2_RX18_N' J2-152 # # J3 NO CONNECTION NETS # NET 'NO_CONN_AF13_J3_TX20_P' J3-33 NET 'NO_CONN_AE13_J3_TX20_N' J3-35 NET 'NO_CONN_AC7_J3_MGT_CLK1_P' J3-37 NET 'NO_CONN_AC8_J3_MGT_CLK1_N' J3-39 NET 'NO_CONN_AD13_J3_TX1_N' J3-49 NET 'NO_CONN_AH12_J3_TX2_N' J3-55 NET 'NO_CONN_AC12_J3_TX3_N' J3-61 NET 'NO_CONN_AA14_J3_TX4_N' J3-67 NET 'NO_CONN_AH13_J3_TX5_N' J3-73 NET 'NO_CONN_AE15_J3_TX6_N' J3-79 NET 'NO_CONN_AB14_J3_TX7_N' J3-85 NET 'NO_CONN_AC16_J3_TX8_N' J3-91 NET 'NO_CONN_AF15_J3_TX21_P' J3-95 NET 'NO_CONN_AG15_J3_TX21_N' J3-97 NET 'NO_CONN_AK18_J3_TX10_N' J3-103 NET 'NO_CONN_AK23_J3_TX11_N' J3-109 NET 'NO_CONN_AK20_J3_TX12_N' J3-115 NET 'NO_CONN_AK21_J3_TX13_N' J3-121 NET 'NO_CONN_AJ19_J3_TX14_N' J3-127 NET 'NO_CONN_AF19_J3_TX15_P' J3-131 NET 'NO_CONN_AG19_J3_TX15_N' J3-133 NET 'NO_CONN_AF23_J3_TX16_P' J3-137 NET 'NO_CONN_AF24_J3_TX16_N' J3-139 NET 'NO_CONN_AH23_J3_TX17_P' J3-143 NET 'NO_CONN_AH24_J3_TX17_N' J3-145 NET 'NO_CONN_AC24_J3_TX18_P' J3-149 NET 'NO_CONN_AD24_J3_TX18_N' J3-151 NET 'NO_CONN_AD23_J3_TX19_P' J3-155 NET 'NO_CONN_AE23_J3_TX19_N' J3-157 NET 'NO_CONN_AD5_J3_MGT_RX7_N' J3-2 NET 'NO_CONN_AD6_J3_MGT_RX7_P' J3-4 NET 'NO_CONN_AG14_J3_MGT_RX6_N' J3-34 NET 'NO_CONN_AF14_J3_MGT_RX6_P' J3-36 NET 'NO_CONN_AJ15_J3_RX0_P' J3-42 NET 'NO_CONN_AK15_J3_RX0_N' J3-44 NET 'NO_CONN_AJ13_J3_RX1_N' J3-50 NET 'NO_CONN_AK12_J3_RX2_N' J3-56 NET 'NO_CONN_AK16_J3_RX3_N' J3-62 NET 'NO_CONN_AF17_J3_RX4_N' J3-68 NET 'NO_CONN_J3_NC_PIN_76' J3-76 NET 'NO_CONN_AE18_J3_RX7_P' J3-84 NET 'NO_CONN_AE17_J3_RX7_N' J3-86 NET 'NO_CONN_AB16_J3_RX8_P' J3-90 NET 'NO_CONN_AB17_J3_RX8_N' J3-92 NET 'NO_CONN_AG17_J3_RX21_P' J3-96 NET 'NO_CONN_AG16_J3_RX21_N' J3-98 NET 'NO_CONN_AJ23_J3_RX10_P' J3-102 NET 'NO_CONN_AJ24_J3_RX10_N' J3-104 NET 'NO_CONN_AJ25_J3_RX11_P' J3-108 NET 'NO_CONN_AK25_J3_RX11_N' J3-110 NET 'NO_CONN_AG24_J3_RX12_P' J3-114 NET 'NO_CONN_AG25_J3_RX12_N' J3-116 NET 'NO_CONN_AC22_J3_RX13_P' J3-120 NET 'NO_CONN_AC23_J3_RX13_N' J3-122 NET 'NO_CONN_AD21_J3_RX14_P' J3-126 NET 'NO_CONN_AE21_J3_RX14_N' J3-128 NET 'NO_CONN_AA22_J3_RX15_P' J3-132 NET 'NO_CONN_AA23_J3_RX15_N' J3-134 NET 'NO_CONN_Y22_J3_RX16_P' J3-138 NET 'NO_CONN_Y23_J3_RX16_N' J3-140 NET 'NO_CONN_AA24_J3_RX17_P' J3-144 NET 'NO_CONN_AB24_J3_RX17_N' J3-146 NET 'NO_CONN_W21_J3_RX18_P' J3-150 NET 'NO_CONN_Y21_J3_RX18_N' J3-152 # # SUNDRY HTM-0 NETS # # HTM-0 KEY-IN NET LIST FILE # # # ORIGINAL REV. 31-JAN-2018 # CURRENT REV. 12-APR-2018 # # # # # CURRENTLY THIS SUNDRY NET LIST FILE CONTAINS: # # - GROUND THE FPGA MEZZANINE MOUNTING SCREW HOLES # # - GROUND THE GROUND RIVETS AND THE SCOPE LOOPS # # - SHIELD FILL RESISTOR FOR THE ISO_12V POWER SUPPLY # # # # # # GROUND THE FPGA MEZZANINE MOUNTING SCREW HOLES # NET 'GROUND' FPGA_MEZZ-1 FPGA_MEZZ-2 NET 'GROUND' FPGA_MEZZ-3 FPGA_MEZZ-4 # # GROUND THE: PERIMETER RIVETS # RIVETS ADJACENT TO HIGH-SPEED TRACES # NET 'GROUND' GR1-1 GR2-1 GR3-1 GR4-1 GR5-1 NET 'GROUND' GR6-1 GR7-1 GR8-1 GR9-1 GR10-1 NET 'GROUND' GR11-1 GR12-1 GR13-1 GR14-1 GR15-1 NET 'GROUND' GR16-1 NET 'GROUND' GR21-1 GR22-1 GR23-1 GR24-1 GR25-1 NET 'GROUND' GR26-1 GR27-1 GR28-1 GR29-1 GR30-1 NET 'GROUND' GR41-1 GR42-1 GR43-1 GR44-1 GR45-1 NET 'GROUND' GR46-1 GR47-1 GR48-1 NET 'GROUND' GR51-1 GR52-1 GR53-1 GR54-1 GR55-1 NET 'GROUND' GR56-1 GR57-1 GR58-1 GR59-1 GR60-1 NET 'GROUND' GR61-1 GR62-1 NET 'GROUND' GR71-1 GR72-1 GR73-1 GR74-1 GR75-1 NET 'GROUND' GR76-1 GR77-1 GR78-1 GR79-1 GR80-1 NET 'GROUND' GR81-1 GR82-1 GR83-1 NET 'GROUND' GR91-1 GR92-1 GR93-1 GR94-1 GR95-1 NET 'GROUND' GR96-1 GR97-1 GR98-1 GR99-1 GR100-1 NET 'GROUND' GR101-1 GR102-1 GR103-1 GR104-1 GR105-1 NET 'GROUND' GR111-1 GR112-1 GR113-1 GR114-1 GR115-1 NET 'GROUND' GR116-1 GR117-1 NET 'GROUND' GR121-1 GR122-1 GR123-1 GR124-1 GR125-1 NET 'GROUND' GR126-1 # # GROUND THE: SCOPE LOOPS # NET 'GROUND' WTERM1-1 WTERM2-1 NET 'GROUND' WTERM3-1 WTERM4-1 # # SHIELD FILL FOR THE ISO_12V POWER SUPPLY # NET 'SHIELD_ATCA_12V_MODULE' R961-1 NET 'GROUND' R961-2