# # FPGA Ethernet TRANS1 J14 Front Panel RJ-45 Nets # ----------------------------------------------------- # # # Original Rev. 4-Feb-2018 # Current Rev. 5-Feb-2018 # # # This Net List File contain the connections from the # FPGA Mezzanine to the front panel RJ-45 connector J14. # # J14 Lower or Left FPGA Mezzanine PHY 2 # Upper or Right FPGA Mezzanine PHY 1 # # # TRANS1 Left J14 Lower FPGA Mezzanine PHY 2 # Right J14 Upper FPGA Mezzanine PHY 1 # # # FPGA Mezzanine PHY 1 is Bank 501 of the ARM Cortex # FPGA Mezzanine PHY 2 is Bank 9 of the FPGA Fabric # # # # Recall the default setup of the 4 Lanes in each # Ethernet link: # # ATCA # Pri Sec ADFplus # ATCA Alt Mag Mag RJ-45 Conn. # Lane Lane Pin Pin Pin Column # ------- ------- ----- ----- ----- ------- # # A-Dir 0_Dir 1 7 1 A # 2 CT 8 # A-Cmp 0_Cmp 3 9 2 B # # # B-Dir 1_Dir 4 10 3 C # 5 CT 11 # B-Cmp 1_Cmp 6 12 6 D # # # C-Dir 2_Dir 24 18 4 E # 23 CT 17 # C-Cmp 2_Cmp 22 16 5 F # # # D-Dir 3_Dir 21 15 7 G # 20 CT 14 # D-Cmp 3_Cmp 19 13 8 H # # # # To Facilitate routing one may: # # - Swap transformers within a given side of a module. # For example R1, R3, R7, R9 could be # swapped with R4, R6, R10, R12. # # - It is probably best not to wire things up so that # for a given ethernet link some of its transformers # are in the R side of the module and some of its # transformers are in the L side of the module. # # - Swap the polarity of a given transformer. For # example one may swap R1 with R3 while also # swapping R7 with R9. # # # To facilitate understanding how the magnetics for a # given Ethernet link are wired up I'm putting the nets # for the Primary and Seconday sides of a given link # next to each other in this file. # # Note that the RC components attached to the magnetics # have net names that are independed of the Etherent link # that they service. These Center Tap (CT) nets are # listed at the end of this file. These magnetics RC # nets do not have to be disturbed if the Primary and # Seconday nets are swapped for routing. # # # #------------------------------------------------------------ # # # TRANS1 Right J14 Upper/Right FPGA Mezzanine PHY 1 # # # Primary Nets Trans 1 R NET 'PHY_1_TRD0_6_DIR' J2-23 TRANS1-R1 NET 'PHY_1_TRD0_6_CMP' J2-21 TRANS1-R3 NET 'PHY_1_TRD1_6_DIR' J2-19 TRANS1-R4 NET 'PHY_1_TRD1_6_CMP' J2-17 TRANS1-R6 NET 'PHY_1_TRD2_6_DIR' J2-15 TRANS1-R24 NET 'PHY_1_TRD2_6_CMP' J2-13 TRANS1-R22 NET 'PHY_1_TRD3_6_DIR' J2-11 TRANS1-R21 NET 'PHY_1_TRD3_6_CMP' J2-9 TRANS1-R19 # # Secondary Nets Trans 1 R Front Panel J14 Right-Upper NET 'J14_U_A_0_DIR' TRANS1-R7 J14-U1 NET 'J14_U_A_0_CMP' TRANS1-R9 J14-U2 NET 'J14_U_B_1_DIR' TRANS1-R10 J14-U3 NET 'J14_U_B_1_CMP' TRANS1-R12 J14-U6 NET 'J14_U_C_2_DIR' TRANS1-R18 J14-U4 NET 'J14_U_C_2_CMP' TRANS1-R16 J14-U5 NET 'J14_U_D_3_DIR' TRANS1-R15 J14-U7 NET 'J14_U_D_3_CMP' TRANS1-R13 J14-U8 # #------------------------------------------------------------ # # # TRANS1 Left J14 Lower/Left FPGA Mezzanine PHY 2 # # # Primary Nets Trans 1 L NET 'PHY_2_TRD0_6_DIR' J2-39 TRANS1-L1 NET 'PHY_2_TRD0_6_CMP' J2-37 TRANS1-L3 NET 'PHY_2_TRD1_6_DIR' J2-35 TRANS1-L4 NET 'PHY_2_TRD1_6_CMP' J2-33 TRANS1-L6 NET 'PHY_2_TRD2_6_DIR' J2-31 TRANS1-L24 NET 'PHY_2_TRD2_6_CMP' J2-29 TRANS1-L22 NET 'PHY_2_TRD3_6_DIR' J2-27 TRANS1-L21 NET 'PHY_2_TRD3_6_CMP' J2-25 TRANS1-L19 # # Secondary Nets Trans 1 L Front Panel J14 Left-Lower NET 'J14_L_A_0_DIR' TRANS1-L7 J14-L1 NET 'J14_L_A_0_CMP' TRANS1-L9 J14-L2 NET 'J14_L_B_1_DIR' TRANS1-L10 J14-L3 NET 'J14_L_B_1_CMP' TRANS1-L12 J14-L6 NET 'J14_L_C_2_DIR' TRANS1-L18 J14-L4 NET 'J14_L_C_2_CMP' TRANS1-L16 J14-L5 NET 'J14_L_D_3_DIR' TRANS1-L15 J14-L7 NET 'J14_L_D_3_CMP' TRANS1-L13 J14-L8 # #------------------------------------------------------------ # # # Primary Center Tap Nets Trans 1 R and L # NET 'TRANS1_R_A_0_PRI_CT' TRANS1-R2 C301-2 NET 'TRANS1_R_B_1_PRI_CT' TRANS1-R5 C304-2 NET 'TRANS1_R_C_2_PRI_CT' TRANS1-R23 C302-2 NET 'TRANS1_R_D_3_PRI_CT' TRANS1-R20 C303-2 NET 'GROUND' C301-1 C302-1 C303-1 C304-1 NET 'TRANS1_L_A_0_PRI_CT' TRANS1-L2 C307-2 NET 'TRANS1_L_B_1_PRI_CT' TRANS1-L5 C308-2 NET 'TRANS1_L_C_2_PRI_CT' TRANS1-L23 C306-2 NET 'TRANS1_L_D_3_PRI_CT' TRANS1-L20 C309-2 NET 'GROUND' C306-1 C307-1 C308-1 C309-1 # # Secondary Center Tap Nets Trans 1 R and L # NET 'TRANS1_R_A_0_SEC_CT' TRANS1-R8 R302-1 NET 'TRANS1_R_B_1_SEC_CT' TRANS1-R11 R304-1 NET 'TRANS1_R_C_2_SEC_CT' TRANS1-R17 R301-1 NET 'TRANS1_R_D_3_SEC_CT' TRANS1-R14 R303-1 NET 'TRANS1_L_SEC_CT_TIE' R301-2 R302-2 R303-2 R304-2 NET 'TRANS1_L_SEC_CT_TIE' C305-1 NET 'GROUND' C305-2 NET 'TRANS1_L_A_0_SEC_CT' TRANS1-L8 R307-1 NET 'TRANS1_L_B_1_SEC_CT' TRANS1-L11 R308-1 NET 'TRANS1_L_C_2_SEC_CT' TRANS1-L17 R306-1 NET 'TRANS1_L_D_3_SEC_CT' TRANS1-L14 R309-1 NET 'TRANS1_R_SEC_CT_TIE' R306-2 R307-2 R308-2 R309-2 NET 'TRANS1_R_SEC_CT_TIE' C310-1 NET 'GROUND' C310-2