#
#                HTM Card  Net List File
#
#                 Life Boat Signal Nets
#               -------------------------
#
#
#                                     Initial  Rev.   3-Apr-2018
#                                     Current  Rev.   4-Apr-2018
#
#
#   This file holds all of the  Life Boat Signal  nets.
#
#   Most of the Life Boat nets on the HTM Card are
#   associated with the connector J11   which also
#   handles the power supply monitoring connections.
#
#
#   The  Life Boat Signals  include:
#
#        The CPLD JTAG connection  including Bulk_3V3
#        power for this JTAG connection
#
#        CPLD GPIO_3
#        CPLD GPIO_4
#        CPLD GPIO_5
#
#        JTAGENB    for the CPLD JTAG Connection
#        BOOTMODE
#        RESIN      Reset Input
#        CONFIGX    Configure_X
#        VBAT_IN    Backup Battery Input   for Realtime Clock and FPGA Key
#
#        Four FPGA Select I/O signals routed to the J11 connector
#
#


#
#   At the high pin number end of the J11
#   connector we have the CPLD JTAG nets
#   including some limited Bulk_3V3 power.
#

NET  'CPLD_M_TMS'   J3-82   J11-16
NET  'CPLD_M_TCK'   J3-81   J11-18
NET  'CPLD_M_TDO'   J3-88   J11-20
NET  'CPLD_M_TDI'   J3-87   J11-22

NET  'GROUND'   J11-13   J11-15   J11-17   J11-19   J11-21


NET  'BULK_3V3'             R509-1
NET  'CPLD_M_JTAG_POWER'    R509-2   J11-14





#
#   Nets for the following 8  Life Boat Signals:
#

#     CPLD GPIO_3

NET  'LB_CPLD_GPIO_3'    J2-16    WTERM21-1    J11-40    R510-1    R511-1



#     CPLD GPIO_4

NET  'LB_CPLD_GPIO_4'    J2-18    WTERM22-1    J11-38    R520-1    R521-1



#     CPLD GPIO_5

NET  'LB_CPLD_GPIO_5'    J2-20    WTERM23-1    J11-36    R530-1    R531-1



#     JTAGENB  for the CPLD JTAG Connection

NET  'LB_JTAGENB'       J3-136    WTERM24-1    J11-34    R540-1    R541-1



#     BOOTMODE

NET  'LB_BOOTMODE'      J3-135    WTERM25-1    J11-32    R550-1    R551-1



#     RESIN    Reset Input

NET  'LB_RESIN'         J3-130    WTERM26-1    J11-30    R560-1    R561-1



#     CONFIGX    Configure_X

NET  'LB_CONFIGX'       J3-129    WTERM27-1    J11-28    R570-1    R571-1



#     VBAT_IN    Backup Battery Input   for Realtime Clock and FPGA Key

NET  'LB_VBAT_IN'       J3-124    WTERM28-1    J11-26    R580-1    R581-1





#
#   Connect the Pull-Up and Pull_Down  Resistors
#   for these 8 Life Boat Signals to Bulk_3V3
#   and Ground.
#

NET  'BULK_3V3'   R510-2   R520-2   R530-2   R540-2
NET  'GROUND'     R511-2   R521-2   R531-2   R541-2

NET  'BULK_3V3'   R550-2   R560-2   R570-2   R580-2
NET  'GROUND'     R551-2   R561-2   R571-2   R581-2





#
#   Connect 4 Select I/O lines from the FPGA
#   to the J11 Connector as Life Boats.
#

NET  'LB_FPGA_Sel_IO_1'     J3-107    J11-25    WTERM31-1

NET  'LB_FPGA_Sel_IO_2'     J3-113    J11-29    WTERM32-1

NET  'LB_FPGA_Sel_IO_3'     J3-119    J11-33    WTERM33-1

NET  'LB_FPGA_Sel_IO_4'     J3-125    J11-37    WTERM34-1


NET  'GROUND'   J11-39   J11-35   J11-31   J11-27