Found 172 pins for J1 which is of type Samtec_ASP-122953-01-J1 ------------------------------------------------------ Pins sorted by Pin Name 1 = No_Conn_AC4_MGT_RX8_P MGT_RX8_P | AC4 from line 20 of fpga_mezz_no_conn_nets 2 = MGT_TX_8_to_Cap_DIR MGT_TX8_P | AB2 from line 100 of fex_readout_to_hub_nets 3 = No_Conn_AC3_MGT_RX8_N MGT_RX8_N | AC3 from line 21 of fpga_mezz_no_conn_nets 4 = MGT_TX_8_to_Cap_CMP MGT_TX8_N | AB1 from line 101 of fex_readout_to_hub_nets 5 = Combined_Data_from_HUB1_to_MGT_RX_9_DIR MGT_RX9_P | AB6 from line 28 of fpga_j3_j23_combined_data_from_hubs_nets 6 = MGT_TX_9_to_Cap_DIR MGT_TX9_P | Y2 from line 107 of fex_readout_to_hub_nets 7 = Combined_Data_from_HUB1_to_MGT_RX_9_CMP MGT_RX9_N | AB5 from line 29 of fpga_j3_j23_combined_data_from_hubs_nets 8 = MGT_TX_9_to_Cap_CMP MGT_TX9_N | Y1 from line 108 of fex_readout_to_hub_nets 9 = Mini_POD_Cap_D11_to_MGT_DIR MGT_RX10_P | Y6 from line 77 of mini_POD_nets 10 = MGT_TX_10_to_Cap_DIR MGT_TX10_P | W4 from line 115 of fex_readout_to_hub_nets 11 = Mini_POD_Cap_D11_to_MGT_CMP MGT_RX10_N | Y5 from line 78 of mini_POD_nets 12 = MGT_TX_10_to_Cap_CMP MGT_TX10_N | W3 from line 116 of fex_readout_to_hub_nets 13 = Mini_POD_Cap_D9_to_MGT_CMP MGT_RX11_P | AA4 from line 70 of mini_POD_nets 14 = MGT_TX_11_to_Cap_DIR MGT_TX11_P | V2 from line 123 of fex_readout_to_hub_nets 15 = Mini_POD_Cap_D9_to_MGT_DIR MGT_RX11_N | AA3 from line 69 of mini_POD_nets 16 = MGT_TX_11_to_Cap_CMP MGT_TX11_N | V1 from line 124 of fex_readout_to_hub_nets 17 = Mini_POD_Cap_D7_to_MGT_CMP MGT_RX12_P | V6 from line 62 of mini_POD_nets 18 = Mini_POD_Trans_D2_DIR MGT_TX12_P | T2 from line 290 of mini_POD_nets 19 = Mini_POD_Cap_D7_to_MGT_DIR MGT_RX12_N | V5 from line 61 of mini_POD_nets 20 = Mini_POD_Trans_D2_CMP MGT_TX12_N | T1 from line 291 of mini_POD_nets 21 = Mini_POD_Cap_D5_to_MGT_DIR MGT_RX13_P | U4 from line 53 of mini_POD_nets 22 = Mini_POD_Trans_D0_CMP MGT_TX13_P | R4 from line 295 of mini_POD_nets 23 = Mini_POD_Cap_D5_to_MGT_CMP MGT_RX13_N | U3 from line 54 of mini_POD_nets 24 = Mini_POD_Trans_D0_DIR MGT_TX13_N | R3 from line 294 of mini_POD_nets 25 = Mini_POD_Cap_D3_to_MGT_DIR MGT_RX14_P | T6 from line 45 of mini_POD_nets 26 = Mini_POD_Trans_D1_DIR MGT_TX14_P | P2 from line 298 of mini_POD_nets 27 = Mini_POD_Cap_D3_to_MGT_CMP MGT_RX14_N | T5 from line 46 of mini_POD_nets 28 = Mini_POD_Trans_D1_CMP MGT_TX14_N | P1 from line 299 of mini_POD_nets 29 = Mini_POD_Cap_D1_to_MGT_CMP MGT_RX15_P | P6 from line 38 of mini_POD_nets 30 = Mini_POD_Trans_D3_DIR MGT_TX15_P | N4 from line 302 of mini_POD_nets 31 = Mini_POD_Cap_D1_to_MGT_DIR MGT_RX15_N | P5 from line 37 of mini_POD_nets 32 = Mini_POD_Trans_D3_CMP MGT_TX15_N | N3 from line 303 of mini_POD_nets 33 = No_Conn_F3_J1_TX20_N J1_TX20_N | F3 from line 23 of fpga_mezz_no_conn_nets 34 = No_Conn_E5_J1_RX20_N J1_RX20_N | E5 from line 98 of fpga_mezz_no_conn_nets 35 = No_Conn_F4_J1_TX20_P J1_TX20_P | F4 from line 24 of fpga_mezz_no_conn_nets 36 = No_Conn_F5_J1_RX20_P J1_RX20_P | F5 from line 99 of fpga_mezz_no_conn_nets 37 = No_Conn_K6_J1_TX21_N J1_TX21_N | K6 from line 26 of fpga_mezz_no_conn_nets 38 = No_Conn_U7_MGT_CLK4_P MGT_CLK4_P | U7 from line 101 of fpga_mezz_no_conn_nets 39 = No_Conn_J6_J1_TX21_P J1_TX21_P | J6 from line 27 of fpga_mezz_no_conn_nets 40 = No_Conn_U8_MGT_CLK4_N MGT_CLK4_N | U8 from line 102 of fpga_mezz_no_conn_nets 41 = No_Conn_J1_J1_TX0_P J1_TX0_P | J1 from line 29 of fpga_mezz_no_conn_nets 42 = No_Conn_L3_J1_RX0_P J1_RX0_P | L3 from line 104 of fpga_mezz_no_conn_nets 43 = No_Conn_H1_J1_TX0_N J1_TX0_N | H1 from line 30 of fpga_mezz_no_conn_nets 44 = No_Conn_L2_J1_RX0_N J1_RX0_N | L2 from line 105 of fpga_mezz_no_conn_nets 45 = No_Conn_L4_J1_B33_VRP J1_B33_VRP | L4 from line 32 of fpga_mezz_no_conn_nets 46 = No_Conn_L5_J1_B33_VRN J1_B33_VRN | L5 from line 107 of fpga_mezz_no_conn_nets 47 = No_Conn_H2_J1_TX1_P J1_TX1_P | H2 from line 34 of fpga_mezz_no_conn_nets 48 = No_Conn_L1_J1_RX1_P J1_RX1_P | L1 from line 109 of fpga_mezz_no_conn_nets 49 = No_Conn_G1_J1_TX1_N J1_TX1_N | G1 from line 35 of fpga_mezz_no_conn_nets 50 = No_Conn_K1_J1_RX1_N J1_RX1_N | K1 from line 110 of fpga_mezz_no_conn_nets 51 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 52 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 53 = No_Conn_G2_J1_TX2_P J1_TX2_P | G2 from line 38 of fpga_mezz_no_conn_nets 54 = No_Conn_K3_J1_RX2_P J1_RX2_P | K3 from line 113 of fpga_mezz_no_conn_nets 55 = No_Conn_F2_J1_TX2_N J1_TX2_N | F2 from line 39 of fpga_mezz_no_conn_nets 56 = No_Conn_K2_J1_RX2_N J1_RX2_N | K2 from line 114 of fpga_mezz_no_conn_nets 57 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 58 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 59 = No_Conn_E3_J1_TX3_P J1_TX3_P | E3 from line 41 of fpga_mezz_no_conn_nets 60 = No_Conn_H6_J1_RX3_P J1_RX3_P | H6 from line 116 of fpga_mezz_no_conn_nets 61 = No_Conn_E2_J1_TX3_N J1_TX3_N | E2 from line 42 of fpga_mezz_no_conn_nets 62 = No_Conn_G6_J1_RX3_N J1_RX3_N | G6 from line 117 of fpga_mezz_no_conn_nets 63 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 64 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 65 = No_Conn_E1_J1_TX4_P J1_TX4_P | E1 from line 44 of fpga_mezz_no_conn_nets 66 = No_Conn_K5_J1_RX4_P J1_RX4_P | K5 from line 119 of fpga_mezz_no_conn_nets 67 = No_Conn_D1_J1_TX4_N J1_TX4_N | D1 from line 45 of fpga_mezz_no_conn_nets 68 = No_Conn_J5_J1_RX4_N J1_RX4_N | J5 from line 120 of fpga_mezz_no_conn_nets 69 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 70 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 71 = No_Conn_C2_J1_TX5_P J1_TX5_P | C2 from line 47 of fpga_mezz_no_conn_nets 72 = No_Conn_J4_J1_RX5_P J1_RX5_P | J4 from line 122 of fpga_mezz_no_conn_nets 73 = No_Conn_C1_J1_TX5_N J1_TX5_N | C1 from line 48 of fpga_mezz_no_conn_nets 74 = No_Conn_J3_J1_RX5_N J1_RX5_N | J3 from line 123 of fpga_mezz_no_conn_nets 75 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 76 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 77 = No_Conn_B2_J1_TX6_P J1_TX6_P | B2 from line 50 of fpga_mezz_no_conn_nets 78 = No_Conn_D4_J1_RX6_P J1_RX6_P | D4 from line 125 of fpga_mezz_no_conn_nets 79 = No_Conn_B1_J1_TX6_N J1_TX6_N | B1 from line 51 of fpga_mezz_no_conn_nets 80 = No_Conn_D3_J1_RX6_N J1_RX6_N | D3 from line 126 of fpga_mezz_no_conn_nets 81 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 82 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 83 = No_Conn_E6_J1_TX7_P J1_TX7_P | E6 from line 53 of fpga_mezz_no_conn_nets 84 = No_Conn_B5_J1_RX7_P J1_RX7_P | B5 from line 128 of fpga_mezz_no_conn_nets 85 = No_Conn_D5_J1_TX7_N J1_TX7_N | D5 from line 54 of fpga_mezz_no_conn_nets 86 = No_Conn_B4_J1_RX7_N J1_RX7_N | B4 from line 129 of fpga_mezz_no_conn_nets 87 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 88 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 89 = No_Conn_A3_J1_TX8_P J1_TX8_P | A3 from line 56 of fpga_mezz_no_conn_nets 90 = No_Conn_A5_J1_RX8_P J1_RX8_P | A5 from line 131 of fpga_mezz_no_conn_nets 91 = No_Conn_A2_J1_TX8_N J1_TX8_N | A2 from line 57 of fpga_mezz_no_conn_nets 92 = No_Conn_A4_J1_RX8_N J1_RX8_N | A4 from line 132 of fpga_mezz_no_conn_nets 93 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 94 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 95 = No_Conn_H4_J1_TX9_P J1_TX9_P | H4 from line 59 of fpga_mezz_no_conn_nets 96 = No_Conn_G5_J1_RX9_P J1_RX9_P | G5 from line 134 of fpga_mezz_no_conn_nets 97 = No_Conn_H3_J1_TX9_N J1_TX9_N | H3 from line 60 of fpga_mezz_no_conn_nets 98 = No_Conn_G4_J1_RX9_N J1_RX9_N | G4 from line 135 of fpga_mezz_no_conn_nets 99 = Mezz_1V8 VCCIO_33 | from line 84 of fpga_vcco_nets 100 = Mezz_1V8 VCCIO_33 | from line 84 of fpga_vcco_nets 101 = No_Conn_E7_J1_TX10_P J1_TX10_P | E7 from line 63 of fpga_mezz_no_conn_nets 102 = No_Conn_L8_J1_RX10_P J1_RX10_P | L8 from line 137 of fpga_mezz_no_conn_nets 103 = No_Conn_D6_J1_TX10_N J1_TX10_N | D6 from line 64 of fpga_mezz_no_conn_nets 104 = No_Conn_K8_J1_RX10_N J1_RX10_N | K8 from line 138 of fpga_mezz_no_conn_nets 105 = No_Conn_M10_J1_B34_VRP J1_B34_VRP | M10 from line 66 of fpga_mezz_no_conn_nets 106 = No_Conn_M12_J1_B34_VRN J1_B34_VRN | M12 from line 140 of fpga_mezz_no_conn_nets 107 = No_Conn_F8_J1_TX11_P J1_TX11_P | F8 from line 68 of fpga_mezz_no_conn_nets 108 = No_Conn_L10_J1_RX11_P J1_RX11_P | L10 from line 142 of fpga_mezz_no_conn_nets 109 = No_Conn_F7_J1_TX11_N J1_TX11_N | F7 from line 69 of fpga_mezz_no_conn_nets 110 = No_Conn_L9_J1_RX11_N J1_RX11_N | L9 from line 143 of fpga_mezz_no_conn_nets 111 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 112 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 113 = No_Conn_C7_J1_TX12_P J1_TX12_P | C7 from line 71 of fpga_mezz_no_conn_nets 114 = No_Conn_L12_J1_RX12_P J1_RX12_P | L12 from line 145 of fpga_mezz_no_conn_nets 115 = No_Conn_B7_J1_TX12_N J1_TX12_N | B7 from line 72 of fpga_mezz_no_conn_nets 116 = No_Conn_K12_J1_RX12_N J1_RX12_N | K12 from line 146 of fpga_mezz_no_conn_nets 117 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 118 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 119 = No_Conn_J8_J1_TX13_P J1_TX13_P | J8 from line 74 of fpga_mezz_no_conn_nets 120 = No_Conn_H7_J1_RX13_P J1_RX13_P | H7 from line 148 of fpga_mezz_no_conn_nets 121 = No_Conn_H8_J1_TX13_N J1_TX13_N | H8 from line 75 of fpga_mezz_no_conn_nets 122 = No_Conn_G7_J1_RX13_N J1_RX13_N | G7 from line 149 of fpga_mezz_no_conn_nets 123 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 124 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 125 = No_Conn_B9_J1_TX14_P J1_TX14_P | B9 from line 77 of fpga_mezz_no_conn_nets 126 = No_Conn_J10_J1_RX14_P J1_RX14_P | J10 from line 151 of fpga_mezz_no_conn_nets 127 = No_Conn_A9_J1_TX14_N J1_TX14_N | A9 from line 78 of fpga_mezz_no_conn_nets 128 = No_Conn_J9_J1_RX14_N J1_RX14_N | J9 from line 152 of fpga_mezz_no_conn_nets 129 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 130 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 131 = No_Conn_B10_J1_TX15_P J1_TX15_P | B10 from line 80 of fpga_mezz_no_conn_nets 132 = No_Conn_C6_J1_RX15_P J1_RX15_P | C6 from line 154 of fpga_mezz_no_conn_nets 133 = No_Conn_A10_J1_TX15_N J1_TX15_N | A10 from line 81 of fpga_mezz_no_conn_nets 134 = No_Conn_B6_J1_RX15_N J1_RX15_N | B6 from line 155 of fpga_mezz_no_conn_nets 135 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 136 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 137 = No_Conn_E10_J1_TX16_P J1_TX16_P | E10 from line 83 of fpga_mezz_no_conn_nets 138 = No_Conn_J11_J1_RX16_P J1_RX16_P | J11 from line 157 of fpga_mezz_no_conn_nets 139 = No_Conn_D10_J1_TX16_N J1_TX16_N | D10 from line 84 of fpga_mezz_no_conn_nets 140 = No_Conn_H11_J1_RX16_N J1_RX16_N | H11 from line 158 of fpga_mezz_no_conn_nets 141 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 142 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 143 = No_Conn_K11_J1_TX17_P J1_TX17_P | K11 from line 86 of fpga_mezz_no_conn_nets 144 = No_Conn_H12_J1_RX17_P J1_RX17_P | H12 from line 160 of fpga_mezz_no_conn_nets 145 = No_Conn_K10_J1_TX17_N J1_TX17_N | K10 from line 87 of fpga_mezz_no_conn_nets 146 = No_Conn_G11_J1_RX17_N J1_RX17_N | G11 from line 161 of fpga_mezz_no_conn_nets 147 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 148 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 149 = No_Conn_F9_J1_TX18_P J1_TX18_P | F9 from line 89 of fpga_mezz_no_conn_nets 150 = No_Conn_E11_J1_RX18_P J1_RX18_P | E11 from line 163 of fpga_mezz_no_conn_nets 151 = No_Conn_E8_J1_TX18_N J1_TX18_N | E8 from line 90 of fpga_mezz_no_conn_nets 152 = No_Conn_D11_J1_RX18_N J1_RX18_N | D11 from line 164 of fpga_mezz_no_conn_nets 153 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 154 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 155 = No_Conn_G10_J1_TX19_P J1_TX19_P | G10 from line 92 of fpga_mezz_no_conn_nets 156 = No_Conn_D9_J1_RX19_P J1_RX19_P | D9 from line 166 of fpga_mezz_no_conn_nets 157 = No_Conn_F10_J1_TX19_N J1_TX19_N | F10 from line 93 of fpga_mezz_no_conn_nets 158 = No_Conn_D8_J1_RX19_N J1_RX19_N | D8 from line 167 of fpga_mezz_no_conn_nets 159 = Mezz_1V8 VCCIO_34 | from line 86 of fpga_vcco_nets 160 = Mezz_1V8 VCCIO_34 | from line 86 of fpga_vcco_nets 161 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 162 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 163 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 164 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 165 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 166 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 167 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 168 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 169 = MEZZ_1V8 1.8V | from line 28 of fpga_j1_power_and_ground_nets 170 = MEZZ_1V8 1.8V | from line 29 of fpga_j1_power_and_ground_nets 171 = MEZZ_1V8 1.8V | from line 28 of fpga_j1_power_and_ground_nets 172 = MEZZ_1V8 1.8V | from line 29 of fpga_j1_power_and_ground_nets ------------------------------------------------------ Pins sorted by Net Name 7 = Combined_Data_from_HUB1_to_MGT_RX_9_CMP MGT_RX9_N | AB5 from line 29 of fpga_j3_j23_combined_data_from_hubs_nets 5 = Combined_Data_from_HUB1_to_MGT_RX_9_DIR MGT_RX9_P | AB6 from line 28 of fpga_j3_j23_combined_data_from_hubs_nets 57 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 51 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 63 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 69 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 75 = GROUND GND | from line 36 of fpga_j1_power_and_ground_nets 93 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 117 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 111 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 81 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 87 = GROUND GND | from line 37 of fpga_j1_power_and_ground_nets 135 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 123 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 129 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 147 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 141 = GROUND GND | from line 38 of fpga_j1_power_and_ground_nets 165 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 167 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 161 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 163 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 153 = GROUND GND | from line 39 of fpga_j1_power_and_ground_nets 58 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 52 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 64 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 76 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 70 = GROUND GND | from line 41 of fpga_j1_power_and_ground_nets 94 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 112 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 82 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 88 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 118 = GROUND GND | from line 42 of fpga_j1_power_and_ground_nets 130 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 136 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 124 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 142 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 148 = GROUND GND | from line 43 of fpga_j1_power_and_ground_nets 164 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 162 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 168 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 166 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 154 = GROUND GND | from line 44 of fpga_j1_power_and_ground_nets 171 = MEZZ_1V8 1.8V | from line 28 of fpga_j1_power_and_ground_nets 169 = MEZZ_1V8 1.8V | from line 28 of fpga_j1_power_and_ground_nets 172 = MEZZ_1V8 1.8V | from line 29 of fpga_j1_power_and_ground_nets 170 = MEZZ_1V8 1.8V | from line 29 of fpga_j1_power_and_ground_nets 12 = MGT_TX_10_to_Cap_CMP MGT_TX10_N | W3 from line 116 of fex_readout_to_hub_nets 10 = MGT_TX_10_to_Cap_DIR MGT_TX10_P | W4 from line 115 of fex_readout_to_hub_nets 16 = MGT_TX_11_to_Cap_CMP MGT_TX11_N | V1 from line 124 of fex_readout_to_hub_nets 14 = MGT_TX_11_to_Cap_DIR MGT_TX11_P | V2 from line 123 of fex_readout_to_hub_nets 4 = MGT_TX_8_to_Cap_CMP MGT_TX8_N | AB1 from line 101 of fex_readout_to_hub_nets 2 = MGT_TX_8_to_Cap_DIR MGT_TX8_P | AB2 from line 100 of fex_readout_to_hub_nets 8 = MGT_TX_9_to_Cap_CMP MGT_TX9_N | Y1 from line 108 of fex_readout_to_hub_nets 6 = MGT_TX_9_to_Cap_DIR MGT_TX9_P | Y2 from line 107 of fex_readout_to_hub_nets 100 = Mezz_1V8 VCCIO_33 | from line 84 of fpga_vcco_nets 99 = Mezz_1V8 VCCIO_33 | from line 84 of fpga_vcco_nets 160 = Mezz_1V8 VCCIO_34 | from line 86 of fpga_vcco_nets 159 = Mezz_1V8 VCCIO_34 | from line 86 of fpga_vcco_nets 11 = Mini_POD_Cap_D11_to_MGT_CMP MGT_RX10_N | Y5 from line 78 of mini_POD_nets 9 = Mini_POD_Cap_D11_to_MGT_DIR MGT_RX10_P | Y6 from line 77 of mini_POD_nets 29 = Mini_POD_Cap_D1_to_MGT_CMP MGT_RX15_P | P6 from line 38 of mini_POD_nets 31 = Mini_POD_Cap_D1_to_MGT_DIR MGT_RX15_N | P5 from line 37 of mini_POD_nets 27 = Mini_POD_Cap_D3_to_MGT_CMP MGT_RX14_N | T5 from line 46 of mini_POD_nets 25 = Mini_POD_Cap_D3_to_MGT_DIR MGT_RX14_P | T6 from line 45 of mini_POD_nets 23 = Mini_POD_Cap_D5_to_MGT_CMP MGT_RX13_N | U3 from line 54 of mini_POD_nets 21 = Mini_POD_Cap_D5_to_MGT_DIR MGT_RX13_P | U4 from line 53 of mini_POD_nets 17 = Mini_POD_Cap_D7_to_MGT_CMP MGT_RX12_P | V6 from line 62 of mini_POD_nets 19 = Mini_POD_Cap_D7_to_MGT_DIR MGT_RX12_N | V5 from line 61 of mini_POD_nets 13 = Mini_POD_Cap_D9_to_MGT_CMP MGT_RX11_P | AA4 from line 70 of mini_POD_nets 15 = Mini_POD_Cap_D9_to_MGT_DIR MGT_RX11_N | AA3 from line 69 of mini_POD_nets 22 = Mini_POD_Trans_D0_CMP MGT_TX13_P | R4 from line 295 of mini_POD_nets 24 = Mini_POD_Trans_D0_DIR MGT_TX13_N | R3 from line 294 of mini_POD_nets 28 = Mini_POD_Trans_D1_CMP MGT_TX14_N | P1 from line 299 of mini_POD_nets 26 = Mini_POD_Trans_D1_DIR MGT_TX14_P | P2 from line 298 of mini_POD_nets 20 = Mini_POD_Trans_D2_CMP MGT_TX12_N | T1 from line 291 of mini_POD_nets 18 = Mini_POD_Trans_D2_DIR MGT_TX12_P | T2 from line 290 of mini_POD_nets 32 = Mini_POD_Trans_D3_CMP MGT_TX15_N | N3 from line 303 of mini_POD_nets 30 = Mini_POD_Trans_D3_DIR MGT_TX15_P | N4 from line 302 of mini_POD_nets 133 = No_Conn_A10_J1_TX15_N J1_TX15_N | A10 from line 81 of fpga_mezz_no_conn_nets 91 = No_Conn_A2_J1_TX8_N J1_TX8_N | A2 from line 57 of fpga_mezz_no_conn_nets 89 = No_Conn_A3_J1_TX8_P J1_TX8_P | A3 from line 56 of fpga_mezz_no_conn_nets 92 = No_Conn_A4_J1_RX8_N J1_RX8_N | A4 from line 132 of fpga_mezz_no_conn_nets 90 = No_Conn_A5_J1_RX8_P J1_RX8_P | A5 from line 131 of fpga_mezz_no_conn_nets 127 = No_Conn_A9_J1_TX14_N J1_TX14_N | A9 from line 78 of fpga_mezz_no_conn_nets 3 = No_Conn_AC3_MGT_RX8_N MGT_RX8_N | AC3 from line 21 of fpga_mezz_no_conn_nets 1 = No_Conn_AC4_MGT_RX8_P MGT_RX8_P | AC4 from line 20 of fpga_mezz_no_conn_nets 131 = No_Conn_B10_J1_TX15_P J1_TX15_P | B10 from line 80 of fpga_mezz_no_conn_nets 79 = No_Conn_B1_J1_TX6_N J1_TX6_N | B1 from line 51 of fpga_mezz_no_conn_nets 77 = No_Conn_B2_J1_TX6_P J1_TX6_P | B2 from line 50 of fpga_mezz_no_conn_nets 86 = No_Conn_B4_J1_RX7_N J1_RX7_N | B4 from line 129 of fpga_mezz_no_conn_nets 84 = No_Conn_B5_J1_RX7_P J1_RX7_P | B5 from line 128 of fpga_mezz_no_conn_nets 134 = No_Conn_B6_J1_RX15_N J1_RX15_N | B6 from line 155 of fpga_mezz_no_conn_nets 115 = No_Conn_B7_J1_TX12_N J1_TX12_N | B7 from line 72 of fpga_mezz_no_conn_nets 125 = No_Conn_B9_J1_TX14_P J1_TX14_P | B9 from line 77 of fpga_mezz_no_conn_nets 73 = No_Conn_C1_J1_TX5_N J1_TX5_N | C1 from line 48 of fpga_mezz_no_conn_nets 71 = No_Conn_C2_J1_TX5_P J1_TX5_P | C2 from line 47 of fpga_mezz_no_conn_nets 132 = No_Conn_C6_J1_RX15_P J1_RX15_P | C6 from line 154 of fpga_mezz_no_conn_nets 113 = No_Conn_C7_J1_TX12_P J1_TX12_P | C7 from line 71 of fpga_mezz_no_conn_nets 139 = No_Conn_D10_J1_TX16_N J1_TX16_N | D10 from line 84 of fpga_mezz_no_conn_nets 152 = No_Conn_D11_J1_RX18_N J1_RX18_N | D11 from line 164 of fpga_mezz_no_conn_nets 67 = No_Conn_D1_J1_TX4_N J1_TX4_N | D1 from line 45 of fpga_mezz_no_conn_nets 80 = No_Conn_D3_J1_RX6_N J1_RX6_N | D3 from line 126 of fpga_mezz_no_conn_nets 78 = No_Conn_D4_J1_RX6_P J1_RX6_P | D4 from line 125 of fpga_mezz_no_conn_nets 85 = No_Conn_D5_J1_TX7_N J1_TX7_N | D5 from line 54 of fpga_mezz_no_conn_nets 103 = No_Conn_D6_J1_TX10_N J1_TX10_N | D6 from line 64 of fpga_mezz_no_conn_nets 158 = No_Conn_D8_J1_RX19_N J1_RX19_N | D8 from line 167 of fpga_mezz_no_conn_nets 156 = No_Conn_D9_J1_RX19_P J1_RX19_P | D9 from line 166 of fpga_mezz_no_conn_nets 137 = No_Conn_E10_J1_TX16_P J1_TX16_P | E10 from line 83 of fpga_mezz_no_conn_nets 150 = No_Conn_E11_J1_RX18_P J1_RX18_P | E11 from line 163 of fpga_mezz_no_conn_nets 65 = No_Conn_E1_J1_TX4_P J1_TX4_P | E1 from line 44 of fpga_mezz_no_conn_nets 61 = No_Conn_E2_J1_TX3_N J1_TX3_N | E2 from line 42 of fpga_mezz_no_conn_nets 59 = No_Conn_E3_J1_TX3_P J1_TX3_P | E3 from line 41 of fpga_mezz_no_conn_nets 34 = No_Conn_E5_J1_RX20_N J1_RX20_N | E5 from line 98 of fpga_mezz_no_conn_nets 83 = No_Conn_E6_J1_TX7_P J1_TX7_P | E6 from line 53 of fpga_mezz_no_conn_nets 101 = No_Conn_E7_J1_TX10_P J1_TX10_P | E7 from line 63 of fpga_mezz_no_conn_nets 151 = No_Conn_E8_J1_TX18_N J1_TX18_N | E8 from line 90 of fpga_mezz_no_conn_nets 157 = No_Conn_F10_J1_TX19_N J1_TX19_N | F10 from line 93 of fpga_mezz_no_conn_nets 55 = No_Conn_F2_J1_TX2_N J1_TX2_N | F2 from line 39 of fpga_mezz_no_conn_nets 33 = No_Conn_F3_J1_TX20_N J1_TX20_N | F3 from line 23 of fpga_mezz_no_conn_nets 35 = No_Conn_F4_J1_TX20_P J1_TX20_P | F4 from line 24 of fpga_mezz_no_conn_nets 36 = No_Conn_F5_J1_RX20_P J1_RX20_P | F5 from line 99 of fpga_mezz_no_conn_nets 109 = No_Conn_F7_J1_TX11_N J1_TX11_N | F7 from line 69 of fpga_mezz_no_conn_nets 107 = No_Conn_F8_J1_TX11_P J1_TX11_P | F8 from line 68 of fpga_mezz_no_conn_nets 149 = No_Conn_F9_J1_TX18_P J1_TX18_P | F9 from line 89 of fpga_mezz_no_conn_nets 155 = No_Conn_G10_J1_TX19_P J1_TX19_P | G10 from line 92 of fpga_mezz_no_conn_nets 146 = No_Conn_G11_J1_RX17_N J1_RX17_N | G11 from line 161 of fpga_mezz_no_conn_nets 49 = No_Conn_G1_J1_TX1_N J1_TX1_N | G1 from line 35 of fpga_mezz_no_conn_nets 53 = No_Conn_G2_J1_TX2_P J1_TX2_P | G2 from line 38 of fpga_mezz_no_conn_nets 98 = No_Conn_G4_J1_RX9_N J1_RX9_N | G4 from line 135 of fpga_mezz_no_conn_nets 96 = No_Conn_G5_J1_RX9_P J1_RX9_P | G5 from line 134 of fpga_mezz_no_conn_nets 62 = No_Conn_G6_J1_RX3_N J1_RX3_N | G6 from line 117 of fpga_mezz_no_conn_nets 122 = No_Conn_G7_J1_RX13_N J1_RX13_N | G7 from line 149 of fpga_mezz_no_conn_nets 140 = No_Conn_H11_J1_RX16_N J1_RX16_N | H11 from line 158 of fpga_mezz_no_conn_nets 144 = No_Conn_H12_J1_RX17_P J1_RX17_P | H12 from line 160 of fpga_mezz_no_conn_nets 43 = No_Conn_H1_J1_TX0_N J1_TX0_N | H1 from line 30 of fpga_mezz_no_conn_nets 47 = No_Conn_H2_J1_TX1_P J1_TX1_P | H2 from line 34 of fpga_mezz_no_conn_nets 97 = No_Conn_H3_J1_TX9_N J1_TX9_N | H3 from line 60 of fpga_mezz_no_conn_nets 95 = No_Conn_H4_J1_TX9_P J1_TX9_P | H4 from line 59 of fpga_mezz_no_conn_nets 60 = No_Conn_H6_J1_RX3_P J1_RX3_P | H6 from line 116 of fpga_mezz_no_conn_nets 120 = No_Conn_H7_J1_RX13_P J1_RX13_P | H7 from line 148 of fpga_mezz_no_conn_nets 121 = No_Conn_H8_J1_TX13_N J1_TX13_N | H8 from line 75 of fpga_mezz_no_conn_nets 126 = No_Conn_J10_J1_RX14_P J1_RX14_P | J10 from line 151 of fpga_mezz_no_conn_nets 138 = No_Conn_J11_J1_RX16_P J1_RX16_P | J11 from line 157 of fpga_mezz_no_conn_nets 41 = No_Conn_J1_J1_TX0_P J1_TX0_P | J1 from line 29 of fpga_mezz_no_conn_nets 74 = No_Conn_J3_J1_RX5_N J1_RX5_N | J3 from line 123 of fpga_mezz_no_conn_nets 72 = No_Conn_J4_J1_RX5_P J1_RX5_P | J4 from line 122 of fpga_mezz_no_conn_nets 68 = No_Conn_J5_J1_RX4_N J1_RX4_N | J5 from line 120 of fpga_mezz_no_conn_nets 39 = No_Conn_J6_J1_TX21_P J1_TX21_P | J6 from line 27 of fpga_mezz_no_conn_nets 119 = No_Conn_J8_J1_TX13_P J1_TX13_P | J8 from line 74 of fpga_mezz_no_conn_nets 128 = No_Conn_J9_J1_RX14_N J1_RX14_N | J9 from line 152 of fpga_mezz_no_conn_nets 145 = No_Conn_K10_J1_TX17_N J1_TX17_N | K10 from line 87 of fpga_mezz_no_conn_nets 143 = No_Conn_K11_J1_TX17_P J1_TX17_P | K11 from line 86 of fpga_mezz_no_conn_nets 116 = No_Conn_K12_J1_RX12_N J1_RX12_N | K12 from line 146 of fpga_mezz_no_conn_nets 50 = No_Conn_K1_J1_RX1_N J1_RX1_N | K1 from line 110 of fpga_mezz_no_conn_nets 56 = No_Conn_K2_J1_RX2_N J1_RX2_N | K2 from line 114 of fpga_mezz_no_conn_nets 54 = No_Conn_K3_J1_RX2_P J1_RX2_P | K3 from line 113 of fpga_mezz_no_conn_nets 66 = No_Conn_K5_J1_RX4_P J1_RX4_P | K5 from line 119 of fpga_mezz_no_conn_nets 37 = No_Conn_K6_J1_TX21_N J1_TX21_N | K6 from line 26 of fpga_mezz_no_conn_nets 104 = No_Conn_K8_J1_RX10_N J1_RX10_N | K8 from line 138 of fpga_mezz_no_conn_nets 108 = No_Conn_L10_J1_RX11_P J1_RX11_P | L10 from line 142 of fpga_mezz_no_conn_nets 114 = No_Conn_L12_J1_RX12_P J1_RX12_P | L12 from line 145 of fpga_mezz_no_conn_nets 48 = No_Conn_L1_J1_RX1_P J1_RX1_P | L1 from line 109 of fpga_mezz_no_conn_nets 44 = No_Conn_L2_J1_RX0_N J1_RX0_N | L2 from line 105 of fpga_mezz_no_conn_nets 42 = No_Conn_L3_J1_RX0_P J1_RX0_P | L3 from line 104 of fpga_mezz_no_conn_nets 45 = No_Conn_L4_J1_B33_VRP J1_B33_VRP | L4 from line 32 of fpga_mezz_no_conn_nets 46 = No_Conn_L5_J1_B33_VRN J1_B33_VRN | L5 from line 107 of fpga_mezz_no_conn_nets 102 = No_Conn_L8_J1_RX10_P J1_RX10_P | L8 from line 137 of fpga_mezz_no_conn_nets 110 = No_Conn_L9_J1_RX11_N J1_RX11_N | L9 from line 143 of fpga_mezz_no_conn_nets 105 = No_Conn_M10_J1_B34_VRP J1_B34_VRP | M10 from line 66 of fpga_mezz_no_conn_nets 106 = No_Conn_M12_J1_B34_VRN J1_B34_VRN | M12 from line 140 of fpga_mezz_no_conn_nets 38 = No_Conn_U7_MGT_CLK4_P MGT_CLK4_P | U7 from line 101 of fpga_mezz_no_conn_nets 40 = No_Conn_U8_MGT_CLK4_N MGT_CLK4_N | U8 from line 102 of fpga_mezz_no_conn_nets