Found 172 pins for J3 which is of type Samtec_ASP-122953-01-J3 ------------------------------------------------------ Pins sorted by Pin Name 1 = MGT_TX_7_to_Cap_CMP MGT_TX7_N | AD1 from line 82 of fex_readout_to_hub_nets 2 = No_Conn_AD5_J3_MGT_RX7_N MGT_RX7_N | AD5 from line 397 of fpga_mezz_no_conn_nets 3 = MGT_TX_7_to_Cap_DIR MGT_TX7_P | AD2 from line 81 of fex_readout_to_hub_nets 4 = No_Conn_AD6_J3_MGT_RX7_P MGT_RX7_P | AD6 from line 398 of fpga_mezz_no_conn_nets 5 = MGT_TX_6_to_Cap_CMP MGT_TX6_N | AE3 from line 74 of fex_readout_to_hub_nets 6 = Combined_Data_from_HUB2_to_MGT_RX_6_CMP MGT_RX6_N | AF5 from line 48 of fpga_j3_j23_combined_data_from_hubs_nets 7 = MGT_TX_6_to_Cap_DIR MGT_TX6_P | AE4 from line 73 of fex_readout_to_hub_nets 8 = Combined_Data_from_HUB2_to_MGT_RX_6_DIR MGT_RX6_P | AF6 from line 47 of fpga_j3_j23_combined_data_from_hubs_nets 9 = MGT_TX_5_to_Cap_CMP MGT_TX5_N | AF1 from line 66 of fex_readout_to_hub_nets 10 = Mini_POD_Cap_D10_to_MGT_CMP MGT_RX5_N | AG3 from line 96 of mini_POD_nets 11 = MGT_TX_5_to_Cap_DIR MGT_TX5_P | AF2 from line 65 of fex_readout_to_hub_nets 12 = Mini_POD_Cap_D10_to_MGT_DIR MGT_RX5_P | AG4 from line 95 of mini_POD_nets 13 = MGT_TX_4_to_Cap_CMP MGT_TX4_N | AH1 from line 58 of fex_readout_to_hub_nets 14 = Mini_POD_Cap_D8_to_MGT_CMP MGT_RX4_N | AH5 from line 104 of mini_POD_nets 15 = MGT_TX_4_to_Cap_DIR MGT_TX4_P | AH2 from line 57 of fex_readout_to_hub_nets 16 = Mini_POD_Cap_D8_to_MGT_DIR MGT_RX4_P | AH6 from line 103 of mini_POD_nets 17 = MGT_TX_3_to_Cap_CMP MGT_TX3_N | AK1 from line 49 of fex_readout_to_hub_nets 18 = Mini_POD_Cap_D6_to_MGT_CMP MGT_RX3_N | AE7 from line 112 of mini_POD_nets 19 = MGT_TX_3_to_Cap_DIR MGT_TX3_P | AK2 from line 48 of fex_readout_to_hub_nets 20 = Mini_POD_Cap_D6_to_MGT_DIR MGT_RX3_P | AE8 from line 111 of mini_POD_nets 21 = MGT_TX_2_to_Cap_CMP MGT_TX2_N | AJ3 from line 41 of fex_readout_to_hub_nets 22 = Mini_POD_Cap_D4_to_MGT_CMP MGT_RX2_N | AG7 from line 120 of mini_POD_nets 23 = MGT_TX_2_to_Cap_DIR MGT_TX2_P | AJ4 from line 40 of fex_readout_to_hub_nets 24 = Mini_POD_Cap_D4_to_MGT_DIR MGT_RX2_P | AG8 from line 119 of mini_POD_nets 25 = MGT_TX_1_to_Cap_CMP MGT_TX1_N | AK5 from line 33 of fex_readout_to_hub_nets 26 = Mini_POD_Cap_D2_to_MGT_DIR MGT_RX1_N | AJ7 from line 127 of mini_POD_nets 27 = MGT_TX_1_to_Cap_DIR MGT_TX1_P | AK6 from line 32 of fex_readout_to_hub_nets 28 = Mini_POD_Cap_D2_to_MGT_CMP MGT_RX1_P | AJ8 from line 128 of mini_POD_nets 29 = MGT_TX_0_to_Cap_CMP MGT_TX0_N | AK9 from line 25 of fex_readout_to_hub_nets 30 = Mini_POD_Cap_D0_to_MGT_CMP MGT_RX0_N | AH9 from line 136 of mini_POD_nets 31 = MGT_TX_0_to_Cap_DIR MGT_TX0_P | AK10 from line 24 of fex_readout_to_hub_nets 32 = Mini_POD_Cap_D0_to_MGT_DIR MGT_RX0_P | AH10 from line 135 of mini_POD_nets 33 = No_Conn_AF13_J3_TX20_P J3_TX20_N | AF13 from line 341 of fpga_mezz_no_conn_nets 34 = No_Conn_AG14_J3_MGT_RX6_N J3_RX20_N | AG14 from line 400 of fpga_mezz_no_conn_nets 35 = No_Conn_AE13_J3_TX20_N J3_TX20_P | AE13 from line 342 of fpga_mezz_no_conn_nets 36 = No_Conn_AF14_J3_MGT_RX6_P J3_RX20_P | AF14 from line 401 of fpga_mezz_no_conn_nets 37 = No_Conn_AC7_J3_MGT_CLK1_P MGT_CLK1_P | AC7 from line 344 of fpga_mezz_no_conn_nets 38 = Ref_40_MHz_to_SiLab_Cmp SI5328_CLK1_P | from line 181 of clock_generation_nets 39 = No_Conn_AC8_J3_MGT_CLK1_N MGT_CLK1_N | AC8 from line 345 of fpga_mezz_no_conn_nets 40 = Ref_40_MHz_to_SiLab_Dir SI5328_CLK1_N | from line 180 of clock_generation_nets 41 = Access_Signal_1_from_FPGA J3_TX0_P | AE12 from line 148 of jtag_and_j12_associated_nets 42 = No_Conn_AJ15_J3_RX0_P J3_RX0_P | AJ15 from line 403 of fpga_mezz_no_conn_nets 43 = Access_Signal_2_from_FPGA J3_TX0_N | AF12 from line 149 of jtag_and_j12_associated_nets 44 = No_Conn_AK15_J3_RX0_N J3_RX0_N | AK15 from line 404 of fpga_mezz_no_conn_nets 45 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 46 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 47 = HW_ADRS_3 J3_TX1_P | AD14 from line 79 of hardware_address_nets 48 = MP_Trans_RESET J3_RX1_P | AJ14 from line 368 of mini_POD_nets 49 = No_Conn_AD13_J3_TX1_N J3_TX1_N | AD13 from line 347 of fpga_mezz_no_conn_nets 50 = No_Conn_AJ13_J3_RX1_N J3_RX1_N | AJ13 from line 406 of fpga_mezz_no_conn_nets 51 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 52 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 53 = HW_ADRS_2 J3_TX2_P | AG12 from line 78 of hardware_address_nets 54 = MP_Trans_SCL J3_RX2_P | AK13 from line 367 of mini_POD_nets 55 = No_Conn_AH12_J3_TX2_N J3_TX2_N | AH12 from line 349 of fpga_mezz_no_conn_nets 56 = No_Conn_AK12_J3_RX2_N J3_RX2_N | AK12 from line 408 of fpga_mezz_no_conn_nets 57 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 58 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 59 = HW_ADRS_6 J3_TX3_P | AB12 from line 83 of hardware_address_nets 60 = MP_Trans_SDA J3_RX3_P | AJ16 from line 366 of mini_POD_nets 61 = No_Conn_AC12_J3_TX3_N J3_TX3_N | AC12 from line 351 of fpga_mezz_no_conn_nets 62 = No_Conn_AK16_J3_RX3_N J3_RX3_N | AK16 from line 410 of fpga_mezz_no_conn_nets 63 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 64 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 65 = HW_ADRS_7 J3_TX4_P | AA15 from line 84 of hardware_address_nets 66 = MP_Trans_INTR J3_RX4_P | AF18 from line 365 of mini_POD_nets 67 = No_Conn_AA14_J3_TX4_N J3_TX4_N | AA14 from line 353 of fpga_mezz_no_conn_nets 68 = No_Conn_AF17_J3_RX4_N J3_RX4_N | AF17 from line 412 of fpga_mezz_no_conn_nets 69 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 70 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 71 = HW_ADRS_5 J3_TX5_P | AH14 from line 82 of hardware_address_nets 72 = MP_Rec_RESET J3_RX5_P | AH18 from line 203 of mini_POD_nets 73 = No_Conn_AH13_J3_TX5_N J3_TX5_N | AH13 from line 355 of fpga_mezz_no_conn_nets 74 = MP_Rec_SCL J3_RX5_N | AJ18 from line 202 of mini_POD_nets 75 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 76 = No_Conn_J3_NC_Pin_76 NC | from line 414 of fpga_mezz_no_conn_nets 77 = HW_ADRS_4 J3_TX6_P | AE16 from line 81 of hardware_address_nets 78 = MP_Rec_SDA J3_RX6_P | AD16 from line 201 of mini_POD_nets 79 = No_Conn_AE15_J3_TX6_N J3_TX6_N | AE15 from line 357 of fpga_mezz_no_conn_nets 80 = MP_Rec_INTR J3_RX6_N | AD15 from line 200 of mini_POD_nets 81 = CPLD_M_TCK M_TCK | from line 47 of htm_life_boat_nets 82 = CPLD_M_TMS M_TMS | from line 46 of htm_life_boat_nets 83 = HW_ADRS_0 J3_TX7_P | AB15 from line 76 of hardware_address_nets 84 = No_Conn_AE18_J3_RX7_P J3_RX7_P | AE18 from line 416 of fpga_mezz_no_conn_nets 85 = No_Conn_AB14_J3_TX7_N J3_TX7_N | AB14 from line 359 of fpga_mezz_no_conn_nets 86 = No_Conn_AE17_J3_RX7_N J3_RX7_N | AE17 from line 417 of fpga_mezz_no_conn_nets 87 = CPLD_M_TDI M_TDI | from line 49 of htm_life_boat_nets 88 = CPLD_M_TDO M_TDO | from line 48 of htm_life_boat_nets 89 = HW_ADRS_1 J3_TX8_P | AC17 from line 77 of hardware_address_nets 90 = No_Conn_AB16_J3_RX8_P J3_RX8_P | AB16 from line 419 of fpga_mezz_no_conn_nets 91 = No_Conn_AC16_J3_TX8_N J3_TX8_N | AC16 from line 361 of fpga_mezz_no_conn_nets 92 = No_Conn_AB17_J3_RX8_N J3_RX8_N | AB17 from line 420 of fpga_mezz_no_conn_nets 93 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 94 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 95 = No_Conn_AF15_J3_TX21_P J3_TX21_P | AF15 from line 363 of fpga_mezz_no_conn_nets 96 = No_Conn_AG17_J3_RX21_P J3_RX21_P | AG17 from line 422 of fpga_mezz_no_conn_nets 97 = No_Conn_AG15_J3_TX21_N J3_TX21_N | AG15 from line 364 of fpga_mezz_no_conn_nets 98 = No_Conn_AG16_J3_RX21_N J3_RX21_N | AG16 from line 423 of fpga_mezz_no_conn_nets 99 = Mezz_3V3 VCCIO_10 | from line 61 of fpga_vcco_nets 100 = Mezz_3V3 VCCIO_10 | from line 61 of fpga_vcco_nets 101 = PLL_40_MHz_Locked_Mon J3_TX10_P | AK17 from line 105 of clock_generation_nets 102 = No_Conn_AJ23_J3_RX10_P J3_RX10_P | AJ23 from line 428 of fpga_mezz_no_conn_nets 103 = No_Conn_AK18_J3_TX10_N J3_TX10_N | AK18 from line 369 of fpga_mezz_no_conn_nets 104 = No_Conn_AJ24_J3_RX10_N J3_RX10_N | AJ24 from line 429 of fpga_mezz_no_conn_nets 105 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 106 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 107 = LB_FPGA_Sel_IO_1 J3_TX11_P | AK22 from line 136 of htm_life_boat_nets 108 = No_Conn_AJ25_J3_RX11_P J3_RX11_P | AJ25 from line 431 of fpga_mezz_no_conn_nets 109 = No_Conn_AK23_J3_TX11_N J3_TX11_N | AK23 from line 371 of fpga_mezz_no_conn_nets 110 = No_Conn_AK25_J3_RX11_N J3_RX11_N | AK25 from line 432 of fpga_mezz_no_conn_nets 111 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 112 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 113 = LB_FPGA_Sel_IO_2 J3_TX12_P | AJ20 from line 138 of htm_life_boat_nets 114 = No_Conn_AG24_J3_RX12_P J3_RX12_P | AG24 from line 434 of fpga_mezz_no_conn_nets 115 = No_Conn_AK20_J3_TX12_N J3_TX12_N | AK20 from line 373 of fpga_mezz_no_conn_nets 116 = No_Conn_AG25_J3_RX12_N J3_RX12_N | AG25 from line 435 of fpga_mezz_no_conn_nets 117 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 118 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 119 = LB_FPGA_Sel_IO_3 J3_TX13_P | AJ21 from line 140 of htm_life_boat_nets 120 = No_Conn_AC22_J3_RX13_P J3_RX13_P | AC22 from line 437 of fpga_mezz_no_conn_nets 121 = No_Conn_AK21_J3_TX13_N J3_TX13_N | AK21 from line 375 of fpga_mezz_no_conn_nets 122 = No_Conn_AC23_J3_RX13_N J3_RX13_N | AC23 from line 438 of fpga_mezz_no_conn_nets 123 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 124 = LB_VBAT_IN VBAT_IN | from line 109 of htm_life_boat_nets 125 = LB_FPGA_Sel_IO_4 J3_TX14_P | AH19 from line 142 of htm_life_boat_nets 126 = No_Conn_AD21_J3_RX14_P J3_RX14_P | AD21 from line 440 of fpga_mezz_no_conn_nets 127 = No_Conn_AJ19_J3_TX14_N J3_TX14_N | AJ19 from line 377 of fpga_mezz_no_conn_nets 128 = No_Conn_AE21_J3_RX14_N J3_RX14_N | AE21 from line 441 of fpga_mezz_no_conn_nets 129 = LB_CONFIGX CONFIGX | from line 103 of htm_life_boat_nets 130 = LB_RESIN RESIN | from line 97 of htm_life_boat_nets 131 = No_Conn_AF19_J3_TX15_P J3_TX15_P | AF19 from line 379 of fpga_mezz_no_conn_nets 132 = No_Conn_AA22_J3_RX15_P J3_RX15_P | AA22 from line 443 of fpga_mezz_no_conn_nets 133 = No_Conn_AG19_J3_TX15_N J3_TX15_N | AG19 from line 380 of fpga_mezz_no_conn_nets 134 = No_Conn_AA23_J3_RX15_N J3_RX15_N | AA23 from line 444 of fpga_mezz_no_conn_nets 135 = LB_BOOTMODE BOOTMODE | from line 91 of htm_life_boat_nets 136 = LB_JTAGENB JTAGENB | from line 85 of htm_life_boat_nets 137 = No_Conn_AF23_J3_TX16_P J3_TX16_P | AF23 from line 382 of fpga_mezz_no_conn_nets 138 = No_Conn_Y22_J3_RX16_P J3_RX16_P | Y22 from line 446 of fpga_mezz_no_conn_nets 139 = No_Conn_AF24_J3_TX16_N J3_TX16_N | AF24 from line 383 of fpga_mezz_no_conn_nets 140 = No_Conn_Y23_J3_RX16_N J3_RX16_N | Y23 from line 447 of fpga_mezz_no_conn_nets 141 = TCK_TO_FPGA_MEZZ TCK | Y12 from line 115 of jtag_and_j12_associated_nets 142 = TMS_TO_FPGA_MEZZ TMS | V10 from line 110 of jtag_and_j12_associated_nets 143 = No_Conn_AH23_J3_TX17_P J3_TX17_P | AH23 from line 385 of fpga_mezz_no_conn_nets 144 = No_Conn_AA24_J3_RX17_P J3_RX17_P | AA24 from line 449 of fpga_mezz_no_conn_nets 145 = No_Conn_AH24_J3_TX17_N J3_TX17_N | AH24 from line 386 of fpga_mezz_no_conn_nets 146 = No_Conn_AB24_J3_RX17_N J3_RX17_N | AB24 from line 450 of fpga_mezz_no_conn_nets 147 = TDI_TO_FPGA_MEZZ TDI | P10 from line 120 of jtag_and_j12_associated_nets 148 = TDO_From_FPGA_Mezz TDO | Y10 from line 129 of jtag_and_j12_associated_nets 149 = No_Conn_AC24_J3_TX18_P J3_TX18_P | AC24 from line 388 of fpga_mezz_no_conn_nets 150 = No_Conn_W21_J3_RX18_P J3_RX18_P | W21 from line 452 of fpga_mezz_no_conn_nets 151 = No_Conn_AD24_J3_TX18_N J3_TX18_N | AD24 from line 389 of fpga_mezz_no_conn_nets 152 = No_Conn_Y21_J3_RX18_N J3_RX18_N | Y21 from line 453 of fpga_mezz_no_conn_nets 153 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 154 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 155 = No_Conn_AD23_J3_TX19_P J3_TX19_P | AD23 from line 391 of fpga_mezz_no_conn_nets 156 = FPGA_40_MHz_Logic_Clk_Dir J3_RX19_P | AE22 from line 160 of clock_generation_nets 157 = No_Conn_AE23_J3_TX19_N J3_TX19_N | AE23 from line 392 of fpga_mezz_no_conn_nets 158 = FPGA_40_MHz_Logic_Clk_Cmp J3_RX19_N | AF22 from line 161 of clock_generation_nets 159 = Mezz_3V3 VCCIO_11 | from line 63 of fpga_vcco_nets 160 = Mezz_3V3 VCCIO_11 | from line 63 of fpga_vcco_nets 161 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 162 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 163 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 164 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 165 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 166 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 167 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 168 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 169 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 170 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 171 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 172 = GROUND GND | from line 40 of fpga_j3_power_and_ground_nets ------------------------------------------------------ Pins sorted by Net Name 41 = Access_Signal_1_from_FPGA J3_TX0_P | AE12 from line 148 of jtag_and_j12_associated_nets 43 = Access_Signal_2_from_FPGA J3_TX0_N | AF12 from line 149 of jtag_and_j12_associated_nets 81 = CPLD_M_TCK M_TCK | from line 47 of htm_life_boat_nets 87 = CPLD_M_TDI M_TDI | from line 49 of htm_life_boat_nets 88 = CPLD_M_TDO M_TDO | from line 48 of htm_life_boat_nets 82 = CPLD_M_TMS M_TMS | from line 46 of htm_life_boat_nets 6 = Combined_Data_from_HUB2_to_MGT_RX_6_CMP MGT_RX6_N | AF5 from line 48 of fpga_j3_j23_combined_data_from_hubs_nets 8 = Combined_Data_from_HUB2_to_MGT_RX_6_DIR MGT_RX6_P | AF6 from line 47 of fpga_j3_j23_combined_data_from_hubs_nets 158 = FPGA_40_MHz_Logic_Clk_Cmp J3_RX19_N | AF22 from line 161 of clock_generation_nets 156 = FPGA_40_MHz_Logic_Clk_Dir J3_RX19_P | AE22 from line 160 of clock_generation_nets 57 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 51 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 63 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 69 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 45 = GROUND GND | from line 32 of fpga_j3_power_and_ground_nets 93 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 117 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 111 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 105 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 75 = GROUND GND | from line 33 of fpga_j3_power_and_ground_nets 161 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 123 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 165 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 163 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 153 = GROUND GND | from line 34 of fpga_j3_power_and_ground_nets 171 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 169 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 167 = GROUND GND | from line 35 of fpga_j3_power_and_ground_nets 58 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 52 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 64 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 46 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 70 = GROUND GND | from line 37 of fpga_j3_power_and_ground_nets 112 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 118 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 106 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 94 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 154 = GROUND GND | from line 38 of fpga_j3_power_and_ground_nets 164 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 162 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 170 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 168 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 166 = GROUND GND | from line 39 of fpga_j3_power_and_ground_nets 172 = GROUND GND | from line 40 of fpga_j3_power_and_ground_nets 83 = HW_ADRS_0 J3_TX7_P | AB15 from line 76 of hardware_address_nets 89 = HW_ADRS_1 J3_TX8_P | AC17 from line 77 of hardware_address_nets 53 = HW_ADRS_2 J3_TX2_P | AG12 from line 78 of hardware_address_nets 47 = HW_ADRS_3 J3_TX1_P | AD14 from line 79 of hardware_address_nets 77 = HW_ADRS_4 J3_TX6_P | AE16 from line 81 of hardware_address_nets 71 = HW_ADRS_5 J3_TX5_P | AH14 from line 82 of hardware_address_nets 59 = HW_ADRS_6 J3_TX3_P | AB12 from line 83 of hardware_address_nets 65 = HW_ADRS_7 J3_TX4_P | AA15 from line 84 of hardware_address_nets 135 = LB_BOOTMODE BOOTMODE | from line 91 of htm_life_boat_nets 129 = LB_CONFIGX CONFIGX | from line 103 of htm_life_boat_nets 107 = LB_FPGA_Sel_IO_1 J3_TX11_P | AK22 from line 136 of htm_life_boat_nets 113 = LB_FPGA_Sel_IO_2 J3_TX12_P | AJ20 from line 138 of htm_life_boat_nets 119 = LB_FPGA_Sel_IO_3 J3_TX13_P | AJ21 from line 140 of htm_life_boat_nets 125 = LB_FPGA_Sel_IO_4 J3_TX14_P | AH19 from line 142 of htm_life_boat_nets 136 = LB_JTAGENB JTAGENB | from line 85 of htm_life_boat_nets 130 = LB_RESIN RESIN | from line 97 of htm_life_boat_nets 124 = LB_VBAT_IN VBAT_IN | from line 109 of htm_life_boat_nets 29 = MGT_TX_0_to_Cap_CMP MGT_TX0_N | AK9 from line 25 of fex_readout_to_hub_nets 31 = MGT_TX_0_to_Cap_DIR MGT_TX0_P | AK10 from line 24 of fex_readout_to_hub_nets 25 = MGT_TX_1_to_Cap_CMP MGT_TX1_N | AK5 from line 33 of fex_readout_to_hub_nets 27 = MGT_TX_1_to_Cap_DIR MGT_TX1_P | AK6 from line 32 of fex_readout_to_hub_nets 21 = MGT_TX_2_to_Cap_CMP MGT_TX2_N | AJ3 from line 41 of fex_readout_to_hub_nets 23 = MGT_TX_2_to_Cap_DIR MGT_TX2_P | AJ4 from line 40 of fex_readout_to_hub_nets 17 = MGT_TX_3_to_Cap_CMP MGT_TX3_N | AK1 from line 49 of fex_readout_to_hub_nets 19 = MGT_TX_3_to_Cap_DIR MGT_TX3_P | AK2 from line 48 of fex_readout_to_hub_nets 13 = MGT_TX_4_to_Cap_CMP MGT_TX4_N | AH1 from line 58 of fex_readout_to_hub_nets 15 = MGT_TX_4_to_Cap_DIR MGT_TX4_P | AH2 from line 57 of fex_readout_to_hub_nets 9 = MGT_TX_5_to_Cap_CMP MGT_TX5_N | AF1 from line 66 of fex_readout_to_hub_nets 11 = MGT_TX_5_to_Cap_DIR MGT_TX5_P | AF2 from line 65 of fex_readout_to_hub_nets 5 = MGT_TX_6_to_Cap_CMP MGT_TX6_N | AE3 from line 74 of fex_readout_to_hub_nets 7 = MGT_TX_6_to_Cap_DIR MGT_TX6_P | AE4 from line 73 of fex_readout_to_hub_nets 1 = MGT_TX_7_to_Cap_CMP MGT_TX7_N | AD1 from line 82 of fex_readout_to_hub_nets 3 = MGT_TX_7_to_Cap_DIR MGT_TX7_P | AD2 from line 81 of fex_readout_to_hub_nets 80 = MP_Rec_INTR J3_RX6_N | AD15 from line 200 of mini_POD_nets 72 = MP_Rec_RESET J3_RX5_P | AH18 from line 203 of mini_POD_nets 74 = MP_Rec_SCL J3_RX5_N | AJ18 from line 202 of mini_POD_nets 78 = MP_Rec_SDA J3_RX6_P | AD16 from line 201 of mini_POD_nets 66 = MP_Trans_INTR J3_RX4_P | AF18 from line 365 of mini_POD_nets 48 = MP_Trans_RESET J3_RX1_P | AJ14 from line 368 of mini_POD_nets 54 = MP_Trans_SCL J3_RX2_P | AK13 from line 367 of mini_POD_nets 60 = MP_Trans_SDA J3_RX3_P | AJ16 from line 366 of mini_POD_nets 100 = Mezz_3V3 VCCIO_10 | from line 61 of fpga_vcco_nets 99 = Mezz_3V3 VCCIO_10 | from line 61 of fpga_vcco_nets 160 = Mezz_3V3 VCCIO_11 | from line 63 of fpga_vcco_nets 159 = Mezz_3V3 VCCIO_11 | from line 63 of fpga_vcco_nets 30 = Mini_POD_Cap_D0_to_MGT_CMP MGT_RX0_N | AH9 from line 136 of mini_POD_nets 32 = Mini_POD_Cap_D0_to_MGT_DIR MGT_RX0_P | AH10 from line 135 of mini_POD_nets 10 = Mini_POD_Cap_D10_to_MGT_CMP MGT_RX5_N | AG3 from line 96 of mini_POD_nets 12 = Mini_POD_Cap_D10_to_MGT_DIR MGT_RX5_P | AG4 from line 95 of mini_POD_nets 28 = Mini_POD_Cap_D2_to_MGT_CMP MGT_RX1_P | AJ8 from line 128 of mini_POD_nets 26 = Mini_POD_Cap_D2_to_MGT_DIR MGT_RX1_N | AJ7 from line 127 of mini_POD_nets 22 = Mini_POD_Cap_D4_to_MGT_CMP MGT_RX2_N | AG7 from line 120 of mini_POD_nets 24 = Mini_POD_Cap_D4_to_MGT_DIR MGT_RX2_P | AG8 from line 119 of mini_POD_nets 18 = Mini_POD_Cap_D6_to_MGT_CMP MGT_RX3_N | AE7 from line 112 of mini_POD_nets 20 = Mini_POD_Cap_D6_to_MGT_DIR MGT_RX3_P | AE8 from line 111 of mini_POD_nets 14 = Mini_POD_Cap_D8_to_MGT_CMP MGT_RX4_N | AH5 from line 104 of mini_POD_nets 16 = Mini_POD_Cap_D8_to_MGT_DIR MGT_RX4_P | AH6 from line 103 of mini_POD_nets 67 = No_Conn_AA14_J3_TX4_N J3_TX4_N | AA14 from line 353 of fpga_mezz_no_conn_nets 132 = No_Conn_AA22_J3_RX15_P J3_RX15_P | AA22 from line 443 of fpga_mezz_no_conn_nets 134 = No_Conn_AA23_J3_RX15_N J3_RX15_N | AA23 from line 444 of fpga_mezz_no_conn_nets 144 = No_Conn_AA24_J3_RX17_P J3_RX17_P | AA24 from line 449 of fpga_mezz_no_conn_nets 85 = No_Conn_AB14_J3_TX7_N J3_TX7_N | AB14 from line 359 of fpga_mezz_no_conn_nets 90 = No_Conn_AB16_J3_RX8_P J3_RX8_P | AB16 from line 419 of fpga_mezz_no_conn_nets 92 = No_Conn_AB17_J3_RX8_N J3_RX8_N | AB17 from line 420 of fpga_mezz_no_conn_nets 146 = No_Conn_AB24_J3_RX17_N J3_RX17_N | AB24 from line 450 of fpga_mezz_no_conn_nets 61 = No_Conn_AC12_J3_TX3_N J3_TX3_N | AC12 from line 351 of fpga_mezz_no_conn_nets 91 = No_Conn_AC16_J3_TX8_N J3_TX8_N | AC16 from line 361 of fpga_mezz_no_conn_nets 120 = No_Conn_AC22_J3_RX13_P J3_RX13_P | AC22 from line 437 of fpga_mezz_no_conn_nets 122 = No_Conn_AC23_J3_RX13_N J3_RX13_N | AC23 from line 438 of fpga_mezz_no_conn_nets 149 = No_Conn_AC24_J3_TX18_P J3_TX18_P | AC24 from line 388 of fpga_mezz_no_conn_nets 37 = No_Conn_AC7_J3_MGT_CLK1_P MGT_CLK1_P | AC7 from line 344 of fpga_mezz_no_conn_nets 39 = No_Conn_AC8_J3_MGT_CLK1_N MGT_CLK1_N | AC8 from line 345 of fpga_mezz_no_conn_nets 49 = No_Conn_AD13_J3_TX1_N J3_TX1_N | AD13 from line 347 of fpga_mezz_no_conn_nets 126 = No_Conn_AD21_J3_RX14_P J3_RX14_P | AD21 from line 440 of fpga_mezz_no_conn_nets 155 = No_Conn_AD23_J3_TX19_P J3_TX19_P | AD23 from line 391 of fpga_mezz_no_conn_nets 151 = No_Conn_AD24_J3_TX18_N J3_TX18_N | AD24 from line 389 of fpga_mezz_no_conn_nets 2 = No_Conn_AD5_J3_MGT_RX7_N MGT_RX7_N | AD5 from line 397 of fpga_mezz_no_conn_nets 4 = No_Conn_AD6_J3_MGT_RX7_P MGT_RX7_P | AD6 from line 398 of fpga_mezz_no_conn_nets 35 = No_Conn_AE13_J3_TX20_N J3_TX20_P | AE13 from line 342 of fpga_mezz_no_conn_nets 79 = No_Conn_AE15_J3_TX6_N J3_TX6_N | AE15 from line 357 of fpga_mezz_no_conn_nets 86 = No_Conn_AE17_J3_RX7_N J3_RX7_N | AE17 from line 417 of fpga_mezz_no_conn_nets 84 = No_Conn_AE18_J3_RX7_P J3_RX7_P | AE18 from line 416 of fpga_mezz_no_conn_nets 128 = No_Conn_AE21_J3_RX14_N J3_RX14_N | AE21 from line 441 of fpga_mezz_no_conn_nets 157 = No_Conn_AE23_J3_TX19_N J3_TX19_N | AE23 from line 392 of fpga_mezz_no_conn_nets 33 = No_Conn_AF13_J3_TX20_P J3_TX20_N | AF13 from line 341 of fpga_mezz_no_conn_nets 36 = No_Conn_AF14_J3_MGT_RX6_P J3_RX20_P | AF14 from line 401 of fpga_mezz_no_conn_nets 95 = No_Conn_AF15_J3_TX21_P J3_TX21_P | AF15 from line 363 of fpga_mezz_no_conn_nets 68 = No_Conn_AF17_J3_RX4_N J3_RX4_N | AF17 from line 412 of fpga_mezz_no_conn_nets 131 = No_Conn_AF19_J3_TX15_P J3_TX15_P | AF19 from line 379 of fpga_mezz_no_conn_nets 137 = No_Conn_AF23_J3_TX16_P J3_TX16_P | AF23 from line 382 of fpga_mezz_no_conn_nets 139 = No_Conn_AF24_J3_TX16_N J3_TX16_N | AF24 from line 383 of fpga_mezz_no_conn_nets 34 = No_Conn_AG14_J3_MGT_RX6_N J3_RX20_N | AG14 from line 400 of fpga_mezz_no_conn_nets 97 = No_Conn_AG15_J3_TX21_N J3_TX21_N | AG15 from line 364 of fpga_mezz_no_conn_nets 98 = No_Conn_AG16_J3_RX21_N J3_RX21_N | AG16 from line 423 of fpga_mezz_no_conn_nets 96 = No_Conn_AG17_J3_RX21_P J3_RX21_P | AG17 from line 422 of fpga_mezz_no_conn_nets 133 = No_Conn_AG19_J3_TX15_N J3_TX15_N | AG19 from line 380 of fpga_mezz_no_conn_nets 114 = No_Conn_AG24_J3_RX12_P J3_RX12_P | AG24 from line 434 of fpga_mezz_no_conn_nets 116 = No_Conn_AG25_J3_RX12_N J3_RX12_N | AG25 from line 435 of fpga_mezz_no_conn_nets 55 = No_Conn_AH12_J3_TX2_N J3_TX2_N | AH12 from line 349 of fpga_mezz_no_conn_nets 73 = No_Conn_AH13_J3_TX5_N J3_TX5_N | AH13 from line 355 of fpga_mezz_no_conn_nets 143 = No_Conn_AH23_J3_TX17_P J3_TX17_P | AH23 from line 385 of fpga_mezz_no_conn_nets 145 = No_Conn_AH24_J3_TX17_N J3_TX17_N | AH24 from line 386 of fpga_mezz_no_conn_nets 50 = No_Conn_AJ13_J3_RX1_N J3_RX1_N | AJ13 from line 406 of fpga_mezz_no_conn_nets 42 = No_Conn_AJ15_J3_RX0_P J3_RX0_P | AJ15 from line 403 of fpga_mezz_no_conn_nets 127 = No_Conn_AJ19_J3_TX14_N J3_TX14_N | AJ19 from line 377 of fpga_mezz_no_conn_nets 102 = No_Conn_AJ23_J3_RX10_P J3_RX10_P | AJ23 from line 428 of fpga_mezz_no_conn_nets 104 = No_Conn_AJ24_J3_RX10_N J3_RX10_N | AJ24 from line 429 of fpga_mezz_no_conn_nets 108 = No_Conn_AJ25_J3_RX11_P J3_RX11_P | AJ25 from line 431 of fpga_mezz_no_conn_nets 56 = No_Conn_AK12_J3_RX2_N J3_RX2_N | AK12 from line 408 of fpga_mezz_no_conn_nets 44 = No_Conn_AK15_J3_RX0_N J3_RX0_N | AK15 from line 404 of fpga_mezz_no_conn_nets 62 = No_Conn_AK16_J3_RX3_N J3_RX3_N | AK16 from line 410 of fpga_mezz_no_conn_nets 103 = No_Conn_AK18_J3_TX10_N J3_TX10_N | AK18 from line 369 of fpga_mezz_no_conn_nets 115 = No_Conn_AK20_J3_TX12_N J3_TX12_N | AK20 from line 373 of fpga_mezz_no_conn_nets 121 = No_Conn_AK21_J3_TX13_N J3_TX13_N | AK21 from line 375 of fpga_mezz_no_conn_nets 109 = No_Conn_AK23_J3_TX11_N J3_TX11_N | AK23 from line 371 of fpga_mezz_no_conn_nets 110 = No_Conn_AK25_J3_RX11_N J3_RX11_N | AK25 from line 432 of fpga_mezz_no_conn_nets 76 = No_Conn_J3_NC_Pin_76 NC | from line 414 of fpga_mezz_no_conn_nets 150 = No_Conn_W21_J3_RX18_P J3_RX18_P | W21 from line 452 of fpga_mezz_no_conn_nets 152 = No_Conn_Y21_J3_RX18_N J3_RX18_N | Y21 from line 453 of fpga_mezz_no_conn_nets 138 = No_Conn_Y22_J3_RX16_P J3_RX16_P | Y22 from line 446 of fpga_mezz_no_conn_nets 140 = No_Conn_Y23_J3_RX16_N J3_RX16_N | Y23 from line 447 of fpga_mezz_no_conn_nets 101 = PLL_40_MHz_Locked_Mon J3_TX10_P | AK17 from line 105 of clock_generation_nets 38 = Ref_40_MHz_to_SiLab_Cmp SI5328_CLK1_P | from line 181 of clock_generation_nets 40 = Ref_40_MHz_to_SiLab_Dir SI5328_CLK1_N | from line 180 of clock_generation_nets 141 = TCK_TO_FPGA_MEZZ TCK | Y12 from line 115 of jtag_and_j12_associated_nets 147 = TDI_TO_FPGA_MEZZ TDI | P10 from line 120 of jtag_and_j12_associated_nets 148 = TDO_From_FPGA_Mezz TDO | Y10 from line 129 of jtag_and_j12_associated_nets 142 = TMS_TO_FPGA_MEZZ TMS | V10 from line 110 of jtag_and_j12_associated_nets