Found 48 pins for TRANS1 which is of type Pulse_HX5201NL ------------------------------------------------------ Pins sorted by Pin Name L1 = PHY_2_TRD0_6_DIR Left TD0+ from line 137 of enet_j14_trans1_fpga_mezz_nets L2 = TRANS1_L_A_0_PRI_CT Left TCT0 from line 185 of enet_j14_trans1_fpga_mezz_nets L3 = PHY_2_TRD0_6_CMP Left TD0- from line 138 of enet_j14_trans1_fpga_mezz_nets L4 = PHY_2_TRD1_6_DIR Left TD1+ from line 140 of enet_j14_trans1_fpga_mezz_nets L5 = TRANS1_L_B_1_PRI_CT Left TCT1 from line 186 of enet_j14_trans1_fpga_mezz_nets L6 = PHY_2_TRD1_6_CMP Left TD1- from line 141 of enet_j14_trans1_fpga_mezz_nets L7 = J14_L_A_0_DIR Left MX0+ from line 153 of enet_j14_trans1_fpga_mezz_nets L8 = TRANS1_L_A_0_SEC_CT Left MCT0 from line 210 of enet_j14_trans1_fpga_mezz_nets L9 = J14_L_A_0_CMP Left MX0- from line 154 of enet_j14_trans1_fpga_mezz_nets R1 = PHY_1_TRD0_6_DIR Right TD0+ from line 98 of enet_j14_trans1_fpga_mezz_nets R2 = TRANS1_R_A_0_PRI_CT Right TCT0 from line 177 of enet_j14_trans1_fpga_mezz_nets R3 = PHY_1_TRD0_6_CMP Right TD0- from line 99 of enet_j14_trans1_fpga_mezz_nets R4 = PHY_1_TRD1_6_DIR Right TD1+ from line 101 of enet_j14_trans1_fpga_mezz_nets R5 = TRANS1_R_B_1_PRI_CT Right TCT1 from line 178 of enet_j14_trans1_fpga_mezz_nets R6 = PHY_1_TRD1_6_CMP Right TD1- from line 102 of enet_j14_trans1_fpga_mezz_nets R7 = J14_U_A_0_DIR Right MX0+ from line 114 of enet_j14_trans1_fpga_mezz_nets R8 = TRANS1_R_A_0_SEC_CT Right MCT0 from line 200 of enet_j14_trans1_fpga_mezz_nets R9 = J14_U_A_0_CMP Right MX0- from line 115 of enet_j14_trans1_fpga_mezz_nets L10 = J14_L_B_1_DIR Left MX1+ from line 156 of enet_j14_trans1_fpga_mezz_nets L11 = TRANS1_L_B_1_SEC_CT Left MCT1 from line 211 of enet_j14_trans1_fpga_mezz_nets L12 = J14_L_B_1_CMP Left MX1- from line 157 of enet_j14_trans1_fpga_mezz_nets L13 = J14_L_D_3_CMP Left MX3- from line 163 of enet_j14_trans1_fpga_mezz_nets L14 = TRANS1_L_D_3_SEC_CT Left MCT3 from line 213 of enet_j14_trans1_fpga_mezz_nets L15 = J14_L_D_3_DIR Left MX3+ from line 162 of enet_j14_trans1_fpga_mezz_nets L16 = J14_L_C_2_CMP Left MX2- from line 160 of enet_j14_trans1_fpga_mezz_nets L17 = TRANS1_L_C_2_SEC_CT Left MCT2 from line 212 of enet_j14_trans1_fpga_mezz_nets L18 = J14_L_C_2_DIR Left MX2+ from line 159 of enet_j14_trans1_fpga_mezz_nets L19 = PHY_2_TRD3_6_CMP Left TD3- from line 147 of enet_j14_trans1_fpga_mezz_nets L20 = TRANS1_L_D_3_PRI_CT Left TCT3 from line 188 of enet_j14_trans1_fpga_mezz_nets L21 = PHY_2_TRD3_6_DIR Left TD3+ from line 146 of enet_j14_trans1_fpga_mezz_nets L22 = PHY_2_TRD2_6_CMP Left TD2- from line 144 of enet_j14_trans1_fpga_mezz_nets L23 = TRANS1_L_C_2_PRI_CT Left TCT2 from line 187 of enet_j14_trans1_fpga_mezz_nets L24 = PHY_2_TRD2_6_DIR Left TD2+ from line 143 of enet_j14_trans1_fpga_mezz_nets R10 = J14_U_B_1_DIR Right MX1+ from line 117 of enet_j14_trans1_fpga_mezz_nets R11 = TRANS1_R_B_1_SEC_CT Right MCT1 from line 201 of enet_j14_trans1_fpga_mezz_nets R12 = J14_U_B_1_CMP Right MX1- from line 118 of enet_j14_trans1_fpga_mezz_nets R13 = J14_U_D_3_CMP Right MX3- from line 124 of enet_j14_trans1_fpga_mezz_nets R14 = TRANS1_R_D_3_SEC_CT Right MCT3 from line 203 of enet_j14_trans1_fpga_mezz_nets R15 = J14_U_D_3_DIR Right MX3+ from line 123 of enet_j14_trans1_fpga_mezz_nets R16 = J14_U_C_2_CMP Right MX2- from line 121 of enet_j14_trans1_fpga_mezz_nets R17 = TRANS1_R_C_2_SEC_CT Right MCT2 from line 202 of enet_j14_trans1_fpga_mezz_nets R18 = J14_U_C_2_DIR Right MX2+ from line 120 of enet_j14_trans1_fpga_mezz_nets R19 = PHY_1_TRD3_6_CMP Right TD3- from line 108 of enet_j14_trans1_fpga_mezz_nets R20 = TRANS1_R_D_3_PRI_CT Right TCT3 from line 180 of enet_j14_trans1_fpga_mezz_nets R21 = PHY_1_TRD3_6_DIR Right TD3+ from line 107 of enet_j14_trans1_fpga_mezz_nets R22 = PHY_1_TRD2_6_CMP Right TD2- from line 105 of enet_j14_trans1_fpga_mezz_nets R23 = TRANS1_R_C_2_PRI_CT Right TCT2 from line 179 of enet_j14_trans1_fpga_mezz_nets R24 = PHY_1_TRD2_6_DIR Right TD2+ from line 104 of enet_j14_trans1_fpga_mezz_nets ------------------------------------------------------ Pins sorted by Net Name L9 = J14_L_A_0_CMP Left MX0- from line 154 of enet_j14_trans1_fpga_mezz_nets L7 = J14_L_A_0_DIR Left MX0+ from line 153 of enet_j14_trans1_fpga_mezz_nets L12 = J14_L_B_1_CMP Left MX1- from line 157 of enet_j14_trans1_fpga_mezz_nets L10 = J14_L_B_1_DIR Left MX1+ from line 156 of enet_j14_trans1_fpga_mezz_nets L16 = J14_L_C_2_CMP Left MX2- from line 160 of enet_j14_trans1_fpga_mezz_nets L18 = J14_L_C_2_DIR Left MX2+ from line 159 of enet_j14_trans1_fpga_mezz_nets L13 = J14_L_D_3_CMP Left MX3- from line 163 of enet_j14_trans1_fpga_mezz_nets L15 = J14_L_D_3_DIR Left MX3+ from line 162 of enet_j14_trans1_fpga_mezz_nets R9 = J14_U_A_0_CMP Right MX0- from line 115 of enet_j14_trans1_fpga_mezz_nets R7 = J14_U_A_0_DIR Right MX0+ from line 114 of enet_j14_trans1_fpga_mezz_nets R12 = J14_U_B_1_CMP Right MX1- from line 118 of enet_j14_trans1_fpga_mezz_nets R10 = J14_U_B_1_DIR Right MX1+ from line 117 of enet_j14_trans1_fpga_mezz_nets R16 = J14_U_C_2_CMP Right MX2- from line 121 of enet_j14_trans1_fpga_mezz_nets R18 = J14_U_C_2_DIR Right MX2+ from line 120 of enet_j14_trans1_fpga_mezz_nets R13 = J14_U_D_3_CMP Right MX3- from line 124 of enet_j14_trans1_fpga_mezz_nets R15 = J14_U_D_3_DIR Right MX3+ from line 123 of enet_j14_trans1_fpga_mezz_nets R3 = PHY_1_TRD0_6_CMP Right TD0- from line 99 of enet_j14_trans1_fpga_mezz_nets R1 = PHY_1_TRD0_6_DIR Right TD0+ from line 98 of enet_j14_trans1_fpga_mezz_nets R6 = PHY_1_TRD1_6_CMP Right TD1- from line 102 of enet_j14_trans1_fpga_mezz_nets R4 = PHY_1_TRD1_6_DIR Right TD1+ from line 101 of enet_j14_trans1_fpga_mezz_nets R22 = PHY_1_TRD2_6_CMP Right TD2- from line 105 of enet_j14_trans1_fpga_mezz_nets R24 = PHY_1_TRD2_6_DIR Right TD2+ from line 104 of enet_j14_trans1_fpga_mezz_nets R19 = PHY_1_TRD3_6_CMP Right TD3- from line 108 of enet_j14_trans1_fpga_mezz_nets R21 = PHY_1_TRD3_6_DIR Right TD3+ from line 107 of enet_j14_trans1_fpga_mezz_nets L3 = PHY_2_TRD0_6_CMP Left TD0- from line 138 of enet_j14_trans1_fpga_mezz_nets L1 = PHY_2_TRD0_6_DIR Left TD0+ from line 137 of enet_j14_trans1_fpga_mezz_nets L6 = PHY_2_TRD1_6_CMP Left TD1- from line 141 of enet_j14_trans1_fpga_mezz_nets L4 = PHY_2_TRD1_6_DIR Left TD1+ from line 140 of enet_j14_trans1_fpga_mezz_nets L22 = PHY_2_TRD2_6_CMP Left TD2- from line 144 of enet_j14_trans1_fpga_mezz_nets L24 = PHY_2_TRD2_6_DIR Left TD2+ from line 143 of enet_j14_trans1_fpga_mezz_nets L19 = PHY_2_TRD3_6_CMP Left TD3- from line 147 of enet_j14_trans1_fpga_mezz_nets L21 = PHY_2_TRD3_6_DIR Left TD3+ from line 146 of enet_j14_trans1_fpga_mezz_nets L2 = TRANS1_L_A_0_PRI_CT Left TCT0 from line 185 of enet_j14_trans1_fpga_mezz_nets L8 = TRANS1_L_A_0_SEC_CT Left MCT0 from line 210 of enet_j14_trans1_fpga_mezz_nets L5 = TRANS1_L_B_1_PRI_CT Left TCT1 from line 186 of enet_j14_trans1_fpga_mezz_nets L11 = TRANS1_L_B_1_SEC_CT Left MCT1 from line 211 of enet_j14_trans1_fpga_mezz_nets L23 = TRANS1_L_C_2_PRI_CT Left TCT2 from line 187 of enet_j14_trans1_fpga_mezz_nets L17 = TRANS1_L_C_2_SEC_CT Left MCT2 from line 212 of enet_j14_trans1_fpga_mezz_nets L20 = TRANS1_L_D_3_PRI_CT Left TCT3 from line 188 of enet_j14_trans1_fpga_mezz_nets L14 = TRANS1_L_D_3_SEC_CT Left MCT3 from line 213 of enet_j14_trans1_fpga_mezz_nets R2 = TRANS1_R_A_0_PRI_CT Right TCT0 from line 177 of enet_j14_trans1_fpga_mezz_nets R8 = TRANS1_R_A_0_SEC_CT Right MCT0 from line 200 of enet_j14_trans1_fpga_mezz_nets R5 = TRANS1_R_B_1_PRI_CT Right TCT1 from line 178 of enet_j14_trans1_fpga_mezz_nets R11 = TRANS1_R_B_1_SEC_CT Right MCT1 from line 201 of enet_j14_trans1_fpga_mezz_nets R23 = TRANS1_R_C_2_PRI_CT Right TCT2 from line 179 of enet_j14_trans1_fpga_mezz_nets R17 = TRANS1_R_C_2_SEC_CT Right MCT2 from line 202 of enet_j14_trans1_fpga_mezz_nets R20 = TRANS1_R_D_3_PRI_CT Right TCT3 from line 180 of enet_j14_trans1_fpga_mezz_nets R14 = TRANS1_R_D_3_SEC_CT Right MCT3 from line 203 of enet_j14_trans1_fpga_mezz_nets