Found 10 pins for U253 which is of type IC_PLL_40M0787 ------------------------------------------------------ Pins sorted by Pin Name 1 = Bk_Trm_Rcvd_Hub_1_Ref_Clk Input Frequency from line 96 of clock_generation_nets 2 = GROUND Ground from line 109 of clock_generation_nets 3 = No_Conn_PLL_pin_3 Active Low Reset from line 112 of clock_generation_nets 4 = No_Conn_PLL_pin_4 Do Not Connect from line 113 of clock_generation_nets 5 = No_Conn_PLL_pin_5 Do Not Connect from line 114 of clock_generation_nets 6 = PLL_40_Clk_Out_Dir Direct Freq Output from line 98 of clock_generation_nets 7 = PLL_40_Clk_Out_Cmp Compl Freq Output from line 99 of clock_generation_nets 8 = GROUND Ground from line 109 of clock_generation_nets 9 = CLK_3V3 VCC 3V3 from line 107 of clock_generation_nets 10 = Raw_PLL_40_MHz_Locked Lock Detect from line 104 of clock_generation_nets ------------------------------------------------------ Pins sorted by Net Name 1 = Bk_Trm_Rcvd_Hub_1_Ref_Clk Input Frequency from line 96 of clock_generation_nets 9 = CLK_3V3 VCC 3V3 from line 107 of clock_generation_nets 2 = GROUND Ground from line 109 of clock_generation_nets 8 = GROUND Ground from line 109 of clock_generation_nets 3 = No_Conn_PLL_pin_3 Active Low Reset from line 112 of clock_generation_nets 4 = No_Conn_PLL_pin_4 Do Not Connect from line 113 of clock_generation_nets 5 = No_Conn_PLL_pin_5 Do Not Connect from line 114 of clock_generation_nets 7 = PLL_40_Clk_Out_Cmp Compl Freq Output from line 99 of clock_generation_nets 6 = PLL_40_Clk_Out_Dir Direct Freq Output from line 98 of clock_generation_nets 10 = Raw_PLL_40_MHz_Locked Lock Detect from line 104 of clock_generation_nets