Found 20 pins for U254 which is of type IC_CDCLVD1204 ------------------------------------------------------ Pins sorted by Pin Name 1 = GROUND GND from line 128 of clock_generation_nets 2 = Fan_40_MHz_In_Sel IN_SEL low=IN0 from line 135 of clock_generation_nets 3 = Fan_40_MHz_In_2_Bias INP1 from line 137 of clock_generation_nets 4 = FanOut_Input_CMM_Ref INN1 from line 126 of clock_generation_nets 5 = CLK_2V5 VCC 2V5 from line 131 of clock_generation_nets 6 = PLL_40_MHz_Signal_Dir INP0 from line 123 of clock_generation_nets 7 = PLL_40_MHz_Signal_Cmp INN0 from line 124 of clock_generation_nets 8 = FanOut_Input_CMM_Ref VAC_REF from line 126 of clock_generation_nets 9 = No_Conn_Clk_Fanout_9 OUTP0 from line 141 of clock_generation_nets 10 = No_Conn_Clk_Fanout_10 OUTN0 from line 142 of clock_generation_nets 11 = Mon_Cp_40_Clk_Dir OUTP1 from line 190 of clock_generation_nets 12 = Mon_Cp_40_Clk_Cmp OUTN1 from line 191 of clock_generation_nets 13 = Pre_Cap_FPGA_40_MHz_Logic_Clk_Dir OUTP2 from line 157 of clock_generation_nets 14 = Pre_Cap_FPGA_40_MHz_Logic_Clk_Cmp OUTN2 from line 158 of clock_generation_nets 15 = Pre_Cap_40_MHz_SiLab_Dir OUTP3 from line 177 of clock_generation_nets 16 = Pre_Cap_40_MHz_SiLab_Cmp OUTN3 from line 178 of clock_generation_nets 17 = GROUND Thrm Gnd from line 129 of clock_generation_nets 18 = GROUND Thrm Gnd from line 129 of clock_generation_nets 19 = GROUND Thrm Gnd from line 129 of clock_generation_nets 20 = GROUND Thrm Gnd from line 129 of clock_generation_nets ------------------------------------------------------ Pins sorted by Net Name 5 = CLK_2V5 VCC 2V5 from line 131 of clock_generation_nets 4 = FanOut_Input_CMM_Ref INN1 from line 126 of clock_generation_nets 8 = FanOut_Input_CMM_Ref VAC_REF from line 126 of clock_generation_nets 3 = Fan_40_MHz_In_2_Bias INP1 from line 137 of clock_generation_nets 2 = Fan_40_MHz_In_Sel IN_SEL low=IN0 from line 135 of clock_generation_nets 1 = GROUND GND from line 128 of clock_generation_nets 20 = GROUND Thrm Gnd from line 129 of clock_generation_nets 17 = GROUND Thrm Gnd from line 129 of clock_generation_nets 19 = GROUND Thrm Gnd from line 129 of clock_generation_nets 18 = GROUND Thrm Gnd from line 129 of clock_generation_nets 12 = Mon_Cp_40_Clk_Cmp OUTN1 from line 191 of clock_generation_nets 11 = Mon_Cp_40_Clk_Dir OUTP1 from line 190 of clock_generation_nets 10 = No_Conn_Clk_Fanout_10 OUTN0 from line 142 of clock_generation_nets 9 = No_Conn_Clk_Fanout_9 OUTP0 from line 141 of clock_generation_nets 7 = PLL_40_MHz_Signal_Cmp INN0 from line 124 of clock_generation_nets 6 = PLL_40_MHz_Signal_Dir INP0 from line 123 of clock_generation_nets 16 = Pre_Cap_40_MHz_SiLab_Cmp OUTN3 from line 178 of clock_generation_nets 15 = Pre_Cap_40_MHz_SiLab_Dir OUTP3 from line 177 of clock_generation_nets 14 = Pre_Cap_FPGA_40_MHz_Logic_Clk_Cmp OUTN2 from line 158 of clock_generation_nets 13 = Pre_Cap_FPGA_40_MHz_Logic_Clk_Dir OUTP2 from line 157 of clock_generation_nets