Requirements for designing the Hub Test Module

Rev: 24-Mar-2017


Minimum = Support full functional test of Hub in Slot 1
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    Use power from ATCA crate

    Fit in ATCA slot
      More specifically: able to populate the 12 node slots of a 14 slot crate
      Can be inserted and extracted without interfering with Hubs or other HTMs
      Does not reduce or significantly change airflow over Hubs
      
    No external tentacles required (for power, JTAG) during production testing
      Except Ethernet port(s), if necessary
      Debugging first Hub or HTM cards can/should break this rule
        JTAG access for debugging firmware or hardware 

    Receive LHC clock from Hub1
      Use it to synchronize all data sent or received to/from either Hub
        Generate reference clock to receive Combined Data
        Generate reference clock to source for Readout Data

    Receive Combined Data from Hub1 at 6.4 Mbps minimum

    Source 6 lanes of Aurora-capable Readout Data to Hub1 at 6.4 Mbps minimum
      lower level tests may send per-lane pseudo-random data for Bit-Error test

    Access to the backplane Ethernet port from Hub1
      Presumably connect it to the FPGA and implement IPbus
      Alternatively just connect to an RJ45 connector
      If the mezanine board already has an RJ45 connecting to the FPGA
        Could use patch to support both of above

    Configure itself at power up 
      no JTAG needed for production testing
      May even hold more than one configuration, see Improvement A



    The firmware needs to be controllable from a computer orchestrating a series of tests

      Presumably via the Hub1 switch and IPbus,
        But could be separate port or protocol if necessary

      Read status of received LHC clock from Hub1
        Maybe just PLL lock status

      Read status and content of received Combined Data from Hub1
        Status of MGT link
        Content may be fixed data defined on Hub
        Maybe receive simulated data using official protocol

      Control payload of Readout Data sent to Hub1
        Presumably Aurora but jFEX uses individual lanes
        Fixed data (short pattern)
        Playback memory (long pattern)
        Pseudo-random for bit-error test

      Implement some number of "dummy" IPbus registers
         For random register test through switch


Improvement A = Stop readout source
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    Start/stop MGT source, especially for first cards or debugging
      May need to load different firmware to "stop" serial link
      Could be via reload of specific firmware triggered from computer


Improvement B = Backplane speed increase
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    Increase backplane readout rate to Hub(s) to 9.6 and 11.2 Gbps


Improvement C = Support testing of both hub slots
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    Receive the LHC clock from Hub2
      Note: nominal usage is no clock sent from Hub2

    Receive Combined Data from Hub2
      Note: initial usage is no Combined Data sent from Hub2

    Source 6 lanes of Aurora-capable Readout Data to Hub2 at 6.4 Mbps minimum

    Access to the backplane Ethernet port from Hub2
      Separate IPbus connection to FPGA
      Or connect to an RJ45 connector



    Corresponding firmware controllable from a computer as for above