{"text_format":"1","workbook":"xlsx","n_sheets":9,"sheets":["Overview","Notes_&_Disclaimers","FPGA_BOARDS","CARRIER_BOARDS","CurrentConfiguration","TE-Configuration","PINOUT_TEMPLATE","PINOUT_TABLE_LAYOUT","Docu"],"not_rendered":{"charts":0,"images":36,"macros":1,"external_links":0,"defined_names":6,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900"}

{"sheet":"Overview","index":0,"n_rows":27,"n_cols":13,"rows_kept":27,"cut":false,"hidden":false,"merged":[[26,5,26,6],[26,7,26,8],[24,5,24,8],[25,10,25,11],[25,5,25,6],[25,7,25,8],[24,10,24,17],[25,12,25,17]]}
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[null,"1."]
[]
[]
[null,"2."]
[]
[]
[null,"3."]
[]
[]
[]
[]
[]
[null,"4.",null,null,null,"Selected Modul Information",null,null,null,null,"Selected Carrier Board Information"]
[null,null,null,null,null,"Name",null,"---",null,null,"Name",null,"---"]
[null,null,null,null,null,"FPGA Family",null,"---"]

{"sheet":"Notes_&_Disclaimers","index":1,"n_rows":26,"n_cols":18,"rows_kept":26,"cut":false,"hidden":false,"merged":[]}
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[null,null,null,null,"Notes"]
[null,null,null,null,"1. ","Published by Trenz Electronic GmbH, Holzweg 19A, 32257 Bünde, Germany."]
[null,null,null,null,"2. ",{"$f":"\"Master Pinout Version \" & 'TE-Configuration'!B8 & \", last update at \" & TEXT('TE-Configuration'!B9,\"TT.MM.JJJ hh:mm:ss\") & \".\"","v":"Master Pinout Version 1.51, last update at 23.03.2018 11:17:00."}]
[null,null,null,null,"3.","Detailed information’s of modules and carrier boards are available on the ",null,null,null,null,null,"Trenz Electronic Wiki",null,"."]
[null,null,null,null,"4.","Are you interested in a custom pcb design? Send a request to ",null,null,null,null,"support@trenz-electronic.de ",null,"."]
[]
[null,null,null,null,"Disclaimers"]
[null,null,null,null,"1.","All pinouts and pin information is provided as-is without assurence of correctness or completeness."]
[null,null,null,null,"2.","All information is subject to change at any time without notice."]
[null,null,null,null,"3.","Please verify all data with user manuals, FPGA and other components vendor's documentation."]
[]
[null,null,null,null,"Notes for pinout tables sheets"]
[null,null,null,null,"1.","Green cells  are editable."]
[null,null,null,null,"2.","Yellow cells are odd and orange cells are even pin numbers. (currently disabled)"]
[null,null,null,null,"3.","Tables can be filtered by values or by color."]
[null,null,null,null,"4.","Filter sort function has only affect on the selected table, but filter properties has effect on all tables (rows are hidden only in excel)!"]
[null,null,null,null,"5.","To change multiple lines, sort by color and “Copy-Past” your preferred value into the cells."]
[null,null,null,null,"6. ","\"Write XDC File\" generate package pin loc-constrains from all selected module names and module FPGA-pins"]
[]
[null,null,null,null,"Notes for  4x5 SoMs"]
[null,null,null,null,"1.","Overview of Power Managment configuration for 4x5 Modules with our Carrier Boards is available on Trenz Electronic Wiki",null,null,null,null,null,null,null,null,null,"4x5 Module Integration Guide",null,"."]

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[]
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[]
[]
[null,null,null,null,null,"Board-Module connecting plug pair",null,null,null,null,null,null,null,null,null," Modul connecting plug"]
[null,null,null,null,null,null,"Module:",null,null,"Mapping","Base Board:",null,null,null,null,null,"Module:"]
[null,"FPGA Bank Voltages",null,null,null,null,"Connector Name:",null,null,null,"Connector Name:",null,null,null,null,null,"Connector Name:"]
[null,"Module:","XXX",null,null,null,"Connector Pins:",null,null,null,"Connector Pins:",null,null,null,null,null,"Connector Pins:"]
[null,"Bank","Value",null,null,"XDC-Export","FPGA Pin","Schem. Name","PIN Number"," ","Pin Number","Comp. Pin / Name","Side",null,null,"XDC-Export","FPGA Pin","Schem. Name","PIN Number"]
[null,null,null,null,null,"Yes",null,null,null,"↔"]
[null,null,null,null,null,"No"]
[null,null,null,null,null,"No"]

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[]
["Image Size","H",5.87]
[null,"B",8.41]
[]
["FPGA_BOARDS Tables, Pin Order must be same as compatible Carrier board -->Position is Pin matching"]
["CONNECTORS_MODUL_X_PIN_CNT Same as compatible Carrier Board or Zero"]
[]
[]
["Ignore Source List Entry:"]
["COMPATIBLE_ID = IGNORE"]
[]
[]
["Todo: Boarder,MappingCol and XDC Line on table items!"]