Hub Virtex FPGA GTY and GTH Transceiver Test (IBERT)
   ------------------------------------------------

                                                   Original Rev. 03-Mar-2016
  						    Current Rev. 04-Mar-2016

                                                   Author: Pawel Plucinski




   Notes:
  --------

     - The xcvu125_flvc2104. FPGA on the Hub Module contains 40 GTY and 40 GTH Transceivers.

     - Half of GTY/GTH transceiver type is in each of the two Super-Logic-Regions.

     - MGT reference clock cannot be shared across SLR.

     - In the design, the logic clock (320.64 MHz) is connected as the LVDS I/O standard to
       the HP-Bank 71. There was a problem to connect the logic clock as the LVPECL I/O standard
       to the HP-Bank 71 (Vivado reports the error). In order to solve the problem the attributes:
       DQS_BIAS and EQ_LEVEL_0 will be added to the XDC file. This will be checked soon.

     - IBERT for UltraScale GTY/GTH Transceivers. IP integrated Bit Error Ratio Tester (IBERT)
       core for UltraScale architecture is designed for evaluating and monitoring
       the GTY/GTH transceivers.
       
     - This firmware is based on the IBERT to check if all of the MGT Transceivers are connected
       in the way that we need them for the Hub to perform its various functions.
    
     - Initial firmware is written to use a fixed line speed. The specific firmware will be
       developed to check various line speeds with the protocol required by L1Calo.
    
     - In order to configure the GTY/GTH IBERT properly one should follow the steps:
          
        - LineRate (Gbps)
        - RefClk (MHz)
        - Quad Count
        - PLL 
        - RefClk Selection (connect a proper RefClk)
        - Clock Settings (Source, I/O Standard, P Package PIN, Frequency - MHz)


     - Vivado automatically generates the sources which are needed to handle the GTY/GTH transceivers. 

     - User is obliged to control all the Vivado sources (including the pin locations, constraints, etc).

     - The final step: Vivado synthesis, Implementation and the bit file generation. 

     - The configuration bit file is generated.  

     - The pin locations automatically generated by Vivado fits to Dan's documentation.        


    Vivado Plots: 
   --------------



  1. The design implementation. Visible SLR0 and SLR1. 
 ----------------------------------------------------

  gty_implemented_design.jpg    
  gth_implemented_design.jpg


  2. Power consumption 
 --------------------

  gty_power.jpg                 
  gth_power.jpg


  3. FPGA utilization
 --------------------

  gty_util.jpg                  
  gth_util.jpg


  4. IBERT configuration; protocol definition
 -------------------------------------------

  LineRate:     (6.4128Gbps)
  DataWidth:    (80)
  RefClk:       (320.64 MHz)
  Quad Count:   (10)
  PLL:          (QPLL0)

  gty_protocol_definition.jpg   
  gth_protocol_definition.jpg

 
  5. IBERT configuration; protocol selection
 --------------------------------------------

  gty_protocol_selection.jpg    
  gth_protocol_selection.jpg


  6. IBERT configuration; clock settings (320.64 MHz)
 -------------------------------------------------

  gty_sysclock.jpg              
  gth_sysclock.jpg


  7. Refclk0_125 - pin location 
 ----------------------------

  gty_refclk0_125.jpg           
  gth_refclk0_125.jpg

  8. Refclk0_132 - pin location
 -----------------------------

  gty_refclk0_132.jpg           
  gth_refclk0_132.jpg

  9. Refclk1_127 - pin location
 ----------------------------

  gty_refclk1_127.jpg           
  gtx_refclk1_127.jpg           


  10. Refclk1_130 - pin location
 -----------------------------

  gty_refclk1_130.jpg           
  gth_refclk1_130.jpg           


  11. Refclk and sysclk - pin location, I/O standard, Bank, SLR.
 -----------------------------------------------------------

  gty_refclk_and_sysclk_loc.jpg 
  gth_refclk_and_sysclk_loc.jpg 


  12. RXP - pin location, Bank, SLR.
 --------------------------------

  gty_rxp_loc.jpg               
  gty_rxp_loc.jpg               

  13. TXP - pin location, Bank, SLR.
 --------------------------------

  gty_txp_loc.jpg               
  gth_txp_loc.jpg


  14. Sysclock - pin location
 -------------------------

  gty_sysclock_lock.jpg         
  gth_sysclock_lock.jpg