Hub SN17 Addendum, 01 JUN - 08 JUN 2020

Day 1:
- Initial power-up shows that BULK_3V3 power supply isn't coming up. Poking around with my 
  meter and Huntron shows that GND and Vout appear to be directly shorted.
- Because BULK_3V3 isn't coming up, neither do MGT_AVAUX and BULK_2V5.
- Which also leaves CLK_3V3 and CLK_2V5 down.

Day 2:
- Methodically removed all subsequent loads from BULK_3V3 and checked for shorts
  after each step:
	- Removed L1151 to disconnect MGT_AVAUX
	- Removed L351 and L352 to disconnect CLK_3V3 and CLK2V5
	- Removed each PLL and its corresponding LVD transceiver
	- Removed L2421 and L2441 to disconnect the Minipods' connectors
	- Removed L1171 to disconnect BULK_2V5
	- Removed L##04, L##05, and L##06 to disconnect all the Broadcoms one at a time
	- Removed L1905 and L1955 to disconnect the Phys chips
- At that point, all that was left was to start pulling parts directly from DCDC8's output
  filter section:
	- Removed DZ1351
	- Removed C1371, C1372, C1373, C1374, C1375, C1376, C1377
- Measured resistance from GND to BULK_3V3 still reads 0 Ohms when you factor out the 
  resistance of my leads.

Day 3:
- After investigation based on advice from Dan, found capacitor C393 shorted to GND. This
  is the CLK_3V3 input filter for the 25MHz ethernet clock, and is seen at the far left
  side of Drawing 39 hub/hardware/drawings/Circuit_Diagrams/39_hub_25_MHz_ethernet_clock.pdf

  I was able to power up the board and verify the power supplies' configurations,
  and verify that their output was correct.

    		 Power Bus:      FPGA     MGT     MGT    Swch    Bulk     Fan    Bulk
       		                 Core    AVCC    AVTT     1V2     1V8     1V8     3V3
                       	         ----    ----    ----    ----    ----    ----    ----
       		   Address:       40      41      42      43      44      45      46
         	     Volts:     0.939    1.001   1.199  1.199   1.790   1.823    3.306
	              Amps:     1.062    0.000   0.125  1.750   0.562  12.000    1.625
	       Fluke Volts:     0.954    1.000   1.200  1.200   1.798   1.798    3.309
		   ISO_12V: 12.000
		      Vref: 2.391

- The 40MHz clock actually has no output as of now, not even free-run. This is my next
  puzzle to solve.


- Day 4:
- The 40MHz PLL was bad. Once I replaced the PLL, I was able to verify both PLLs and
  their upper/lower lock limits. I've also verified the 25MHz and Spare 40MHz
  oscillators.
- This unit has now been through the entire final acceptance procedure. 
	- Voltage checks as above;
	- PLL checks as below;
	- Verified settings on power supplies using DPI-CLI;
	- I erased, blank-checked, and re-flashed the FPGA EEPROM just in case.


			PLL	Free Run	Hi-Lock		Lo-Lock
			------	--------	-------		-------
			40MHz	 40.08		 40.0842	 40.0734
			320MHz	320.5		 40.0812	 40.0753


- Still to-do:
	- Verify clock fanouts;
	- Re-install FPGA heat sink;
	- Re-install minipods & fiber ribbons;
	- Flash IPMC with correct binaries.

08 JUN 2020
- Unit's FPGA heat sink, minipods and fiber ribbons have been installed.
- IPMC module has been flashed.
- Unit is going into the 14SS for IBERT testing.

09 JUN 2020
- Unit ran with no errors for 24hrs in Slot #2 of the 14SS.
- Moved to Slot #1

11 JUN 2020
- Unit ran with no errors for 24hrs in Slot #1 of the 14SS.