Clock Circuit Tests of the Hub Modules ------------------------------------------ Original Rev. 31-Oct-2019 Current Rev. 7-Nov-2019 Because of the difficulty and risk to the Hub Module in removing the heat sink from its FPGA, there are a number of bench tests that should be done on each Hub before the FPGA heat sink is installed. These various tests are listed in the MSU Final Assembly document for the Production Hub Modules. This note is a fuller description of the tests that should be done on the Hub Clock System before this heat sink is installed. These on bench Clock System tests are also important because no detailed tests of the Clock System are done once the Hub Module is in the ATCA Shelf. The Hub Clock System bench tests described here are intended to: - measure the free run frequency of the 40.08 MHz PLL - measure the re-lock range of the 40.08 MHz and 320 MHz PLLs - check that all clock fanout signals are running, checking both sides of all the differential clock signals - measure the frequency of the on board "spare oscillator" once it is installed The first three of these tests must be done before the spare oscillator U562 is installed on the Hub pcb. Note also that the Hub FPGA must be configured with the Safe Foundation firmware for these tests. As shown in Hub Circuit Drawing number 40A this firmware is needed to instantiate the Hub Clock Reference Selector Switch and to set this switch to the spare oscillator position. Measure the Free Run Frequency of the 40.08 MHz PLL: ---------------------------------------------------- This test is accomplished by simply by using a scope probe to connect the A Input of the Fluke frequency counter to one of the output pins of the 40.08 MHz PLL. One of the close by 4-40 mounting screws for the not yet installed heat sink is a convenient ground point to connect the scope probe's ground clip to. The free run frequency of the PLL should be in the range of 40.0787 MHz but this frequency can be expected to drift around a bit because there is no reference for the PLL to lock to. The point of measuring and recording this free run frequency is to verify that this Hub's 40.08 MHz PLL is operating in the same way as this PLL does on the other Hubs. Measure the Re-Lock Range of the 40.08 MHz and 320 MHz PLLs: ------------------------------------------------------------ This test is accomplished by using the output of the HP Generator as the reference for the 40.08 MHz PLL and adjusting the frequency of the HP Generator to find the lower and upper re-lock frequencies of both the 40.08 MHz and 320.64 MHz PLLs (the capture frequencies in PLL speak). This set of tests uses the HP Generator, the Fluke Counter, and a scope. The Sync output of the HP Generator is connected to the Fluke Counter A input and to Channel #1 input of the scope. The scope trigger should be set to Channel #1 and the scope adjusted to give a nice display of 2 cycles or so of the HP Generator square wave Sync output signal. The Fluke Counter is setup to measure this Sync signal and gives a confirmation of the HP Generator's frequency. These connections can be made with short BNC cables. BNC cables with coaxial chokes help prevent RF ground loops. The main output of the HP Generator is connected to the single ended to differential transformer that is used to send the reference to the Hub Module. To start with the main output of the HP Generator can be set to 40.0787 MHz and 300 mVpp symmetric around ground (as it is driving a transformer primary). The output of the single ended to differential adapter is connected to pins 4 and 5 of the not yet installed U562 Spare Oscillator pcb location. The ground wire of the single ended to differential adapter must be connected to the Hub pcb ground. I have used one of the 4-40 heat sink mounting screws to make this ground connection. A scope probe on Ch #2 of the scope is used to look at one of the output pins on either the 40.08 MHz or 320.64 MHz PLL. Starting with the 40.08 MHz PLL and with the HP Generator set to 40.0787 MHz the generator's Sync waveform on scope Ch #1 should be in lock with the PLL output waveform on scope Ch #2. With this setup the following tests can be made: - Manually adjust the frequency of the HP Generator up until the lock is lost. Now slowly adjust the frequency back down until the lock is re-established and record the frequency where the lock is made. This is the highest frequency at which the PLL can operate. This should be about 40.083 MHz. - Now the other way around - manually adjust the generator frequency down until lock is lost and then slowly adjust the frequency back up until the PLL re-locks. This is the lowest frequency at which the PLL can operate. This should be about 40.074 MHz. - With the HP Generator set at 40.0787 MHz adjust its output level down until lock is lost. Adjust the output level back up until lock is re-established and record this mVpp output level. It should be about 150 mVpp. - Switch to watching the output of the 320.64 MHz PLL. The scope display will now show 8 cycles on Ch #2 for each HP Generator Sync cycle on Ch #1. Repeat the hi re-lock and low re-lock frequency tests while watching the output of the 320.64 MHz PLL and record the results. The lock range of the 320.64 MHz is typically slightly less than that of the 40.08 MHz PLL. This can all be done with the HP Generator set for a 300 mVpp output. The point of all of these re-lock tests is just to verify that the PLLs on the card under test are operating normally. Check that all Clock Fanout Signals Are Running Normally: --------------------------------------------------------- With the clock system running normally at 40.0787 MHz with a 300 mVpp reference probe with the scope both sides of all 40.08 MHz and all 320.64 MHz fanout outputs and verify that all of these differential signals look normal. Note that there are 2 fanout chips for the 40.08 MHz clock. These are shown on Hub Circuit Drawing number 40B. There are 17 differential signals of the 40.08 MHz clock to check. The 320.64 MHz fanout is shown on Hub Circuit Drawing number 41. There are 9 copies of the 320.64 MHz differential clock to check. Measure the Frequency of the On Board Spare Oscillator: -------------------------------------------------------- Disconnect the single ended to differential transformer from the Hub pcb U562 pad locations and install the 40.0787 MHz Spare Oscillator. With a scope probe connected to the A input of the Fluke Counter measure and record the frequency of the Spare Oscillator. One can also verify that the output of the 40.0787 MHz PLL is locked to the output of the Spare Oscillator. Summary: -------- If all of the Hub Clock System tests look OK and if its power supplies have all been setup without a problem and are operating OK then it makes sense to go ahead and install the Hub FPGA Heat Sink with thermal bonding. Note that this heat sink covers many of the clock system and power supply components.