Dan's Hub Module Notes 1 --------------------------- Rev. 15-July-2019 ATCA Connectors: ---------------- An example of the Zone 1 connector for the front board is TE 1766500-1. These are about $25 to $28 each. In stock at DK. An example of the Zone 2 connector for the front board is I *think* TE 6469001-1 These are about $19 to $20 each. In stock at DK. This is called an "Advanced Differential Fabric Connector". The ATCA zone 1 and zone 2 connectors are manufactured by TE and ERNI and I assume by others. See the ADFplus Zone 2 connectors below. ATCA Guide Pin Alignment Pin Stuff: 29-Oct-2015 ----------------------------------- I think that the part that we need to use on a Front Board is TE Tyco part number 1-1469373-1 These are in stock at DK for about $4.25 each. I think that on a Front Board that the call the two guide pin receptacles K1 and K2. I think that keying code 1,1 is the required default. See page 2-79 and 2-83 of the specification. Yes the 1,1 code is the default and 1-1469373-1 is the correct part number. Recall that the Hub will have the normal K1 dual pin alignment/key receptacle for the backplane and it has a K2 dual pin alignment/key receptacle for the optical rear transition module. Shelf Slots for this Hub Module to Service: 9-Mar-2015 ------------------------------------------- I assume that we are using 19" rack that has an ATCA Shelf with 14 slots - i.e. we are not using special wide rack that can hold a 16 slot Shelf. Thus the Hub-Module Switch needs only 12 connections to FEX Node Boards and connections to the IPMC and to the Other Hub but not connection to the Shelf Manager. Note the potential difference between Physical Slots and Logical Slots. The Base Interface is always configured as a Dual-Star with the 2 Hub Boards assigned to Logical Slots 1 and 2. Verified at the bottom of page 6-30 that in backplanes with fewer than 16 slots that they Base Interface Channel Numbering, "uses the same routing assignments starting from Logical Slot 1 up to the number of Slots supported (in the backplane)". So in out 14 slots backplanes it is Base Interface Channels 15 and 16 that do not exist. - Base Interface Channel 1 is the Shelf Manager and our Hub is not providing an Ethernet Switch connection to the Shelf Manager. - Base Interface Channel 2 is the Other Hub. - Base Interface Channels 3:14 are the 12 FEX Node Slots which are Logical Slots 3:14 in the Shelf. Why the cross-over of the Base Interface signals in the ATCA Backplane, i.e Hub Signal Ties to Node Signal ------------ ----------- BI_DA on ab BI_DB on cd BI_DB on cd BI_DA on ab BI_DC on ef BI_DD on gh BI_DD on gh BI_DC on ef This is in the backplane. At the slot connectors: DA is always on ab, DB is always on cd, ... This is part of the general cross-over cable stuff with UTP type of Ethernet cables. The general 568B cross-over cable is the following: Goes to Signals Pin Color Pin Connected --- ------- ---- ----------- 1 Wht/Org 3 DA+ --> DB+ 2 Org 6 DA- --> DB- 3 Wht/Grn 1 DB+ --> DA+ --> 6 Grn 2 DB- --> DA- 4 Blu 7 DC+ --> DD+ 5 Wht/Blu 8 DC- --> DD- 7 Wht/Brn 4 DD+ --> DC+ 8 Brn 5 DD- --> DC- The only real need for any of this cross-over stuff is to support old 10/100 Base-T Ethernet Phys which has dedicated Transmit and Receive pairs which clearly must cross-over if you want to directly plug the same "type" of devices into each other. For the old 10/100 Base-T the setup was: Transmit on pins 1,2 Transmit on pins 3,6 -------------------- -------------------- PC NICs, end device Hubs Routers Switches Wireless Access Point The ATCA PICMG 3.0 is from March 2008, i.e. in the era of 10/100 Base-T and before a lot of the Auto MDI-X stuff so duh it has cross-over built into its backplane. Base Interface Switch: ---------------------- The current desire is to use an "un-managed", i.e. pure level 2 type of eithernet switch on the Hub module. This needs to be a 10/100/100BASE-T type of switch. This switch needs to provide connections to: Front Panel for the "up-link" 12 FEX slots This Hub's FPGA Other Hub's FPGA and either This and the Other Hub's ROD or This and the Other Hub's IPMC. No connection is needed to the Shelf Manager from the Hub Base Interface Switch. So this is an absolute minimum of 17 connections with the requirement that sometimes the Switch is connected to the 2 RODS and sometimes the Switch is connected to the 2 IPNCs. Note: Currently we are looking at a Broadcom BCM53128 switch chip. I *think* that one may be able to run this part as a 9 channel switch by tying a Phys chip to its RGMII port and flipping the bottom selector from 8051 to RGMII, but: I don't know this for certain and I don't think it helps, that is two separate 9 port switches gives us only 16 available ports when we tie them together. I don't think that there is a "10th port" to connect two of these switches. Thus I think we are stuck needing 3 of these parts. Currently we are looking at a Broadcom BCM53128 switch chip which is an update of the BCM53128. It has: - 8 of the 10/100/1000 BASE-T ports (with built in PHYs for these 8 ports) - a 9th Inband Management Port (IMP) that is a GMII/RMGII interface for connection to a management CPU - Serrial EEPROM connection - MDC/MDIO, SPI, and Interrupt connections The intent is to use 3 of the BCM53128 switch chips. 2 ports on the "hub BCM53128" are used to connect to the 2 "assistant BCM53128s". 1 port on each of the "assistant BCM53128" is used to connect to the "hub BCM53128". This leaves us with - 20 - ports for connection to objects in the shelf. The BCM53128 switch is a 65 nm 6 metal layer design. It has a 1.2V core with 3.3V I/O and typically consumes about 3.9 Watts. The BCM53128 supply voltages requirements: AVDDH Analog I/O power 3.3V AVDDL Analog core power 1.2V VDDC Digital core power 1.2V VDDO3 Power for GMII/RGMII/MII/RvMII 1.5V 2.5V 3.3V VDDO1 Power for GMII/RGMII/MII/RvMII 1.5V 2.5V 3.3V GPHY1_BAVDD Analog power for PHY 3.3V GPHY2_BAVDD Analog power for PHY 3.3V PLL_AVDD Analog power 1.2V GPHY1_PLLDVDD Analog power 1.2V GPHY2_PLLDVDD Analog power 1.2V There are specific sequence and ramp rate requirements for what they call, "successful power-up", briefly: I/O supplies 3.3V 2.5V must come up first. The maximum ramp up time for the 1.2V core is 2 msec. There are maximum 50 mV noise levels on all 10 supplies. In addition 3 of the supplies need LC filtering. The design guide gives clear specific requirements for bypass caps on all 10 of the supplies. 10/100/1000 BASE-T Magnetics and RJ45s: Rev. 18-Mar-2015 ---------------------------------------- - The magnetics for 1000Base-T is different from the 10/100 magnetics or atleast the connection to the magnetics is different for most Phys parts. This is the difference between modern voltage output parts i.e. 1000BT parts and older 10/100 BT Phys with current outputs. - Some of the RJ45s seem to be specially rated for gigabit ethernet but I do not know if they are really special or not. They do make "condo" RJ45s that are gigabit rated. That is important for front panel space. - The currently selected parts are: Pulse HX5201NL "Magnetics" te_conn_rj45_cat5e_1x2 1888653-X 1x2 Condo Connector The points about this HX5201NL magnetics are: Supports 10/100/1000 Base-T operation Supports MDIX Dual Port part Extended temperature range i.e. better ferrites Uses the most rational circuit, i.e. a 3 wire common mode choke on the Cable side with no auto-transformer This is a small BGA part, 127 sqmm per port the Quad BGA 5401 part, 123 sqmm per port the Dual SMD 5020 part, 160 sqmm per port Supports Power Over Ethernet which is not needed but indicates that the winding balance in the toroids must be OK. Advantages of 5201 over the originally selected 5020 are: only 79% of the board area, better circuit - Other parts that had been seriously considered and Geometries made for some of them. pulse_mag_1000bt_non_poe_hx5008fnl pulse_mag_1000bt_non_poe_hx5020fnl pulse_rj45_cat5e_1x1 E6588-WAOB44-L The 5008 is a classic common mode choke on the Cable side with an auto-transformer. The 5020 has a 2 wire common mode choke on the Cable side and does not have an auto-transformer - Front Panel RJ45 Count: The big question here is, are we permanently internally connecting together the 3 Switch chips, or are we patching together the 3 chips into 1 Switch using front panel RJ45s ?? Two Options Internally connect 3 chips into 1 Switch then Minimum RJ45s: 1 for Up-Link 1 for This Hub's ROD 1 for This Hub's IPMC 2 Switch Ports for connecting to RODs or IPMCs total of 3 "Condo" RJ45s with 1 spare. Externally connect 3 chips into 1 Switch then Minimum RJ45s: 1 for Up-Link 1 for This Hub's ROD 1 for This Hub's IPMC 2 Switch Ports for connecting to RODs or IPMCs 2 Switch Ports for connecting the "Root" Switch chip to the 2 "Branch" Switch chips. 1 Switch Port from each of the 2 "Branch" Swtich chips total of 5 "Condo" RJ45s with 1 spare. - Connections to the Magnetics: The ROD's FPGA and the Hub's FPGA will both use the Micrel ksz9031rnx Phys chip. This chip makes a standard "voltage mode" connection to its side of the magnetics. The BCM53128 Switch Chip makes a standard "voltage mode" connection to its side of the magnetics. The PCMI uses a National Semi now Texas DP83848C 10/100 Base-T Phys chip. This must have the old type of current mode transmitter connection to the magnetics. - Notes about the te_conn_rj45_cat5e_1x2 1888653-X 1x2 Condo Connector We probably want: 1888653-3 or 1888653-4 LEDs 1,4 are in the lower PCB level RJ45 LEDs 2,3 are in the upper RJ45 As installed on our Hub card: LEDs 1,2 are above their RJ45s LEDs 3,4 are below their RJ45s. TE Part No. LED_1 LED_2 LED_3 LED_4 ----------- ----- ----- ----- ----- 1888653-3 Yellow Yellow Green Green 1888653-4 Green Green Yellow Yellow This 1888653-X part is designed to allow Condo RJ45s to fit into the rather narrow ATCA front panel. This requires the connector to step down under the PCB which requires a cut out in the PCB. One would think that the connector data sheet would say how deep this cutout needs to be. All that they says is that: for ATCA the very front surface of the connector should be 1.85 mm in front of the front surface of the 1.00 mm thick front panel the very front surface of the connector to the middle of its back row of pins is 29.3 mm from the center of its back row of pins to the edge of the PCB should be 15.88 mm Then from ATCA, from the front edge of the PCB to the inner surface of the front panel is 2.54 mm. and the front panel is 1.00 mm thick. Put all of this together to get: The front edge of the PCB cutout is 13.42 mm back from the very front surface of the connector. 29.3 - 15.88 The normal not cutout PCB front edge is 5.39 mm back from the very front surface of the connector. 1.85 + 1.00 + 2.54 So the cutout is 8.03 mm deep. 13.42 - 5.39 For the geometry that I made for the 1888653-x it sould be placed at X = 18.58 mm. 10.55 + 8.03 In reality I can probably have these connetors stick out of the front panel more by 1.0 to 1.5 mm and have the cutout that much less deep. This would make them even with the SFP+ Cage installed in its stock X dimension. Xilinx Virtex-7 FPGA Component: ------------------------------- XC7VX550T 80 GTH Transceivers, 600 SE I/O, 86,600 Slices XC7VX690T 80 GTH Transceivers, 600 SE I/O, 108,300 Slices These specs are with both parts in the FFG1927 package, which is a 45mm x 45mm package which is a 44x44 pin array with three balls removed in each corner. This is again a 1mm pin pitch. The XC7VX550T in the FFG1927 has all "HP" type I/O Banks. This means that the maximum Vcco supply is 1.8 Volts. It's interesting that this part has 8 I/O Banks that are not bonded out: 10, 11, 12, 13, 30, 31, 32, 33. Recall the modern Xilinx speed grade system: the -1 devices are the standard and slowest parts, the -3 devices are the fastest parts. I assume that we are interested in the -1C i.e. standard speed commercial temperature range devices. Zone 2 Pin Out Organization: ---------------------------- Section 6 of the ATCA specification gives the details of the Data Transport signals in the Zone 2 connector. The Zone 2 Data Transport connectors, J20 at the top down through J24 by the Zone 1 connector, carry a total of 200 differential signals. Starting at the top with J20 and working down the Data Transport signals are arranged as: Top J20 Clock Signals 6 UpDate Channel 10 Fabric Interface Signals 120 Bottom J24 Base Interface Signals 64 The Base Interface is the Ethernet connection from a Hub Module to each of the Node Modules and to the other Hub Module. To keep the PCB Ethernet traces from needing to cross over the Fabric Interface traces it makes sense to put the Ethernet Switch IC down near the bottom of the Zone 2 connectors. FCI Meg-Array Connectors: ------------------------- 400 10x40 4mm stack height Plug 84740- Receptacle 74221- Suffix: on the Plug -002LF 15 u-inch Au Lead-Free -102LF 30 u-inch Au Lead-Free -202LF 50 u-inch Au Lead-Free Telcordia on the Receptacle -001LF 15 u-inch Au Lead-Free -101LF 30 u-inch Au Lead-Free -201LF 50 u-inch Au Lead-Free Telcordia The current official plan as of 14-Aug-2014 is to use the 400 pin part. From Ed on 26-Feb-2015: * The Hub uses a "Receptacle" (#74221) and the ROD uses a "Plug" (#84740) * In these pictures, you are always looking from the TOP (sometimes through the board) * The connector KEYS are correct (wide at top, narrow at bottom) * Pin A1 is indicated by the dot (in the North West corner). * If the HUB were in this picture, the front panel would be on the LEFT and the rear would be on the RIGHT The Meg-Array closer to the Hub's front panel is reference designator "S1" and the Meg-Array closer to the rear connectors is "S2". The 10 vertical columns are numbered: A,B,C,D,E,F,G,H,J,K T horizontal rows are numbered: 1 through 40 ATCA part of the Power Supplies: Rev. 30-Mar-2015 -------------------------------- Example of a combination 250 Watt Input Module and +12V Intermediate Supply is an Artesyn Embedded Technologies (aka Emerson) ATCR250-48D12-03J. This is in stock at DK for about $250 each. I believe that the general plan is: Input Module --> Isolated +12V Converter --> Individual Non-Isolated Step-Down Converters. At the required Hub Module power level we are probably looking at separate input module and isolated +12V module. Input Module Open-Frame Single Board SynQor IQ65033QMA10 quarter-brick 10 Amp 300 Watt drives PQ60120QEA25 SynQor IQ65033QGA12 quarter-brick 12 Amp 350 Watt drives PQ60120QZB33 Full Feature on the input module means that it has an I2C monitoring connection. Isolated 12V Output Converters Open-Frame Single Board SynQor PQ60120QEA25 quarter-brick 12V 25A Output 300 Watt Fully Reg SynQor SQ60120QPA28 quarter-brick 12V 28A Output 336 Watt Semi-Reg SynQor SQ60120QPB33 quarter-brick 12V 33A Output 396 Watt Semi-Reg PQ60120QZB33NNS-G For now start the design with: IQ65033QGA12 input module full No. IQ65033QGA12ENF-G SQ60120QPA28 isolated 12V full No. SQ60120QPA28NRS-G want nns-g SynQor Distributor: Arrow Electronics www.arrow.com SynQor IQ65033QGA12 Supplies a non-isolated 12 Amp load from redundent -48V inputs Quarter-Brick is: 2.30" x 1.45" Pin Diameters are: 40 mil with 80 mil shoulder Pin Lengths are: 0.145" standard, recommend pin length is 30 mils greater than the PCB thickness Pin Shoulder gives about a 36 mil minimum clearance between PCB surface and the bottom of the module. SynQor SQ60120QPA28 Can supply an isolated 12 Volt 28 Amp load. Quarter-Brick is: 2.30" x 1.45" Pin Diameters are: 40 mil with 80 mil shoulder 62 mil with 100 mil shoulder Pin Lengths are: 0.145" recommend pin length 30 mils greater than the PCB thickness Pin Shoulder gives about a 30 mil clearance between PCB surface and the bottom of the module. Flanged pins are designed to permit SMD soldering by the use of "flanged pin-in-paste" technique. 5 pins total UL/TUV requires a 40 mil clearance around "primary" areas of the module. We want tne "negative logic" version of the isolated converter, i.e. an active Low turns the converter ON. The Remote On/Off pin #2 is input return terminal Vin-. The 100 Ohm Pre-Charge Resistors need to be something like KOA P/N SG73 yes, a surge resistor but what case size, i.e. Watts ? 2010 case size 3/4 Watt The SynQor Input Module slang, "Hot-Swap Switch Open" means that the module power output is turned OFF. Check ATCA Requirement 4.96 on grounds. The Handle Switch ties up to the IPMC. The SynQor part numbers are: a 12 digit base parts number plus: a 3 digit list of options plus: a -G to indicate RoHS For the 10 Amp input module I think that the 3 option characters should be: S --> standard ATCA thresholds and protocols N --> standard 0.145" pin length F --> full features i.e. I2C bus interface IQ65033QMA10SNF-G For the 12 Amp input module I think that the 3 option characters should be: E --> ETSI thresholds and protocol (only option available) N --> standard 0.145" pin length F --> full features i.e. I2C bus interface For the +12V isolated 25 Amp converter PQ60120QEA25NNS-G A --> Open Frame (not threaded baseplate) N --> Negative Enable Logic (pulling On/Off pin to Vin- will turn the nodule ON) N --> standard 145 mil pin length S --> standard feature set (no other option available) -G --> RoHS compliant IPMC: Rev. 3-Nov-2015 ----- A socket for the IPMC is a Molex part number 877823003. This is the DDR3 VLP Mini-DIMM form factor. It is about 19 mm tall. The Atlas IPMC is from: LAPP IN2P3 CNRS Annecy-le-Vieux France. The SMD pads for the IPMC Socket are 0.35 mm x 1.75 mm long. The pitch of the SMD pads is 0.60 mm. The center of row to center of row spacing is 2x 1.38 mm. The IPMC from LAPP IN2P3 CNRS uses a National-Semi Texas DP83848C 10/100Base-T Phys part. IPMC Enable to the Isolated +12V Converter: Rev. 3-Nov-2015 ------------------------------------------- The Enable Signal to the Isolated +12V Converter comes from pin 225 of the IPMC mdoule. I assume that this signal goes voltage Hi to enable the +12V converter. This enable signal comes directly from one of the STM32F407 uProcessors on the IPMC. This Enable signal has a 4.7k Ohm pull down resistor on the IPMC. The characteristics of this Enable output signal from the IPMC are: Output Low Voltage 0.4 V max Output Hi Voltage 2.4 V min Vcc max Output Current +- 8 mA max See pages 21 and 22 of the IPMC manual. In SynQor speak we use negative logic On/Off controll, i.e. when the On/Off control pin on the SynQor converter is Low (wrt its V_In- pin) then the converter is ON. - On its On/Off control pin the SynQor converter includes a 10k Ohm pull up to +5V wrt its V_In- pin. - Any voltage > 4.0 Volts on the On/Off control pin will turn the supply Off. - And voltage < 1.0 Volt on the On/Off control pin will turn the Isolated +12V Converter On. - I do not see a apecification for the current input to the On/Off control pin on the SynQor converter. Their instruction seet does show it driven with: opto coupler, jumper, open collector descrete dransistor, TTL/CMOS gate all referenced to its V_In- pin. The Avago ACPL-217 - These come in many current transfer ratio bins. The price is not a strong function of the current transfer ration bins. Pick the middle of the road 130% to 260% bin as it will work fine in the Hub application. - These come with different Safety Approvals. The cost is not a strong function of the Safety Approval so pick the fancier IEC/EN/DIN/EN 60767-5-2 approval. - This comes down to part number ACPL-217-56BE. - The DK number for the ACPL-217-56BE part is: 516-2896-1-ND about $0.78 each and in stock. - The expected LED Forward Voltage at 20 mA is: 1.2 to 1.4 Volts. At 5 mA the forward Voltage is: 1.0 to 1.2 Volts over the full temperature range. - Assuming that the uProcessor driver gives you a full 3V3 Vcc output and that the LED forward drop is a minimum 1.0 V and that you want a maximum 8 mA draw on the driver, then the series resistor must be at least: 288 Ohms. - Assuming that the uProcessor driver gives you only a 2.4 Volt output and that the LED forward drop is 1.2 Volts and that you need at least 3 mA in the LED then the series resistor must not be more than: 400 Ohms - For now pick a 330 Ohm LED series resistor. This will give at least 3.6 mA and at most 7.0 mA of LED current. In Theory this Enable pin out of the IPMC should still give valid 3.3V CMOS logic levels. Zone 2 Advanced Differential Fabric plus Conn: Rev. 3-Mar-2015 ------------------------------------------------ The Erni high speed differential connector publication from Feb 2015 has information about trace stubs, anti-pads and general layout information. I'm still working to figure out exactly the difference between ADF and ADFplus connectors and the correct part number and series connectors for ADFplus from the 3.1 specification. One possibility is that the ADFplus is the plus type of TE Connectivity Z-PACK HM-Zd specifically Hm-Zd Plus catalog 1773095 or http://hmzd.te.com This connector type goes up to 12.5 Gb/s performance. OK, if we are going to use a "Z-PACK Hm-Zd Plus" connector then the TE Connectivity part that we probably want is: 2065657-1 The -1 is the correct plating. The PICMG specification about location of the ADFplus connectors on the PCB is not clear. I think it referes to the location of pin A1 and not to the location of the ground pin AG1. Receive verification from Ian/David about ADFplus location on the ATCA PCB 3-Mar-2015 Yes. A1 not AG1. Probably we should specify this on our drawings. J23 is 95.25 (this dimension is the same as the base specification, the offset into the board of A1 is what gives the change in the X dimension compared to base). From the TE Conn application data I think that pin AG1 should be about 1 mm back from the card edge. From this TE Conn application data there is also a hint that the HG row should be 18.0 mm from the card edge for the ADFplus connectors. The TE Conn application data defines the drill hole and pad layout in figure 4 on page 9. The specifications are: minimum board thinkness 1.40 mm minimum metal left in hole after back drill 1.40 mm maximum board thinkness 3.50 mm Pad Diameter Signal Pin 0.92 mm Pad Diameter Ground Pin 0.80 mm Drill Hole Diameter per plating 0.530 to 0.570 mm Thinkness of Cu plating on each wall 0.025 to 0.050 mm Thickness of the Surface Finish 0.0001 to 0.004 mm --> Nominal Finished Hole Diameter 0.460 mm Indicated tolerance on hole diameter 0.050 mm There appears to be a 0.45 mm shift between the centerline of the Connector Body and the centerline of its Leads. The controllable downward pressure to insert the connectors is to be 16 lbs per contact minimum. 16 lbs x 160 = 2560 lbs This is all from TE Conn application data 114-13059 Rev M FPGA Bypass Capacitors: ----------------------- Should get the XMP277 series 7 schematic review guide. From Xilinx the Required "PCB Capacitors" i.e. the minimum capacitors that we must put on the PCB: XC7VX550T XC7VX690T FFG1927 FFG1927 --------- --------- VCCINT 680 uFd 4 5 330 uFd 0 0 4.7 uFd 0 0 VCCBRAM 680 uFd 1 1 330 uFd 0 0 100 uFd 0 0 4.7 uFd 13 17 VCCAUX 47 uFd 1 1 4.7 uFd 0 0 VCCAUX_IO per Group 100 uFd 1 1 47 uFd 0 0 4.7 uFd 0 0 VCCO Bank 0 47 uFd 1 1 VCCO per Bank except Bank 0 100 uFd or 47 uFd 1 1 GTH per Group 3 groups on each side 6 groups total per FPGA GTH AVCC 4.7 uFd 1 1 GTH AVTT 4.7 uFd 1 1 GTH AVAUX 4.7 uFd 1 1 "Package" capacitors, i.e. capacitors that Xilinx includes within the the Virtex FFG1927 package itself. XC7VX550T XC7VX690T FFG1927 FFG1927 --------- --------- VCCINT 4.7 uFd 4 4 VCCAUX 4.7 uFd 2 2 VCCAUX_IO per Group 1.0 uFd 1 1 VCCO per Bank 1.0 uFd 1 1 GTH_AVCC one 100 nFd per Quad GTH_AVTT one 100 nFd per Quad GTH_AVAUX one 100 nFd per Quad XILINX Capacitor Specifications: max Range Value Body Type ESL ESR Volt Part Numb. ----- ---- ---- ---- -------- ---- ------------------ 680 uFd D Tant 2 nH 5 10.3125 GHz then 1.050 V GTH AVTT 1.20 V GTH AVAUX 1.80 V Power Trends Power Supply Modules: Rev. 17-Feb-2015 ---------------------------------- Look at the non-isolated DC/DC Converters that can work with a 12 Volt input and make output voltage and current in the range of interest for the Hub. From Web in Feb 2015: PTR08100W 4.5 to 14 In 0.6 to 5.5 Out at 10 A PTH08T240F 4.5 to 14 In 0.7 to 2.0 Out at 10 A PTH08T240W 4.5 to 14 In 0.7 to 5.5 Out at 10 A PTH08T241W 4.5 to 14 In 0.7 to 5.5 Out at 10 A Ceramic PTH08T220W 4.5 to 14 In 0.7 to 5.5 Out at 16 A PTH08T221W 4.5 to 14 In 0.7 to 5.5 Out at 16 A Ceramic PTH08T210W 5.5 to 14 In 0.7 to 3.6 Out at 30 A PTH08T255W 8.0 to 14 In 3.0 to 5.2 Out at 40 A PTH08T250W 4.5 to 14 In 0.7 to 3.6 Out at 50 A PTV08T250W 8.0 to 14 In 0.8 to 3.6 Out at 50 A PTV08040W 8.0 to 14 In 0.8 to 3.6 Out at 50 A PTH12040W 8.0 to 14 In 0.8 to 5.5 Out at 50 A From older data book: PTH12060 12 VOLT In 0.8 to 5.5V Out at 10 A PTH12010 12 VOLT In 0.8 to 5.5V Out at 12 A PTH12020 12 VOLT In 0.8 to 5.5V Out at 18 A PTH12030 12 VOLT In 0.8 to 5.5V Out at 26 A PTH12040 12 VOLT In 0.8 to 5.5V Out at 50 A PTH08T240W 4.5 Tto 14V In 0.7 to 5.5V Out at 10 A PTH08T241W 4.5 Tto 14V In 0.7 to 5.5V Out at 10 A Ceramic PTH08T220W 4.5 Tto 14V In 0.7 to 5.5V Out at 16 A PTH08T221W 4.5 Tto 14V In 0.7 to 5.5V Out at 16 A Ceramic PTH08T210W 4.5 Tto 14V In 0.7 to 3.6V Out at 30 A PTH08T250W 4.5 Tto 14V In 0.7 to 5.5V Out at 50 A PTH08T255W 4.5 Tto 14V In 0.7 to 5.5V Out at 50 A From DK and Data Sheets: PTH12020 is in stock at DK this data sheet is from May 2003 revised March 2009 revised again April 2013 PTH08T240W is in stock at DK data sheet is from Nov 2005 revised June 2009 revised Nov 2010 PTH08T220W is in stock at DK data sheet is from Nov 2005 revised June 2009 revised May 2011 PTH08T210 is in stock at DK data sheet is from Oct 2005 revised March 2009 revised May 2011 PTH08T250W is in stock at DK data sheet is from March 2009 revised Nov 2010 revised March 2011 PTH08T255W is not in stock at DK its data sheet is Nov 2008 Power Supplies on the Xilinx VC709 Evaluation Board: Rev. 17-Feb-2015 ---------------------------------------------------- My main interest in this area is to see how they handled the GTH supplies (note this demo board has the same number of GTH Quads as the Hub Module will have but this demo board appears to run only 2 of the GTH power groups) and to see what board level bypass capacitors they are using on all of the FPGA power buses. To be specific the VC709 board uses 8 GTH transceivers for the PCI Express connection, 10 GTH transceivers for the FMC connections, and 4 GTH transceivers for SFP/SFP+ connections. This is a total of 22 GTH Transceivers which come from a total of 6 Quads: 113, 114, 115, 117, 118, 119 and yes these are all in Power Groups 10 and 11, i.e. running only 2 out of the 6 Power Groups on the device. The GTH AVAUX supply is 10 Amps max. It comes from a PTD08D210W. They use a 5 mill Ohm shunt on the output and an INA333 with a 4.22 k Ohm resistor to measure the output current. I can not tell so far if there is "remote sense". After the shunt, as part of this power supply schematic, they have a 47 uFd 10 V X7R and a 330 uFd 10V Tant capacitor. The input to the module has a 180 uFd 16V Alum and a 1 uFd 25V X5R then a ferrite and then a 330 uFd 25V Alum and a 22 uFd 25V X5R. The PTD08D210W is running from a +12V input. The FPGA's 1V8 supply is just the other half of this PTD08D210W - the rest of the parts are the same. The VCCAUX supply is just another one of these 10 Amp modules. The GTH AVCC and AVTT supplies share another PTD08D210W and are thus 10 Amps max. The only difference is that they have included a zener diode on the output, a 1N5335BRLG, a 3.9 Volt zener. Page Content ---- --------------------------- 1 Disclamer 2 Block disagram with page references 3 Rocks: 200 MHz, 233.333 MHz, 156.250 MHz, SMA User Clock 4 114.285 MHz rock and SI5324C clock 5 JTAG DIGILENT_USB_JTAG, 80 MHz Clock, 74LV541 JTAG Buffer 74AVC1T45 and 74AVC2T245 JTAG Level Translators 6 USB UART CP2103GM_MLP_28 7 FPGA Bank "0" with lots of special pins and signals 8 FPGA Banks 39 and 37 DDR 9 FPGA Bank 38 DDR 10 DDR Socket A 11 DDR A Decoupling Caps and some FPGA I/O Bank Decoupling 12 FPGA Banks 31 and 33 DDR 13 FPGA Bank 32 DDR 14 DDR Socket B 15 DDR B Decoupling Caps and some FPGA I/O Bank Decoupling 16 FPGA Banks 36, 19 17 FPGA Banks 34, 35 FMC1 18 FMC Header Rows: A, B, C, D and NC7SZ66 TDI Switch 19 FMC Header Rows: E, F, G 20 FMC Header Rows: H, J, K 21 FMC Header Grounds 22 FPGA Banks 13 23 FPGA Banks 14 and 15 24 Byte Wide Flash Memory PC28F00AG18FE 25 Buttons, Switches, LEDs 26 LCD Level Shifters: 74AVC4T245, TXS0108E, 74AVC1T45 27 XADC Analog Dev ADP123 XADC VCC supply and REF3012 reference 1.25V 28 no content 29 PCA9548ARGER PCA9546A I2C Switches 30 FPGA Bank 17 - SFP Control and GTH bank 113 - SFP Data 31 SFP+ connector #1 and its cage 32 SFP+ connector #2 and its cage 33 SFP+ connector #3 and its cage 34 SFP+ connector #4 and its cage 35 PCIe 8x Card Edge Connctor 36 FPGA GTH Banks: 113, 114 37 FPGA GTH Banks: 117, 118, 119 38 FPGA GTH Banks: 111, 112, 116 39 FPGA GTH Power Pins: GTH: AVCC, AVTT, AVAUX groups G10 adn G11 40 FPGA Bank 12 and 16 41 FPGA Bank 18 42 FPGA Power Pins: VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO 6 banks 43 FPGA Grounds 44 FPGA ByPass Caps 45 Linear Power Supplies: 5V0 at 2 Amps, Power Good LED, TPS51200DRCT DDR Terminator Supply 46 Power Connector, PMBus Header and Level Shifter 47 Power Controler #1 UCD9248 VCCINT, VCCAUX, VCC_3V3 48 VCCINT 2x 40 Amps from 2x PTD08A020W VCCINT 49 VCCAUX and VCC_3V3 both 10 Amp from a PTD08D210W 50 no content 51 Power Controler #2 UCD9248 VCC_2V5, VCC_1V5, GTH AVCC, GTH AVTT 52 PTD08D210W power supply for VCC_2V5 and VCC_1V5 10 Amp max each 53 PTD08D210W power supply for GTH AVCC and GTH AVTT 10 Amp max each 54 Power Controler #3 UCD9248 VCCAUX_IO, GTH AVAUX, and VCC_1V8 55 PTD08D210W power supply for VCCAUX_IO other half not used 56 PTD08D210W power supply for GTH AVAUX and VCC_1V8 57 Mechanical Parts Board Level ByPass Caps Actually on the VC709 Demo Board: --------------------------------------------------------- VCCINT: 5x 680 uFd 6.3V Tant page 44 VCCBRAM: 1x 680 uFd 6.3V Tant page 44 17x 4.7 uFd 6.3V X5R page 44 Note that VCCBRAM is the VCCINT Bus ! VCCAUX: 1x 47 uFd 10V X5R page 44 VCCAUX_IO 6x 100 uFd 6.3V X5R page 44 VCCO 1x 330 uFd 10V Tant, page 15 for DRR Bank 1x 10 uFd 6.3V X5R, many 100 nFd 10V X5R GTH AVCC 1 per group 4.7 uFd 6.3V X5R page 39 GTH AVTT 1 per group 4.7 uFd 6.3V X5R page 39 GTH AVAUX 1 per group 4.7 uFd 6.3V X5R page 39 Power Supplies on the Xilinx VC7215 Evaluation Board: Rev. 18-Feb-2015 ----------------------------------------------------- Studying the VC709 above was interesting but limited because it only operates 22 of the 80 GTH transceivers and powers up only 2 of the 6 GTH Power Groups. The VC7215 operates all 80 GTH transceivers on a 7VX690T FFG1927 device. The current main reason for studying the VC7215 is to learn about the power supplies for the GTH and to learn about the bypass capacitors for all of the FPGA power buses. Page Content ---- --------------------------- 1 Disclamer 2 Block disagram with page references 3 JTAG Chain Block Diag: U32 Sys ACE, 3x FMCs, U1 FPGA Config Loop 4 USB/JTAG 74LVC125A JTAG Driver, TS5A3159A, U17 DIGILENT USB-JTAG 5 PMBus Level Translation: THS4281, PCA9517 6 Input Power Conn and Supervisor: U42 MAX16025 7 15x Power Status LEDs, U60 NC7SV125 8 Temperature Sensor Muxs: U3, U4 CD74HC4051 9 Power Controller #1 U9 UCD9248PFC: 2x VCCINT, VCCAUX, VCCBRAM 10 Power Controller #2 U10 UCD9248PFC: VCCAUX_IO, VCCO_HP 11 GTH Power Monitoring and Control U11 UCD9248PFC: 100 series GTH 12 GTH Power Monitoring and Control U18 UCD9248PFC: 200 series GTH 13 Remote Sense LP Filters: VCCINT, VCCAUX, VCCBRAM, VCCAUX_IO, VCCO_HP 14 Remote Sense LP Filters: 100 and 200 GTH: AVCC, AVTT, AVAUX 15 VCCINT Supply 2x 20 Amp, 2 phase, U5, U51 PTD08A020W, CS & 3.9V zener 16 VCCAUX & VCCBRAM Supplies, 10 Amp each, U6, U56, PTD08A010W, CS & zenr 17 VCCAUX_IO & VCCo_HP Supplies, 10 Amp each, U50, U57, PTD08A010W, CS 1Z 18 UTIL_5V0 & UTIL_3V3 Supplies U2 U13 PTH12060W and PTH12020W 10 & 18Amp 19 UTIL_2V5 supply U52 PTH12020W 18 Amp 20 GTH 100 series Current Sense and Ext Jacks 21 GTH 200 series Current Sense and Ext Jacks 22 GTH 100 series Power Module 23 GTH 100 series Power Module 24 GTH 200 series Power Module 25 GTH 200 series Power Module 26 Probe Power, i.e. 11x SMAs connected to the Power Buses 27 System ACE FPGA Banks 0 and 1 2V5 and 3V3 powered U32 28 System ACE FPGA Banks 2 and 3 2V5 and 3V3 powered U32 29 System ACE Config Power and Gnd, ByPass: UTIL_2V5, UTIL_3V3, VCC_1V2, VCCO_HP_EXT, ADP123 1V2 supply, U32 30 User IF, SD Card Conn, 50 MHz Clock 31 USB - UART Bridge U34 CP2103GM_MLP_28, U19 24LC32A EEPROM 32 Supper Clock Connector: J82, I2C Bus Mux U39 PCA9547 33 200 MHz Clock and diff SMA clock inputs 34 XADC Analog Dev ADP123 Power, REF3012AIDBZT Reference 35 INIT_B LED, DONE LED, PROG_B Button, I/O Header, User Swt and Btn 36 User LEDs 37 GTH Quad 110 and Samtec Connector 38 GTH Quad 111 and Samtec Connector 39 GTH Quad 112 and Samtec Connector 40 GTH Quad 113 and Samtec Connector 41 GTH Quad 114 and Samtec Connector 42 GTH Quad 115 and Samtec Connector 43 GTH Quad 116 and Samtec Connector 44 GTH Quad 117 and Samtec Connector 45 GTH Quad 118 and Samtec Connector 46 GTH Quad 119 and Samtec Connector 47 GTH Quad 210 and Samtec Connector 48 GTH Quad 211 and Samtec Connector 49 GTH Quad 212 and Samtec Connector 50 GTH Quad 213 and Samtec Connector 51 GTH Quad 214 and Samtec Connector 52 GTH Quad 215 and Samtec Connector 53 GTH Quad 216 and Samtec Connector 54 GTH Quad 217 and Samtec Connector 55 GTH Quad 218 and Samtec Connector 56 GTH Quad 219 and Samtec Connector 57 GTX AVCC Power and ByPass Capacitors NOTE Spies 58 GTX AVTT Power and ByPass Capacitors NOTE Spies 59 GTX AVAUX Power and ByPass Capacitors 60 BULLSEYE Test Channels J87 Loopback 61 FPGA "Bank" 0 and the associated special signals UTIL_2V5 powered 62 FPGA Banks 14 and 14 both VCCO_HP powered 63 FPGA Banks 16 and 17 both VCCO_HP powered 64 FPGA Banks 18 and 19 both VCCO_HP powered 65 FPGA Banks 34 and 34 both VCCO_HP powered 66 FPGA Banks 36 and 37 both VCCO_HP powered 67 FPGA Banks 38 and 39 both VCCO_HP powered 68 FPGA Power: VCCAUX, VCCAUX_IO, VCCBRAM 69 FPGA Power VCCINT NOTE the Spy 70 FPGA Grounds NOTE the Spies 71 FPGA Grounds 72 FPGA Grounds NOTE the Spies 73 FMC 1 JA2 rows A, B, C, D and NC7SZ66 JTAG Switch 74 FMC 1 JA2 rows E, F, G 75 FMC 1 JA2 rows H, J, K 76 FMC 1 JA2 Grounds 77 FMC 2 JA3 rows A, B, C, D and NC7SZ66 JTAG Switch 78 FMC 2 JA3 rows E, F, G 79 FMC 2 JA3 rows H, J, K 80 FMC 2 JA3 Grounds 81 FMC 3 JA4 rows A, B, C, D and NC7SZ66 JTAG Switch 82 FMC 3 JA4 rows E, F, G 83 FMC 3 JA4 rows H, J, K 84 FMC 3 JA4 Grounds 85 AFX Sideband Connector JA1 rows A:E 86 Select I/O Termination: 100 Ohm up to VTT, 100 Ohm down to Gnd 87 Select I/O Termination: 100 Ohm up to VTT, 100 Ohm down to Gnd 88 Select I/O VTT Termination Decoupling 89 Ext VTT Jacks, mounting holes, fiducials, Gnd Turrets 90 Bypass Capacitors: VCCINT, VCCAUX, VCCAUX_IO, VCCBRAM VCCO_HP, VCCO_0, VC7215 FPGA ByPass Capacitors: VCCINT: 5x 680 uFd 6.3V Tant page 90 VCCAUX: 1x 47 uFd 6.3V Tant page 90 VCCAUX_IO: 4x 100 uFd 6.3V X5R page 90 VCCBRAM: 1x 680 uFd 6.3V Tant page 90 its own bus 17x 4.7 uFd 10V ?? page 90 e.g. C885 VCCO_HP 12 Banks: 12x 100 uFd 6.3V X5R page 90 VCCO_0 Bank 0: 1x 47 uFd 6.3V Tant page 90 UTIL_2V5 GTX AVCC 1x per Power Group 4.7 uFd 10V ?? page 57 e.g. C965 GTX AVTT 1x per Power Group 4.7 uFd 10V ?? page 58 e.g. C975 GTX AVAUX 1x per Power Group 4.7 uFd 10V ?? page 59 e.g. C195 VC7215 Power Module Bulk Output Capacitors: VCCINT 47 uFd 10V ?? (e.g. C466) then 5 mOhm CS resistor then 330 uFd 10V Tant 47 uFd 10V ?? (e.g. C47) 3.9V Zener on 2x VCCAUX, VCCBRAM, VCCAUX_IO, VCCO_HP, dido but no Zener on VCCO_HP UTIL_5V0, UTIL_3V3, UTIL_2V5 dido but not CS resistors or Zeners GTH AVCC, AVTT, AVAUX where are the bulk caps ?? VC7215 Power Module Input Filters: VCCINT 180 uFd 16V Alum, 10 uFd 25V ?? (e.g. C35), 1 uFd 25V ?? (e.g. C81), the inductor, the 330 uFd 25V Alum, 22 uFd 25V ?? (e.g. C26) all 2x VCCAUX, VCCBRAM, VCCAUX_IO, VCCO_HP, dido UTIL_5V0, UTIL_3V3, UTIL_2V5 dido but the output section is 2x 330 uFd 25V Alum, 10 uFd 25V ?? (e.g. C30) VC7215 Non-FPGA ByPass Capacitors: VTT_HP: 21x 1 uFd 16V X5R page 88 UTIL_3V3: 1x 470 uFd 6.3V Tant page 29 2x 1 uFd 25V X5R 4x 100 nFd 25V X5R 7x 10 nFd 25V X5R UTIL_2V5: 1x 470 uFd 6.3V Tant page 29 1x 1 uFd 25V X5R 2x 10 nFd 25V X5R VCC_1V2: 1x 470 uFd 6.3V Tant page 29 1x 1 uFd 25V X5R 2x 100 nFd 25V X5R 3x 10 nFd 25V X5R VCCO_HP_EXT: 1x 470 uFd 6.3V Tant page 29 1x 1 uFd 25V X5R 2x 10 nFd 25V X5R VC7215 GTH Power Supplies: GTH power is made by two modules, i.e. the 100 and the 200 series power to match the Quad naming. Each of the two modules can make: AVCC 1.0V at 12 Amps, AVTT 1.2V at 8.0 Amps, and AVAUX 1.8V at 2.6 Amps. They again have 3.9V 320 mA zener on each of the supplies, e.g. D9. The modules have a SPI level control bus with PCA9517 translators. The mosules appear to be made by Intersil. These modules take +12V, +5V, and +3.3V power. The power input filters for the +5V and the +3.3V look the same, i.e. bulk power, 10 uF, 25V, 1 uF 25V, and 100 nFd 25V (type not shown, C154, C159, C135), the a 4.9 uH 6.5A or 4.3 uH 8.0A inductor, then 4x 100 uFd 6.3V (type not shown, C146, C147, C148, C149). The +12V filter is similar but its cap next to the module is a single 330 uFd 25V Alum, e.g. C188. So far I have not found any output filters. VC709 and VC7215 Demo Board Power Supply Summary: Rev. 19-Feb-2015 ------------------------------------------------- The VC709 uses an XC7VX690T-2FFG1761C FPGA. The VC7215 uses an XC7VX690T-3FFG1927E FPGA. So both of these cards are relivant to understanding the power requirements of the XC7VX550T FFG1927 on the Hub-Module. Bus VC709 VC7215 --------- --------- ---------- VCCINT combined 40 Amps VCCBRAM combined 10 VCCINT 80 Amps Separate +VCCBRAM VCCAUX 10 10 VCCAUX_IO 10 10 VCCO from Bulk 10 VCCADC ADP123 ADP123 VREFP REF3012 REF3012 GTH AVCC 10 24 5/PS_Grp 4/PS_Grp GTH AVTT 10 16 5/PS_Grp 2.7/PS_Grp GTH AVAUX 10 5.2 5/PS_Grp 0.9/PS_Grp Bulk_5V0 1.5 10 Bulk_3V3 10 18 Bulk_2V5 10 18 Bulk_1V8 10 -- Bulk_1V5 10 -- Bulk_1V2 -- ADP123 VTTDdR 0V75 3 -- Draft Hub PS Layout to Power Just the Virtex FPGA: Rev. 19-Feb-2015 --------------------------------------===========- For now I will assume that all converters will be one of the following 4 types: PTH08T240W 4.5 to 14 In 0.7 to 5.5 Out at 10 A PTH08T220W 4.5 to 14 In 0.7 to 5.5 Out at 16 A PTH08T210W 5.5 to 14 In 0.7 to 3.6 Out at 30 A PTH08T250W 4.5 to 14 In 0.7 to 3.6 Out at 50 A This is for Through Hole with probable sufix WAD but maybe WAH. FPGA Bus Hub Can Converter Bus Volts Supply Module --------- ------- --------- ------------ VCCINT 1.000 V 50 Amps PTH08T250W +VCCBRAM VCCAUX 1.800 from BULK_1V8 reserve 10 Amps VCCAUX_IO 1.800 from BULK_1V8 reserve 10 VCCO 1.800 from BULK_1V8 reserve 10 VCCADC 1.800 ? mA ADP123 VREFP 1.250 ? mA REF3012 GTH AVCC 1.000 30 PTH08T210W 5/PS_Grp GTH AVTT 1.200 16 PTH08T220W ** 2.7/PS_Grp GTH AVAUX 1.800 10 PTH08T240W 1.7/PS_Grp ** Note there may be a good reason to change this to a 30 Amp converter if there are no other buses that actually need a 16 Amp converter. Draft Hub PS Layout to Power Just the GTH FanOut: Rev. 19-Feb-2015 --------------------------------------==========- The Readout Data GTH Fanout will need to handle 6 GTH links from each of 12 slots and 2 GTH links from the Other Hub. This a total of 74 GTH Link Fanouts. The fanout chip that will be used is the NB7VQ14M. For now I will assume that the fanout chips will be powered from the BULK_2V5 bus. The power supply current for this chip with the inputs and outputs open is 170 mA typical and 210 mA maximum. I don't think that connecting the inputs will make a difference to current draw. Because the outputs are AC coupled I don't think that connecting them will make a difference. Thus the total expected current for the GTH fanout is: 12.6 Amps typ 15.5 Amps max. For now reserve 15.5 Amps from the BULK_2V5 supply for the GTH Fanout. Summary and Comparison of the PTH Converters: Rev. 19-Feb-2015 --------------------------------------------- For now I will assume that all converters will be one of the following 4 types: PTH08T240W 4.5 to 14 In 0.7 to 5.5 Out at 10 A PTH08T220W 4.5 to 14 In 0.7 to 5.5 Out at 16 A PTH08T210W 5.5 to 14 In 0.7 to 3.6 Out at 30 A PTH08T250W 4.5 to 14 In 0.7 to 3.6 Out at 50 A 10 Amp 16 Amp 30 Amp 50 Amp Parameter PTH08T240W PTH08T220W PTH08T210W PTH08T250W --------- ---------- ---------- ---------- ---------- Ripple 10 mVpp 15 mVpp 25 mVpp 10 mVpp 20 MHz Ripple 5 mVpp 15 mVpp 11 mVpp 6 mVpp 1/2 Current 1.8 Vout MTBF E+6 6.1 Hrs 6.1 Hrs 3.6 Hrs 2.8 Hrs Switch Frq. 300 kHz 300 kHz 480 kHz 2x 300 kHz 1 phase 1 phase looks 2 phase 2 phase C input: Minimum 220 uFd Alum 330 uFd Alum 470 uFd Alum 1000 uFd Alum 22 uFd Cer 22 uFd Cer 22 uFd Cer 22 uFd Cer Recomnd. 680 uFd 680 uFd 1000 uFd -- uFd RMS mA 700 mA 1500 mA 500 mA 600 mA ESR < 100 mOhm < 100 mOhm < 100 mOhm < 100 mOhm C outout: Minimum 220 uFd 220 uFd 470 uFd 680 uFd Maximum 5k-10k uFd 5k-10k uFd 12k uFd >10k uFd Designed 6x 330 uFd 6x 330 uFd 12x 330 uFd 15x 330 uFd min. uFd x mOhm 1,000 1,000 -- 1,000 max.uFd x mOhm 10,000 10,000 10,000 10,000 TT Res Ohm short short short short Total Bank ERS 7 mOhm 7 mOhm 3 to 5 mOhm 3 to 7 mOhm min. when non-TT Notes: The maximum capacitive load on the +12V isolated supply module is 12,000 uFd when it is fully loaded with a resistive load. When loaded partially ?? but proably less. When loaded with hacking DC/DC converter ?? but probably less. They are worried about using Tantalum caps on the input but so far I do not understand why. They want the Voltage rating of the input caps to be 2x DC + ripple - which is easy to do but none of the Tant caps * in their table * match this requirement. Recall with the good quality CMX capacitors are: Cap_4.7_uFd_0805 Ceramic Capacitor 4.7 uFd 16 Volt X7R Ceramic 0805 Size SMD Kemet Part No. C0805C475K4RACTU Cap_33_uFd_Tant_B Tantalum Capacitor 33 uFd 10 Volt 25 mOhm ESR "B" Case SMD Kemet Part No. T520B336M010ATE025 Cap_220_uFd_Tant_D Tantalum Capacitor 220 uFd 10 Volt 25 mOhm ESR "D" Case SMD Kemet Part No. T520D227M010ATE025 Cap in uFd x ESR in mOhm = 5,500 Cap_330_uFd_Tant_D Tantalum Capacitor 330 uFd 6.3 Volt 15 mOhm ESR "D" Case SMD Kemet Part No. T520D337M006ATE015 Cap in uFd x ESR in mOhm = 4,950 Cap_680_uFd_16V Aluminum Electrolytic Capacitor 680 uFd 16 Volt 80 mOhm ESR "G" Case SMD 637 mA ripple current max. Panisonic Part No. EEE-FK1C681GP Hub Module Power Supply Design Questions: Rev. 19-Feb-2015 ----------------------------------------- 1. Does anyone need +5V ? 2. Does anyone need +12V besides the DC/DC Converters ? 3. What voltages do MiniPOD, SFP, SFP+, Phys, Switch, and ?? take ? Ethernet Physical Interface to the Virtex FPGA: Rev. 23-Feb-2015 ----------------------------------------------- The Hub Module's Virtex FPGA needs 2 Physical, i.e. twisted pair cable level" Ethernet connections. One of these connections runs to the Ethernet Switch on This Hub. The other connection runs via the Base Interface to the Swtich on the Other Hub. Current choices for the "Phys" chip to implement the cable level Ethernet connections on the Hub are: 88E1111 Alaska from Marvell This is used on the Xilinx Demo Boards, on the FEX Demonstrator board and ? On the non-ethernet side it connects to Select I/O Banks on the Virtex FPGA (i.e. not to Transceivers). It appears to have at least 5 types of power pins but I think that they can be connected to just 3 supply buses. Still need to see if it can directly work with 1V8 I/O from the FPGA. I assume that we can get the full book for it. KSZ9031 from Micrel This will be used on the ROD The data for this part and its distribution seem to be available. The KSZ9031 has a RGMII connection to the MAC. This is a total of 12 signals, a clock each way, one control each way, and 4 data lines each way. The 5 types of power connections to the KSZ9031 are: AVDDL_PLL Analog Vdd PLL 1.200V AVDDH Analog Vdd 3.300V / 2.500V AVDDL Analog Vdd 1.200V DVDDH Digital Vdd 3.300V / 2.500V / 1.800V DVDDL Digital Vdd 1.200V DP83848 from National and now TI 10/100 Mb/s Ethernet only. Not of use to the Hub Module. Used on the IPMC mezzanine card. Count of the GTH Receivers and Transmitters: Rev. 20-Feb-2015 -------------------------------------------- The Hub Module's use of the GTH Transceivers: Receivers Function --------- --------------------- 72 6 Links Receive Readout Data from each of 12 FEX 2 2 Links Receive Readout Data from the Other Hub 1 Receiver the Clock signal from an SFP+ 2 Receiver ROD "Back Data" from the ROD on This Hub and from the the ROD on the Other Hub 3 Current Count of Spare GTH Receivers Transmitters Function ------------ --------------------- 2 2 Links Send Readout Data to the ROD on This Hub 2 2 Links Send Readout Data to the ROD on Other Hub 1 Send the combined TTC + ROD1 + ROD2 Data to the Fanout on This Hub for Distribution by the Fabric to 12 FEX and to the Ohter Hub 12 12 Links to a "Life Boat" MiniPOD Transmitter 63 In this version - Spare GTH Transmitter count 15 Alternate version - directly use a bunch of the GTH Transmitters to send out the "Combined Information" (aka TCC Infor + ROD 1 Back Data + ROD 2 Back Data) to the 15 consumers of this Combined Information: 12 FEX, Other Hub, ROD on this Hub, FPGA on This Hub. An issue with this is - how much high frequency noise will 15 GTH Transmitters, synchronously switching make and will this interfere with receiving the already weak screwed up FEX backplane readout data. 48 Alternate version - Spare GTH Transmitter count Possible Passives for the Hub Module: Rev. 14-Jul-2015 ------------------------------------- Electrolytic Caps: Polymer capacitors are types of electrolytic capacitor with conductive polymer (for example, PEDT) as solid electrolyte (cathode). These electrolytic capacitors with conductive polymer and polymerized organic semiconductor (for example, TCNQ complex salt), rather than the more usual liquid (wet) electrolyte, first became available in 1983. Names used for similar technologies are OS-CON (Sanyo trademark), aluminum organic polymer capacitors (AO-CAPS), organic conductive polymer aluminum electrolytic capacitor (OC-CON), functional polymer capacitors (FPCAP). I believe that there are both Aluminum and Tantalum Polymer capacitors. The Panisonic ZC parts are Aluminum Conductive Polymer. The Kemet T530X KO Caps are Tantalum Conductive Polymer. 470 uFd (or 330) at 25 V: FK & FP are 105 deg C ZC is 125 deg C Case mA mOhm Loss Solder Hrs Each ---- ---- ----- ---- ------ ---- ---- EEE-FK1E471AP G 850 0.080 0.14 6 2000 0.36 EEE-FP1E471AP G 1190 0.060 0.14 6 2000 0.39 EEH-ZC1E331P G 2000 0.020 0.14 6 4000 1.53 Solder Profile #6 says: Peak of 260 deg C with 5 sec > 250 deg C once or: Peak of 245 deg C with 10 sec > 240 deg C twice The ZC part is a Conductive Polymer type of aluminum electrolytic cap. 100 through 330 uFd at 100 V: FK is 105 deg C Case mA mOhm Loss Solder Hrs Each Length ---- ---- ----- ---- ------ ---- ---- ------ EEE-FK2A470AQ H13 500 0.320 0.07 11 5000 . 13.5mm EEE-FK2A680AQ H13 500 0.320 0.07 11 5000 . 13.5mm EEE-FK2A101AM J16 793 0.170 0.07 11 5000 . 16.5mm EEE-FK2A151AM J16 793 0.170 0.07 11 5000 . 16.5mm EEE-FK2A221AM K16 917 0.153 0.07 11 5000 . 16.5mm EEE-FK2A331AM K16 917 0.153 0.07 11 5000 1.56 16.5mm Solder Profile #11 says: Peak of 245 deg C with 5 sec > 240 deg C once Ceramic Caps: Kemet 25V 1210 X7R 22 uFd C1210C226M3RACTU 2.8 mm thick Kemet 25V 1210 X7R 10 uFd C1210C106K3RACTU 2.8 mm thick Kemet 25V 1210 X7R 4.7 uFd C1210C475K3RACTU 1.4 mm thick Kemet 10V 1210 X7R 22 uFd C1210C226K8RACTU 2.8 mm thick Kemet 10V 1210 X7R 10 uFd C1210C106K8RACTU 2.2 mm thick Kemet 10V 1210 X7R 4.7 uFd C1210C475K8RACTU 1.0 mm thick Kemet 10V 1206 X7R 22 uFd C1206C226M8RACTU 1.8 mm thick Kemet 25V 1206 X7R 10 uFd C1206C106K3RACTU 1.8 mm thick Kemet 25V 1206 X7R 4.7 uFd C1206C475K3RACTU 1.8 mm thick Kemet 10V 0805 X7R 10 uFd C0805C106K8RACTU 1.4 mm thick Kemet 16V 0805 X7R 4.7 uFd C0805C475K4RACTU 1.4 mm thick CMX Kemet 10V 0603 X7R 2.2 uFd C0603C225K8RACTU 0.90 mm thick Kemet 25V 0603 X7R 1.0 uFd C0603C105K3RACTU 0.87 mm thick Kemet 16V 0603 X7R 470 nFd C0603C474K4RACTU 0.87 mm thick Kemet 25V 0603 X7R 220 nFd C0603C224K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 100 nFd C0603C104K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 47 nFd C0603C473K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 10 nFd C0603C103J3RACTU 0.87 mm thick Kemet 25V 0603 X7R 4.7 nFd C0603C472K3RACTU 0.87 mm thick Kemet 16V 0402 X7R 100 nFd C0402C104K4RACTU 0.55 mm thick Kemet 25V 0402 X7R 47 nFd C0402C473K3RACTU 0.55 mm thick Kemet 25V 0402 X7R 10 nFd C0402C103K3RACTU 0.55 mm thick Kemet 25V 0402 X7R 4.7 nFd C0402C472K3RACTU 0.55 mm thick Kemet 6.3V 0201 X5R 100 nFd C0201C104K9PACTU 0.33 mm thick Kemet 16V 0201 X5R 10 nFd C0201C103K4PACTU 0.33 mm thick Cap_100_nFd_0603 Ceramic Capacitor 100 nFd 25 Volt 0.87 mm thick X7R Ceramic 0603 Size SMD Kemet Part No. C0603C104K3RACTU Cap_220_nFd_0603 Ceramic Capacitor 220 nFd 10 Volt 0.87 mm thick X7R Ceramic 0603 Size SMD Kemet Part No. C0603C224K8RACTU Murata 6.3V 1210 X7R 47 uFd GRM32ER70J476ME20L 2.7 mm thick Tantalum Capacitors: Recalls: "D" case = 2917 (7343 metric) T520 is Polymer Tantalum type called KO Cap Kemet Organic Ta anode, Ta2O5 dielectric, conductive organic polymer cathode --> Low ESR, -55 to 105 deg C, better High Frequency, ESR OK to about 1 MHz, Cap OK to about 500 kHz, no fires, Typical "D" case in 3.10mm thick. Typical "V" case is the same X,Y as "D" but 1.90mm thick. * Not Recommended for new designs For 2V < Vr < 10V max steady state WV is 90% of Vr for 12V < Vr < 25V max steady state WV is 80% of Vr T530 is the same "chemistry" but lower ESR, 125 deg C, higher capacitance, higher Rip Amps, but not > 16V For the +12V Bus: T520D156M025ATE060 15 uFd 25V 60 mOhm D case 1.9 Rip Amps T520D156M025ATE080 15 uFd 25V 80 mOhm D case 1.7 T520V156M025ATE090 * 15 uFd 25V 90 mOhm V case 1.4 T520V226M020ATE040 22 uFd 20V 40 mOhm V case 2.2 Rip Amps T520V226M020ATE045 22 uFd 20V 45 mOhm V case 2.0 16V caps give only 12.8V Working - not enough margin Resistors for various functions: Early PreCharge Resistors: 100 Ohm Surge rated stackpole RPC2512JT100R RPC2512JT100RCT-ND 1.5 W 2512 Semiconductors for various functions: TMP100NA/250 LTC29451UD#PBF AD7998 ADR361 INA198 LTC2974 LTC6909 LM82 Inductors - previous favorites: Wurth 7443340470 4.7 uH 7.5 Amp 12.4 mOhm 45 MHz Wurth 7443320470 4.7 uH 15.5 Amp 6.35 mOhm 43 MHz Panasonic ELL-6SH1R0M 1 uH 3.4 Amp 19 mOhm SMD LEDs and Light Pipes for the Front Panel: Single Height Mentor 1271.1000 3mm Light Pipe with Osram SMD LED: LST670, LYT670, LGT670, LST679, LYT679, LGT679, LST676, LOT676, LYT676, LTT673, LWT673, LSGT670 Dual Heigth Mentor 1270.1002 : 1270.1010 3mm Light Pipe same LEDs Passive Parts to Actually In Use (Draft): Rev. 20-Apr-2015 ------------------------------------------ Capacitors: At 100 Volts: FK is 105 deg C Case mA mOhm Loss Solder Hrs Length uFd ---- ---- ----- ---- ------ ---- ------ --- EEE-FK2A680AQ H13 500 0.320 0.07 11 5000 13.5mm 68 EEE-FK2A331AM K16 917 0.153 0.07 11 5000 16.5mm 330 Solder Profile #11 says: Peak of 245 deg C with 5 sec > 240 deg C once At 20 or 25 Volts: ZC is 125 deg C Case mA mOhm Loss Solder Hrs uFd Volts ---- ---- ----- ---- ------ ---- --- ----- EEH-ZC1E331P G 2000 0.020 0.14 6 4000 330 25V The ZC part is a Conductive Polymer type of aluminum electrolytic cap. Solder Profile #6 says: Peak of 260 deg C with 5 sec > 250 deg C once or: Peak of 245 deg C with 10 sec > 240 deg C twice T520V226M020ATE040 22 uFd 20V 40 mOhm V case 2.2 Rip Amps 1.9 mm thick T521V336M025ATE060 33 uFd 25V 60 mOhm V case 1.8 Rip Amps 1.9 mm thick T521V476M020ATE055 47 uFd 20V 55 mOhm V case 1.8 Rip Amps 1.9 mm thick Kemet 25V 1210 X7R 4.7 uFd C1210C475K3RACTU 1.4 mm thick At 3.3 Volts and Under: Kemet 10V 1206 X7R 22 uFd C1206C226M8RACTU 1.8 mm thick Kemet 10V 0805 X7R 10 uFd C0805C106K8RACTU 1.4 mm thick Kemet 16V 0805 X7R 4.7 uFd C0805C475K4RACTU 1.4 mm thick Kemet 10V 0603 X7R 2.2 uFd C0603C225K8RACTU 0.90 mm thick Kemet 25V 0603 X7R 1.0 uFd C0603C105K3RACTU 0.87 mm thick Kemet 16V 0603 X7R 470 nFd C0603C474K4RACTU 0.87 mm thick Kemet 25V 0603 X7R 220 nFd C0603C224K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 100 nFd C0603C104K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 47 nFd C0603C473K3RACTU 0.87 mm thick Kemet 25V 0603 X7R 10 nFd C0603C103J3RACTU 0.87 mm thick Kemet 25V 0603 X7R 4.7 nFd C0603C472K3RACTU 0.87 mm thick Kemet 16V 0402 X7R 100 nFd C0402C104K4RACTU 0.55 mm thick Kemet 25V 0402 X7R 47 nFd C0402C473K3RACTU 0.55 mm thick Kemet 25V 0402 X7R 10 nFd C0402C103K3RACTU 0.55 mm thick Kemet 25V 0402 X7R 4.7 nFd C0402C472K3RACTU 0.55 mm thick Kemet 6.3V 0201 X5R 100 nFd C0201C104K9PACTU 0.33 mm thick Kemet 16V 0201 X5R 10 nFd C0201C103K4PACTU 0.33 mm thick At 2.5 Volts and Under: Capacitors AC Coupling: 10 nFd 0402 Clock Circuits 47 nFd 0201 GTH Circuits Resistors: 20k 0603 Power Entry I2C Adrs 4.99k 0603 Power Entry Alarm Pull-Up 2.49k 0805 Power Entry Hold-Up Trim 100 Ohm 2010 Power Entry Early-Resistors 10Meg 0805 ESD Ground Isolation 49.9 Ohm 0603 Ethernet Line Ciscuit Not Installed 0805 Ground Isolation Power INDUCTORS for use on the Hub Module: Rev. 27-May-2015 ------------------------------------------ The intent of this section of notes is to arrive at a limited set of inductors that can be used for all power filter applications on the Hub Module. Power filter Inductors are used in a number of applications on the Hub Module. A list of these applications and a sketch of the requirements for each application are listed below. - Input to DCDC Converters: - Filters for the GTH_AVCC and GTH_AVTT supplies to the Virtex FPGA: - Filter for the GTH_AVAUX supply to the Virtex FPGA: - Filter for the 2V5 and 3V3 supply to the MiniPODs: The HP specification calls for 4.7 uH series inductor. Receiver: 2V5 350 mA to 525 mA, 3V3 48 mA to 90 mA Transmitter: 2V5 280 mA to 365 mA, 3V3 105 mA to 185 mA Supply Limits: 2V5 2.375 to 2.625 3V3 3.135 to 3.465 So at the most the 2V5 can have a 0.125V drop with 525 mA and that implies 24 mOhm max. and at the most the 3V3 can have a 0.165V drop with 185 mA and that implies 90 mOhm max. - Filter for the two 3V3 supplies to the SFP+: The HP specification calls for 4.7 uH and they call for less than 1.0 Ohm of DC resistance. The HP AFBR-709SMZ has only a 180 mA typ to 290 mA max current requirement. This part calls for a Vcc of 3.135 V min 3.465 V max. So I don't see how they can stand more than 0.5 Ohm of DC resistance. - Switch Chip higher current filter for AVDDL: For this higher current application the BCM kit uses BLM31PG601S inductors which have: 600 Ohms at 100 MHz, 1500 mA max current, 1206 size, 80 mOhm DC resistance. The total 1V2 current load is expected to be about 1.2 Amps - Switch Chip lower current filter for PLL_AVDD, GPHY1_PLLDVDD, GPHY2_PLLDVDD, GPHY1_BAVDD, GPHY2_BAVDD, XTAL_AVDD: For this lower current application the BCM kit uses BLM11A601S inductors which have: 600 Ohms at 100 MHz, 500 mA max current, 0603 size, 380 mOhm DC resistance. Note that the current part number is: BLM18A601S The total 3V3 current load is expected to be about 0.5 Amps. Final Decisions: For the 2V5 supply to the MiniPODs: Wurth 744311470 at 6.90mm x 6.90mm x 4.00mm tall 4.7 uH 6.0 Amp 19.5 mOhm 33 MHz --> estimate 4.95 pFd shunt For the higher current ferrite "bead", i.e. the 1 higher current filter on the Switch Chips, the 3V3 filter on the MiniPODs, and both filters on the SFP+: Wurth 742792116 60 mOhm 2.5 Amp 1206 height 1.30 mm about 9.5 Ohm at 1 MHz --> about 1.6 uH rated 500 Ohm at 100 MHz about 130 Ohm at 1 GHz above 100 MHz sharp drop in inductive reactance 100 MHz is the 80% point in inductive X 40-50 MHz inductive X is flat at its peak For the lower current ferrite "bead", i.e. the 5 low current filter on the Switch Chips: Wurth 782633601 200 mOhm 1 Amp 0603 about 20 Ohm at 1 MHz --> about 3.2 uH rated 600 Ohm at 100 MHz about 200 Ohm at 1 GHz above 150 MHz sharp drop in inductive reactance ---------------------- Other Filter Inductor Parts: Wurth 742792121 60 mOhm 3 Amp 1206 height 1.30 mm about 10 Ohm at 1 MHz rated 300 Ohm at 100 MHz about 80 Ohm at 1 GHz above 100 MHz sharp drop in inductive reactance 100 MHz is the 80% point in inductive X 40-50 MHz inductive X is flat at its peak Wurth 742792116 60 mOhm 2.5 Amp 1206 height 1.30 mm about 9.5 Ohm at 1 MHz rated 500 Ohm at 100 MHz about 130 Ohm at 1 GHz above 100 MHz sharp drop in inductive reactance 100 MHz is the 80% point in inductive X 40-50 MHz inductive X is flat at its peak Wurth 742792118 70 mOhm 2.5 Amp 1206 height 1.30 mm about 22 Ohm at 1 MHz rated 600 Ohm at 100 MHz about 80 Ohm at 1 GHz above 60 MHz sharp drop in inductive reactance Wurth 742792037 80 mOhm 2.0 Amp 0805 height 1.10 mm about 5.5 Ohm at 1 MHz rated 330 Ohm at 100 MHz about 180 Ohm at 1 GHz above 140 MHz sharp drop in inductive reactance Wurth 742792031 50 mOhm 3.0 Amp 0805 height 1.10 mm about 8.5 Ohm at 1 MHz rated 300 Ohm at 100 MHz about 100 Ohm at 1 GHz above 100 MHz sharp drop in inductive reactance Wurth 742792514 40 mOhm 3.0 Amp 1812 height 1.70 mm about 6.5 Ohm at 1 MHz rated 600 Ohm at 100 MHz about 70 Ohm at 1 GHz above 65 MHz sharp drop in inductive reactance Wurth 74279224401 20 mOhm 4.5 Amp 2220 height 3.45 mm about 9.0 Ohm at 1 MHz rated 400 Ohm at 100 MHz about 90 Ohm at 1 GHz above 80 MHz sharp drop in inductive reactance 10 Ohms at 1 MHz (where the copper resistance is not significant compared to 10 Ohms) implies about 1.6 uH of inductance. 30 Ohms at 1 MHz is about 4.7 uH. the old standby 7443340470 at 8.40mm x 7.90mm x 7.50mm tall 4.7 uH 7.5 Amp 12.4 mOhm 45 MHz --> estimate 2.66 pFd shunt or 74279224401 at 5.59mm x 5.08mm x 3.45mm tall 20 mOhm 4.5 Amp 2220 height 3.45 mm about 9.0 Ohm at 1 MHz rated 400 Ohm at 100 MHz about 90 Ohm at 1 GHz above 80 MHz sharp drop in inductive reactance In 0805 Kemet has: 220 Ohm at 100 MHz 50 mOhm 2 Amp z0805c221apmst 600 Ohm at 100 Mhz 250 mOhm 500 mA z0805c601bsmst 600 Ohm at 100 Mhz 300 mOhm 500 mA z0805c601asmst In 0603 Kemet has: 470 Ohm at 100 MHz 150 mOhm 700 mA Z0603C471BPWZT Wurth 742792645 200 mOhm 1 Amp 0603 about 15 Ohm at 1 MHz rated 470 Ohm at 100 MHz about 200 Ohm at 1 GHz above 200 MHz sharp drop in inductive reactance Wurth 742792040 150 mOhm 2 Amp 0805 about 9 Ohm at 1 MHz rated 600 Ohm at 100 MHz about 200 Ohm at 1 GHz above 125 MHz sharp drop in inductive reactance Inductors - previous favorites: Wurth 7443340470 4.7 uH 7.5 Amp 12.4 mOhm 45 MHz Wurth 7443320470 4.7 uH 15.5 Amp 6.35 mOhm 43 MHz Panasonic ELL-6SH1R0M 1 uH 3.4 Amp 19 mOhm ATCA Power Entry and Isolated +12V Components: Rev. 3-Apr-2015 ---------------------------------------------- The focus of this section is the final decisions of the components to use in the ATCA Power Entry and Isolated +12V sections of the Hub Module design: Power Entry Module: IQ65033QMA10SNF-G Isolated +12V Module: PQ60120QEA25NNS-G PreCharge Resistors: 100 Ohm 2512 1.5W Stackpole RPC2512JT100R Hold-Up Capacitors: 2x 330 uFd 100V K16 EEE-FK2A331AM Hold-Up Trim Resistor: 2.49k 0805 1% Iso 12V Input Caps: 2x 68 uFd 100V H13 EEE-FK2A680AQ Iso 12V Output Caps: 4x 4.7 uFd 25V 1210 X7R C1210C475K3RACTU 2x 22 uFd 20V V case Tant T520V226M020ATE040 2x 330 uFd 25V G10 EEH-ZC1E331P Iso 12V Alarm PU Res: 4.9k 0603 1% Iso 12V ADRS Resistor: ???k 0805 1% ATCA Handle Switch for the Hub Module: Rev. 3-Apr-2015 --------------------------------------- The ATCA specification defines a Handle Switch that is used during the ATCA Hot Swap process. A problem is that this specification defines about 3 versions of handle switches and a number of different mechanical handle types and much of this is not interchangable. See PICMG 3.0 appendix D for more details. There is also the problem of the sense of the switch, i.e. are the contact open or closed when the card is fully inserted and operating normally. The type of handles that we are tentatively using on the Hub are called Southco "plunger" switch type handles. Note the component keep out zone on page D2 pdf page 638. The Southco type handle and switch information starts on page D12 pdf page 648. The typical switch for this type of setup is: ITT/Cannon MDS002 Lever style ITT/Cannon SDS002 Plunger style The compatable switch that is actually out in distribution is the SDS002R from C&K. It's and SMD switch and half way looks like a piece of junk but the C&K data sheet does mention that it was made for ATCA. The SDS002R is SPST Normal Closed. That is with nothing pressing on its plunger the switch is closed. So in moving the handles to extract the card - the switch will close. Closed means that an extraction is taking place. Note that this switch goes on the backside of the board. Recall that the thickness of the ATCA Front Panel should be in the range 0.8 to 2.5 mm and they are all cranked up about sheet metal front panels. So far I have obtained SouthCo style front panel handles that are setup fro plunger style front panel switches. The boss on the handle pushes the switch plunger down to cause the switch to go into its installed state. That is the switch plunger is vertical and must face up to be actuated by the bottom handle. The location of the active surface on the boss that pushes on the plunger when the handle is all the way closes is: up 23.02 mm wrt the center of the SW board hole and inboard 1.93mm wrt the center of the SW board hole. Recall that wrt the SW corner of the board that this holes is at X = 3.57 mm Y = 5.55 mm. The the actuating surface on the handle boss when the handle is fully closed is at: X = 5.50 mm Y = 28.57 mm The LAPP IPMC document says that the signal going to their IPMC should be logical "0" when the board is in working condition. They say that on the IPMC mezzanine itself there is a 4.7k 100 nFd low pass filter, I assume 4.7k series then 100 nFd to Gnd at the actual input to their uProc. This is on page 24 of the v1.6 document. LAPP IPMC document shows the switch going up to 3V3 and a 10k pull down. They call this signal HANDLE_SWITCH_N. Carrier pulls to ground with a 1K and pulls to ground with a series 360 Ohm 100 nFd. Their switch runs up to 3V3. FTM seems to pull up to 3V3 with 1k and run the switch to ground. So the Normally Closed C&K SDS002R will work in this application with the suggested circuit topology, i.e. the Switch runs to the IPMC 3V3 supply and a pull-down resistor to Ground. Hub will use a 1k pull down and a small bypass cap that does not require a snubber resistor to protect the switch contacts. When Hub card is fully installed in the crate and the handle fully closed then the switch plunger will be pushed in, the switch will open, and the pull-down resistor will send a logical "0" into the IPMC mezzanine. SFP+ aka Enhanced Small Form-Factor Pluggable: Rev. 24-Feb-2015 ----------------------------------------------- The current version of the SPF+ specification is Ver. 4.1 from 6-July-2009. Must consider whether to use "linear" or "limiting" SPF+ transceivers. I assume that we want Multi-Mode 850 nm transceivers. Is the cage the same as plan SFP ? Is the connector the same a plan SFP ? We have an example of SFP+ to study in the flaky line card that I promised not to damage and lied. ATCA Board Pitch, Dimensions, Thickness and Rev. 24-Feb-2015 Component Height Limit: -------------------------------------------- Recall that ATCA calls the "Component and Solder" sides of the board "Component Side 1" and "Component Side 2". The pitch is 6 HP 1.200" 30.48 mm. The surface of Component Side 1 of the PCB is 6.61 mm from the pitch line to the left and there is 23.87 mm from this surface to the pitch line to the right.. There is always a Cover on the "solder" sode i.e. a cover on Component Side 2. When component Side 1 covers are not used then the maximum component height on Side 1 is 21.33 mm. This leaves 2.54 mm from the top of the tallest allowed Side 1 component to the pitch line. 2.54mm is the minimum specified clearance. The maximum component height on Side 2 components depends on the thickness of the PCB and on the thickness of the Side 2 Cover and on how much space one leaves for board warpage and clearance. Probably rational numbers for all of this: 6.61 mm from Side 1 surface to the Pitch Line assume 2.54 mm thick PCB (CMX was 3.43 mm thick). assume 0.80 mm thick Side 2 Cover assume 2.00 mm for warpage and clearance This allows 1.27 mm tall Side 2 components Maximum. Recall the the 0805 4.7 uFd caps on CMX are 1.40 mm tall. The ATCA mechanics that I purchased last fall allows a total of 3.2 mm from the Side 2 surface to the inner Cover surface i.e. the cover surface next to Side 2. This basically matches the above example. --> ATCA screws you on Side 2 maximum component height. Recall that ATCA board thickness is designed to be in the range 1.6 to 2.4 mm with an absolute limit of 1.4 to 2.6 mm. If your card is thicker or thiner then that you may remove or add material in the Keepout zone along the top and bottom edges of the card. ATCA has 2.54 mm from the front edge of the PCB to the inner surface of the Front Panel. ATCA uses fance multi-element EDS strips. Will the Hub Module need Stiffening Bars ?? Level Translators: Rev. 25-Feb-2015 ------------------ This is just a note to keep in mind the fact that the Hub Module will need level translators and it may need a lot of them. Recall that the Hub's Virtex-7 part can only do 1V8 and less Select IO. Will Hub need just moderate speed level translators or is it going to require very fast ones for something like RGMII ?? For reference the CMX used: IC_74AVCAH164245 Bi-Directional 16 Bit Bus Translator 23 TSSOP 48 pin SMD TI Part No. SN74AVCAH164245GR IC_TXB_0108_PW Level Translator 8 bit 1 TSSOP 20 pin SMD TI Part No. TXB0108PWR Hub Module PCB Stack-Up: Rev. 25-Feb-2015 ------------------------ So far there is no detailed understanding of the required stack-up for the Hub Module - but there are some observations: High Speed Differential trace pairs will probably need to run both near the Comp side and near the Solder side of the PCB. Thus we will need 50 Ohm layers in many places. HS Diff pairs near the Top for things like the: Virtex, SFP+, Meg-Array, and some of the readout fanout chips on the top. HS Diff pairs near the Bottom for things like the: ADFplus connectors (I know of no other way to handle the traces to these connectors and this means 4 or 5 HS Diff pair layers at the Bottom of the card), readout fanout chips on the bottom. Power Supply distribution: this is not at all understood yet, fills will obviously be required, there are many buses, some are very high current, can all of the converters be located far away and use remote sense ?? Hub Module PCB Custom Design Tools: Rev. 25-Feb-2015 ----------------------------------- Need to have a frank review of how CMX design went and where / how to improve things. On Hub the main issue will not be the 400 precious 6 nsec single-ended signals and managing their connections to the FPGA. On Hub the hard issue will be handling the 10**9 high speed differential pairs. - script to swap Direct and Complement on the pair of connections that has net_name bla_dir bla_cmp, i.e. swap bla_. "simple" because everything is point to point and we do not care about polarity. - script to swap the "device" at the Receiving end between net_names bla_dir bla_cmp and foo_dir foo_cmp i.e. swap the receiving device between bla_ with foo_. "simple" because all GTH are more or less equivalent (leave it to the user to worry about what Quad has which clocks) and all FanOuts are equivalent. On the Hub there will only be a few Select IO connections and they can be probably managed by hand. For the Comp layout it would be nice to be able to move a "Relatively Positioned Set of Components" by some displacement delta_X delta_Y - script MRPCS (Move Relatively Positioned Comp Set) > MRPCS X Y Comp_FileName It adjusts all comp X,Y values in the file Comp_FileName by delta_X delta_Y and then writes a new version of this file with this new X,Y values. Review the Xilinx VC709 before shipping to CERN: Rev. 2-Mar-2015 ------------------------------------------------ The Xilinx VC709 board appears to be made by Zippsystems.com They use Avago AFBR-709SMZ SFP+ optical Transceiver modules. These are: 10 Gb/s, LC connectors, 3.3V supply, 850 nm, Ethernet, about 600 mW, 10GBASE-SW 10GBASE-SR compliant, in stock at DK, about $94 each Review the RJ45 Connector Pinout: Rev. 6-Jan-2016 --------------------------------- This section is being brought up to date and has the final information about the wiring of the AMP 1888653-4 condo front panel ATCA Ethernet connectors. Looking into an RJ45 (8P8C) female connector on a panel, with the locking tab down, then pin #1 is on the left and pin #8 is on the right. The geometry for the AMP 1888653-4 condo connectors has been setup correctly to match this and has upper and lower section pins numbered in opposite direction to make up for the different tab directions in the two sections. Looking at the end of an RJ45 cable with the locking tap up and the contacts facing down, then pin #1 is on the left and pin #8 is on the right. Based on the first point in this section it appears that the pins on the TE Conn 1x2 connector are numbered correctly in the AMP data sheet, i.e. what the data sheet for this connector calls pin #1 is pin #1 in the RJ45 "system", i.e. the Direct side of the first pair. The very not intuitive part is how the 4 twisted pairs in the cable are attached to these rationally numbered pins. There are 2 schemes but in both cases: pins 1 & 2 are a pair, pins 3 & 6 are a pair, pins 4 & 5 are a pair, pins 7 & 8 are a pair Why the 3-6 4-5 setup / confusion / asymmetry ?? Now for the 2 wiring schemes: T568A T568B --------------- --------------- pin Signal Color Signal Color --- ------ ------- ------ ------- 1 DA+ Wht/Grn DA+ Wht/Org 2 DA- Grn DA- Org 3 DB+ Wht/Org DB+ Wht/Grn --> 6 DB- Org DB- Grn 4 DC+ Blue DC+ Blue 5 DC- Wht/Blu DC- Wht/Blu 7 DD+ Whr/Brn DD+ Whr/Brn 8 DD- Brn DD- Brn Note the pin number order in the above tabe. All of the normal Ethernet RJ45 Patch Cables are wired one to one, aka straight through, aka what is on pin X at one end of the cable is on pin X at the other end of the cable. The signal names are their 1000Base-T names and they are the same in both "coloring" schemes. In the cable itself the pairs are always: White with Color X strip is twisted with Color X. The fancy Cat 6 patch cord that I took apart to study uses the T586B coloring scheme. In this cable the Grn pair and the Blue pair are twisted tighter than the Orange pair and Brown pairs. The 4 pairs are in quadrants in the jacket. Grn-Blu are across from each other and Brn-Org are across from each other. Are the jacks on Switches wired differently from the jacks on Devices ? That is with the cables being straight through where is the "cross-over" done ? Is there a cross-over ? Wouldn't you need one for old 10/100 with defined transmit and receive pairs ? KSZ9031RNX connection to its RJ45 (assumed to be "Device") DA+ to pin 1 DA- to pin 2 DB+ to pin 3 DB- to pin 6 DC+ to pin 4 DC- to pin 5 DD+ to pin 7 DD- to pin 8 This was verified on page 5 of the Micrel KSZ9031RNX demo board schematic. Note that they run their magnets "backwards" on this demo board. Section #4 is used for signal "A" ... section #1 for signal "D". On their demo board they also flip the Dir amd Cmp connections on both the input to and output from the magnetics. BMC53128 connection to its RJ45 (assumed to be "Switch") DA+ to pin 1 DA- to pin 2 DB+ to pin 3 DB- to pin 6 DC+ to pin 4 DC- to pin 5 DD+ to pin 7 DD- to pin 8 For the ATCA Backplane connections things are nicely spelled out: DA+ to pin A DA- to pin B DB+ to pin C DB- to pin D DC+ to pin E DC- to pin F DD+ to pin G DD- to pin H ATCA GROUNDS: Rev. 1-Apr-2015 ---------------- ATCA defines a number of "GROUNDS" - lets get them fully understood and use them correctly. Start on page 4-25 Shelf Ground: Front Panel connects directly to the card's Shelf Ground. Front board I/O connections requiring a return path to the Shelf Ground are connected to the Front Panel alignment and safety ground pin. Shelf Ground is pin #25 in the Zone 1 connector which is first to mate. The A1, K1, A2, K2 alignment blocks on the front board should either float or be tied to the Shelf Ground. The Shelf Ground makes a connection to a pin on the Power Input Module. I think this is for the power input filters inside the power entry module. The Shelf Ground is used with the first and third sections of the ESD Strip. Logic Ground: Front boards must isolate Logic Ground and Shelf Ground to a minimum of 9 Meg Ohm. Front boards are to have a mechanism to allow a low impedance connection between Logic Ground and Shelf Ground. This mechanism should be near the front panel. Logic Ground is on the Zone 1 connector pin #26. This is also a first to mate pin in the Zone 1 connector. Logic Ground is the ground planes in the PCB and thus the ground on all Zone 2 connectors. REQ 4.96 page 4.26 Each front board should provide a configurable mechanism to make a low impedance connection bethween Logic Ground and Shelf Ground in the vicinity of the front panel. 48 Volt Return: Must be isolated from the Shelf Ground and isolated from the Logic Ground. At some point in the overall system, the 48 Volt Return is tied to the Shelf Ground. In some systems this may be at one point in the battery plant or in other systems it may be a mesh of connections with one in each rack or in each shelf. EDS Ground Strip: The front board must have a EDS Strip structure along the bottom edge of side 1 of the PCB. The PCB must not have an EDS Strip along the top edge. The EDS Clip on the Shelf's card guide is tied to the shelf's Shelf Ground. The first part of the ESD Strip to make contact during insertion is tied through 10 Meg Ohms to Shelf Ground The middle section of the ESD Strip is tied through 10 Meg Ohms to the Logic Ground. The final section of the ESD Strip to make contact during insertion is tied directly to the Shelf Ground. LEMO ROD Busy Output from the Hub Module: 12-Mar-2015 ----------------------------------------- My understanding is that this single LEMO connector is an output from the ROD on the Hub Module. This LEMO signal indicates that the ROD is Busy. The pointer that Ian give me about the electrical specification of this LEMO output signal are in the CERN EDS system: https://edms.cern.ch/edmsui/#!master/navigator/ document?I:1045051810:1473507311:subDocs This is EDS location contains the specifications and schematic of something called the ROD MkII Busy Module. I assume that the Hub is sending its Lemo output to an input on this MkII Busy Module. If so that module works as follows: - Each input has a 300 Ohm resistor up to a Vcc of +5 Volts and a 62 Ohm resistor to Ground. This makes a Thevenin of 51 Ohm with a bias of +856 mV. This goes into one input of a comparator. The other input of the comparator is tied to a reference of +395 mV. Their "reference" circuit is naive. It depends 100% on the value of the VME +12V bus and it most likely tries as hard as it can to oscillate. 15k Ohm to VME +12V bus and 510 Ohm to ground with a 741 voltage follower OpAmp the output of which has 8x 47 nFd caps to ground. - Pulling this 50 Ohm input based at +856 mV down to ground required pulling 17 mA to ground. - A test register, which can in parallel drive these inputs to the Busy Module uses 74F756 open collector drivers. The 74F756 is guaranteed to pull 64 mA down to 0.55V and at 25 Deg C can typically pull it down to 0.42V. At 25 deg C it can typically pull 48 mA down to 0.38V. - An output from this Busy Module, which can be daisy chained to the input of another Busy Module, uses a 74F07 open collector driver. The 74F07 is guaranteed to pull 64 mA down to 0.50 volts and at 25 deg C and Vcc=5.0V typically pulls it down to 0.30V. - This whole setup (i.e. 0.7V or 0.8V across a 50 Ohm terminator) is kind of like a positive NIM signal but it lacks NIM's current mode driver, i.e. the thing that makes NIM a nice system. List of the Existing Python Mentor Programs: Rev. 14-Mar-2015 -------------------------------------------- The following is a list of python programs that Philippe has written for use with the Mentor system. migt.py migt_f.py netlistsort.py spin.py aaa_convert_mm_to_deca_nm.py match_res2pin.py match_res2pin_v0.3_cmx_0.py match_res2pin_v0.4_cmx_0.py match_res2pin_v1.0.py match_res2pin_v2.0.py match_res2pin_v2.1.py match_res2pin_v3.0.py match_res2pin_v3.1.py reorder_traces.py ATCA Required Front Panel LEDs: Rev. 26-Mar-2015 ------------------------------- The ATCA required front panel LEDs are described starting in section 2.2.8 of the PICMG 3.0 specification. There are: 2 mandatory LEDs, two optional LEDs. Y with Y with 0 0 @ Hole @ Corner -------- ----------- Mandatory LED_1 251.84 257.39 mm Optional LED_2 239.84 245.39 mm Optional LED_3 227.84 233.39 mm reserved for specific LEDs 217.84 223.39 mm reserved for specific LEDs 69.31 74.86 mm Mandatory Blue 59.30 64.85 mm Recall that the Y offset from the "D" Datum Hole to the board's SW corner is 5.55 mm. ATCA wants these indicators on Side 2 of the PCB, but then they say that the "horizontal position of LEDs are design dependent". They also talk about "make typical opening for 5 x 2 LED". The mandatory Blue LED indicates whether or not the front board can be safely extracted. The legend for the Blue LED is "H/S" or "Hot Swap" The mandatory LED_1 can be Red or Amber. What LED_1 means kind of depends on whether this is a North American board or a European boards. The legend for LED_1 is required to be "OOS" or "Out of Service". North American: Red and indicates that this card is to be removed from the Shelf. I believe they mean that this card is to be replaced. European: Amber and indicated that this card is in a failed state. The meaning of LED_2 and LED_3 are defined by the system implementer but LED_2 should be Green and LED_3 should be Amber. Section 3.2.5.1 Blue LED page 3-63 100% OFF means that the card is operational and it is NOT safe to extract the card. 100% ON means that it is safe to extract the card. Long Blink (mostly ON) means transition from state M1 to state M2. Short Blink (mostly OFF) means transition from state M4 to either state M5 or state M6. See Section 3.2.4.1.7 Table 3-18 on page 3-43 Section 3.2.5.2 LED_1 page 3-64 LED_1 indicates a failure or out of service state. Section 3.2.5.3 LED_2 Green Section 3.2.5.4 LED_3 Amber ATCA Hot Swap Requirements : Rev. 30-Mar-2015 ------------------------------- Section 3.8.5 page 3-160 gives some of the board and IPMC and I2C IPM Bus requirements to implement Hot Swap Section 3.9 page 3-166 starts the overall power contro information. Section 3.9.2.1 page 3-194 Hot Swap Insertion or Extraction. Whenever the hot-swap switch is activated (be this an opening or closing of switch contacts) a 2 second period is allowed to charge the hold-up capacitor. After that, if the ouput of the Power Entry module falls below -34V then the hold up capacitor is connected to the Power Entry module's output bus and keeps the Management 3.3V and 5V power running. Whenever the hot-swap switch is de-activated (whatever switch contact arrangement implies de-activated) then an internal resistor bank discharges the hold-up capacitor to less than 60V within 1 second. ATCA requires a 8.70 msec minimum. To make this at the 200 Watt level we need 500 to 600 uFd. We need a 2.49k Ohm hold-up voltage trim resistor to provide a 90 V hold-up voltage. Hub Module Card Counts: Rev. 25-Mar-2015 ------------------------ The official Hub Module Card Counts from Wade on 25-Mar-2015 are: Prototype Build in the summer of 2015: --------------------------------------- 8 fully working cards: 2 for MSU, 2 for CERN, 1 for Rutherford, 1 for Brookhaven, 1 for Cambridge/Birmingham, 1 spare 1 card without the expensive parts installed, 2 bar PCB: Thermal Profile and view/check layout Pre-Production Build in t 201?: -------------------------------- 4 fully working cards Production Build in t 201?: ---------------------------- 19 fully working cards The parts purchases at this time will be: - for expensive stuff just enough to support the summer 2015 prototype build - for inexpensive stuf enough for all 3 builds ATCA Hardware Address Lines into IPMC & FPGA: Rev. 3-Apr-2015 --------------------------------------------- The issue with the Hub Module is that both the IPMC mezzanine and the Hub's Virtex FPGA need to receive the 8 Crate Hardware Address lines. These backplane pins are either floating or tied to Logic Ground in the backplane. The ATCA specification says to pull each of these signals up with a > 4.46k < 10.5k resistor and to bypass each line to ground with a 1nFd cap. Req. 2.298 and Req. 2.299 in Section 2.4.1.5 The LAPP IPMC document shows the same thing with the pull-ups running to the IPMC_3V3 rail. The issue with Hub is that its 1.8V Virtex FPGA inputs must also receive the 8 Hardware Address signal. As an asside the Virtex FPGA must also receive the ?x 3V3 signals that the IPMC will send to it once the IPMC knows what shelf it is withing the overall L1Calo system. So we have two instances of needing 3V3 --> 1V8 level translation. IPMC IPMBus Connections: Rev. 3-Apr-2015 ------------------------ Direct connections of the IPMB_A_SCL IPMB_A_SDA IPMB_B_SCL IPMB_B_SDA lines from the IPMC to the Zone 1 connector is OK because the IPMC mezzanine has the buffers in it and the Shelf has the pull-up resistors. IPMC MGT I2C Bus Connections to the Rev. 3-Apr-2015 FRU&SDR EEPROM and to the Power Entry Module: --------------------------------------------- One of the requirements of the MGT I2C bus (the Pay Load and AMC Management Power Bus) that originates from the IPMC is that it connects to a Blade FRU&SDR EEPROM. This requirement is describedLAPP IPMC document on page 8. The IPMC mezzanine does include the 4.7k Ohm pull-ups for the Mgt_I2C_SCL and Mgt_I2C_SDA lines. Note I think that the IPMC mezzanine itself also includes another FRU&SDR memory device. The address of the blade's FRU&SDR EEPROM must be 1010000 which is typically accomplished by tying all of the address pins on the serial EEPROM to Gnd. ATCA requires that this EEPROM be a 32k x 8bit wide device. A standard EEPROM to use is the Microchip ST 24256 part. At address = 1010000x must be powered by IPMC_3V3 ST Micro M24256-BWMN6TP. The FRU&SDR EEPROM will be mounted on side 2 of the card in an open space where it can be worked on if necessary. The SOIC-8 package will be used to make any rework easier. The maximum height of this package is 1.75 mm so it fits within the 2 mm maximum component height rule for the Hub. The ST Micro part number is: M24256-BWMN6TP which is stock at DK. This is the 3.90 mm wide body SOIC-8 package. Study of the HP 53118 Switch: Rev. 9-Mar-2016 ----------------------------- The HP 53118 based 8 port 1000 Base-T Switch was made in about 2013. Not counting the 2 "loading" capacitors for the crystal oscillator or the capacitors directly associated with the 2 power supplies themselves, there are: side 1: about 6 bypass capacitors pretty clearly associated with the switch chip. They appear to have used 4 more top side capacitors to tie the 4 heat-sink mounting holes to ground. There is 1 power filter inductor top side L3 that is probably 2012 size and probably feeding power to pin 35 XTAL_AVDD, it is clearly feed from 3V3. Side 2: has about 77 capacitors that are directly bypassing the switch chip. Most are probably 0402 case size and about 10 are probably 0805 case size. All are ceramic and most are within the footprint of the switch chip. There are 6 power filter inductors: L6 through L11. L6 is probably 3216 or 3225 case size and is on the 1V2 bus and I assume is for the AVDDL rail. The other 5 inductors are probably 2012 case size and 3 are feed from 1V2 and 2 are feed from 3V3. Summary of the HP switch power supply bypass and filters: they have done basically what you would expect , i.e. match the BCM demo board documentation, 4 rails are filtered from the 1V2 supply and 3 are filtered from the 3V3 supply. The per link LEDs appear to be about 100 or 110 Ohms from the LED anode to 3V3 and the cathodes are tied to pins like 168, 170, 174, 175, 178, 179, 184, 185, i.e. the first 2 LEDs of each 4 LED per Link group. 168 LEDP0 174 LEDP4 178 LEDP8 184 LEDP12 170 LEDP1 175 LEDP5 179 LEDP9 185 LEDP13 The HP switch is a 53118 not the 53128 that is used on Hub. The HP switch numbers its ports in the same order as the 128 chip numbers its ports, but the HP switch used 1:8 instead of 0:7. The LEDs on the HP switch have their anodes pulled up to 3V3 through 100 Ohm resistors. The Cathodes of the HP switch are connectred as follows: Link Speed Link Active ------------------------ ------------------------ Port Pin Num Pin Name Port Pin Num Pin Name ---- ------- -------- ---- ------- -------- 7-8 168 LEDP0 7-8 170 LEDP1 6-7 174 LEDP4 6-7 175 LEDP5 5-6 178 LEDP8 5-6 179 LEDP9 4-5 184 LEDP12 4-5 185 LEDP13 3-4 189 LEDP16 3-4 190 LEDP17 2-3 194 LEDP20 2-3 195 LEDP21 1-2 198 LEDP24 1-2 199 LEDP25 0-1 256 LEDP28 0-1 1 LEDP29 The ports are numbered: Chip Port Num - HP Switch Port Num. OK so this is in reverse rational order as predicted by table 13 on page 75, but it is the first 2 LED pins in each group of 4 LED pins. For the purposes of connecting LEDs on the Hub Module I will uses this pinout which matches a subset of the 53128 demo board schematic. Note that Switch Ports on the Hub Module are numbered 0 through 7. Study of Other POL Power Supply Modules: Rev. 10-July-2015 ---------------------------------------- By "other" I will start with the GE modules as I have seen the Fermi guys using them. They have a whole set of confusing names. I assume that, as in the past, GE just purchased a number of smaller companies and then blam they have a power supply line. At least one of them appears to be (or have been) named Lineage Power Corp from Plano TX. We are interested only in their converters that have an MPBus monitoring/control connection. These appear to be: giga d lynx 80 amp GDT080A0X.pdf mega d lynx 40 amp MDT040A0X.pdf micro d lynx 20 amp UDT020A0X.pdf pico d lynx 12 amp PDT012A0X.pdf pico d lynx 6 amp PDT006A0X.pdf pico d lynx 3 amp PDT003A0X.pdf micro d lynx 12 amp dual UDXS1212A0X.pdf At this point it is not clear how consistent the operation and features of this whole line of converters are. For the light < 3 Amp load is it going to be easier to use a Linear, e.g. LT1764A ? Focus on understanding the details of one of these modules: 20 Amp Part Number: UDT020A0X3-SRZ 475 kHz to 525 kHz Switching Frequency Given exact Rset resistor the output voltage will be within +- 1% Output voltage drift ofer Vin, Load, Temp, Life withing +- 3% Output voltage over Vin min to Vin max 5 mV Output voltage over Load min to max 10 mV Output voltage over Temp min to max 0.4% of Vout monimal Output current foldback at a nominal 130% of rated output On/Off Control normal is "negative logic" special option "4" is "positive logic" for normal logic signal Hi (>2V.0) --> supply is OFF logic signal Low (<0.6V) --> supply is ON Turn ON Delay (case where power has been applied for > 1 sec) and then the converter is turn ON) 600 to 1800 usec Output voltage Ramp Time 10% to 90% 1.2 to 2.7 msec Typical Rtrim values: 30k Ohm --> 1.0V 10k Ohm --> 1.8V 4.444k --> 3.3V Rtrim in kOhm = 12 / (Vout - 0.6) Tracking Accuracy Vseq - Vout 100 mV max ?? Power Good signal Open Drain 90% to 105% of Vout set ?? Digital PMBus Interface 3.3 V bus Vout Measurement Range 0 V to 5.5 V Vout Measurement Resolution 15.62 mV Vout Measurement Accuracy -15 to +5 % Vout Measurement Offset +- 3% Output Current Measurement Range 0A to 26 A Output Current Measurement Resolution 62.5 mA Output Current Measurement Accuracy +- 5% Output Current Measurement Offset 100 mA Input Filter: 2x or 3x 22 uFd ceramic caps Output Filter: 1x 100 nFd plus 2x 47 uFd ceramic minimum for additional filtering Low ERS Polymer and Ceramic caps are recommended. they show: 2x, 4x, 6x, 8x 47 uFd ceramic Max Cout without tuning the loop 2x 47 uFd Max Cout with tuning the loop for ESR > 0.15 mOhm 1,000 uFd for ESR > 10 mOhm 10,000 uFd On/OFF control can be by the On/Off pin or by PMBus Can be set in non-volital memory to be both, just one or just the other. Hub Module Power Bus Table: ReDo 22-July-2015 --------------------------- ====== Bus Anticipated Converter Supply NetName Voltage Consumers Load Capacity Name --------- ------- --------------- ----------- --------- ------ FPGA_CORE 1.000 V FPGA VCCINT 2.3 A qscnt 40 Amps DCDC-1 FPGA VCCBRAM 5.8 A start -------------- 17 A Est by Ed 16 July GTH_AVCC 1.000 V FPGA GTH 20 Amps 40 Amps DCDC-2 Est by Ed 16 July GTH_AVTT 1.200 V FPGA GTH 9 Amps 20 Amps DCDC-3 Est by Ed 16 July GTH_AVAUX 1.800 V FPGA GTH 2.0 Amps 3 Amps DCDC-4 Linear Reg. SWCH_1V2 1.200 V Switch Ethernet 3.5 A Exptd 12 Amps DCDC-5 Phys Chips 0.5 A Exptd ------------- 4.0 A Exptd BULK_1V8 1.800 V FPGA VCCAUX 147 mA qscnt 12 Amps DCDC-6 FPGA VCCAUX_IO 2 mA qscnt FPGA VCCO 1 mA/bnk q Phys Chips 0.2 A Exptd ------------- ? A Exptd FAN_1V8 1.800 V GTH Fanout 13 A Exptd 20 Amps DCDC-7 ------------- 13 A Exptd BULK_3V3 3.300 V Switch Ethernet 1.5 A Exptd 20 Amps DCDC-8 Phys Chips 0.2 A Exptd Clock Gen & Fan 5.0 A Resvd Optical Comps 0.6 A Exptd Supply Linear Regs. 6.0 A Exptd ------------- 13.3 A Exptd POD_2V5 2.500 V MiniPOD Comps 1 A Exptd 3 Amps DCDC-9 Linear Reg. 40 Amp 13.46 x 33.02 10.90 tall MDT040A0X3-SRPHZ about $ 31.55 20 Amp 11.43 x 20.32 8.50 tall UDT020A0X3-SRZ about $ 16.67 12 Amp 12.19 x 12.19 8.50 tall PDT012A0X3-SRZ about $ 13.43 6 Amp 12.19 x 12.19 7.25 tall PDT006A0X3-SRZ about $ 10.58 3 Amp LDO Linear Adjustable 5DDPAK LT1764AEQ#TRPBF about $ 8.58 standard tube of 50 LT1764AEQ#PBF about $ 7.41 GTH and GTY Reference Clock Clock Study for UltraScale: 22-Dec-2015 ------------------------------------------------------- I am/have gone back through all of this to make it fit the requirements for the UltraScale GTH and GTY transceivers. PCS = Physical Coding Sublayer PMA = Physical Medium Attachment GTH: Each Quad has 2 LC tank Plls (QPLL) and one ring oscillator PLL (CPLL) Allows sharing of Reference Clock from two Quads below or from two Quads above BUT Reference Clocks do NOT cross SLRs Super Logic Regions in the UltraScale Stacked Silicon. Pg 32 makes it exactly clear: you can go up 2 Quands and down 2 Quads, i.e. drive 20 GTH channels, without jitter problems in high speed designs. This holds for running 2 clock signals as summerized on page 36. GTH Line Rate: -1 speed grade 0.95 Volt For CPLL with Output Divider 1 4.0 min 8.5 max Gb/s For CPLL with Output Divider 2 2.0 min 4.25 max Gb/s For CPLL with Output Divider 4 1.0 min 2.125 max Gb/s For CPLL with Output Divider 8 0.5 min 1.0625 max Gb/s For QPLL0 with Output Divider 1 9.8 min 12.5 max Gb/s For QPLL0 with Output Divider 2 4.9 min 8.1875 max Gb/s For QPLL0 with Output Divider 4 2.45 min 4.09375 max Gb/s For QPLL0 with Output Divider 8 1.225 min 2.04688 max Gb/s For QPLL0 with Output Divider 16 0.6125 min 1.02344 max Gb/s For QPLL1 with Output Divider 1 8.0 min 12.5 max Gb/s For QPLL1 with Output Divider 2 4.0 min 6.5 max Gb/s For QPLL1 with Output Divider 4 2.0 min 3.25 max Gb/s For QPLL1 with Output Divider 8 1.0 min 1.625 max Gb/s For QPLL1 with Output Divider 16 0.5 min 0.8125 max Gb/s Fpllout x 2 N1 x N2 For CPLL: Fline = ----------- and Fpllout = Fpllin x --------- D M where: M is 1 or 2 N1 is 4 or 5 N2 is 1,2,3,4,5 D is 1,2,4,8,16 with restrictions on 16 CPLL Fpllout == CPLL Fvco CPLL Fpllout range 2.0 GHz min 4.25 GHz max For QPLL: QPLL is required for operating at line rates above those serviced by the CPLL, i.e. above 8.5 Gb/s. Fpllout x 2 N For QPLL: Fline = ----------- and Fpllout = Fpllin x ------- D M x 2 where: M is 1,2,3,4 D is 1,2,4,16 N is 16, 20, 32, 40, 60, 64, 66, 75, 80 84, 90, 96, 100, 112, 120, 125, 150 QPLL Fpllout is 1/2 of the QPLL Fvco. QPLL0 range 9.8 GHz min 16.375 GHz max QPLL1 range 8.0 GHz min 13.000 GHz max **--> Note: It's not clear to me if these GHz ranges are the ranges of the QPLL output or the ranges of the QPLL VCO. But I think that they must be the range of the VCO and: N Fvco = Fpllin x --- M GTY: Each Quad has 2 LC tank Plls (QPLL) and one ring oscillator PLL (CPLL) Allows sharing of Reference Clock from two Quads below or from two Quads above BUT Reference Clocks do NOT cross SLRs Super Logic Regions in the UltraScale Stacked Silicon. Pg 33 makes it exactly clear: you can go up 2 Quands and down 2 Quads, i.e. drive 20 GTH channels, without jitter problems in high speed designs. This holds for running 2 clock signals as summerized on this page. BUT there are special considerations above 16.375 Gb/s line rate. Above 16.375 Gb/s QPLL0 must use Reference Clk input 0 in its Quad and QPLL1 must use Reference Clk input 1 in its Quad. GTY Line Rate: -1 speed grade 0.95 Volt For CPLL with Output Divider 1 4.0 min 8.5 max Gb/s For CPLL with Output Divider 2 2.0 min 4.25 max Gb/s For CPLL with Output Divider 4 1.0 min 2.125 max Gb/s For CPLL with Output Divider 8 0.5 min 1.0625 max Gb/s For QPLL0 with Output Divider 1 9.8 min 12.5 max Gb/s For QPLL0 with Output Divider 2 4.9 min 8.1875 max Gb/s For QPLL0 with Output Divider 4 2.45 min 4.09375 max Gb/s For QPLL0 with Output Divider 8 1.225 min 2.04688 max Gb/s For QPLL0 with Output Divider 16 0.6125 min 1.02344 max Gb/s For QPLL1 with Output Divider 1 8.0 min 12.5 max Gb/s For QPLL1 with Output Divider 2 4.0 min 6.5 max Gb/s For QPLL1 with Output Divider 4 2.0 min 3.25 max Gb/s For QPLL1 with Output Divider 8 1.0 min 1.625 max Gb/s For QPLL1 with Output Divider 16 0.5 min 0.8125 max Gb/s Fpllout x 2 N1 x N2 For CPLL: Fline = ----------- and Fpllout = Fpllin x --------- D M where: M is 1 or 2 N1 is 4 or 5 N2 is 1,2,3,4,5 D is 1, 2, 4, 8, 16, 32 with restrictions on 16 and 32 CPLL Fpllout == CPLL Fvco CPLL Fpllout range 2.0 GHz min 4.25 GHz max For QPLL: QPLL is required for operating at line rates above those serviced by the CPLL, i.e. above 8.5 Gb/s. Note: for line rates above 16.375 Gb/s that a specific Reference input within the Quad must be used for each QPLL. Note: for line rates below 16.375 Gb/s that part of the QPLL's feedback path is a Fractional divid by N scaler. Above 16.375 Gb/s only the integer part of this scaler may be used. Fpllout x 2 For QPLL: Flinerate = ----------- where D = 1,2,3,4,16, 32 D N.FractionalPart Fpllout = Fpllin x --------------------- M x QPLL_CLKOUTRATE where: M is 1,2,3,4 N is 16 through 160 QPLL_CLKOUTRATE is 1 for FULL or 2 or HALF i.e. the PLL block output is either full or half of the VCO frequency for linerates > 16.375 Gb/s set FULL otherwise set HALF I think that for speed grade -1 that we must use HALF. SDMDATA FractionalPart = ------------------- 2 to the SDMWIDTH where: SDMDATA is 0 through (2 to the 24 -1) SDMWIDTH is 16, 20, 24 QPLL0 Fpllout range 9.8 GHz min 16.375 GHz max QPLL1 Fpllout range 8.0 GHz min 13.000 GHz max Which piece of silicon (SLR) in the XCVU125 are the various GTH and GTY transceivers on. - SLR 0 has: the special Configuration Bank 0 and Select I/O Banks: 65, 66, 67, 68, 84 and 94 GTY Quads: 124, 125, 126, 127, 128 GTH Quads: 224, 225, 226, 227, 228 - SLR 1 has: Select I/O Banks: 70, 71, 72 GTY Quads: 129, 130, 131, 132, 133 GTH Quads: 229, 230, 231, 232, 233 I *believe* that the only line rates of interest in the overall L1Calo project are: 4.8, 6.4, and 9.6 Gbps. All of these line rates are LHC locked so by this I mean that for a 40.08 MHz LHC frequency that the line rates would be: 4.8096 Gbps i.e. 120x the 40.08 MHz from the LHC 6.4128 Gbps i.e. 160x the 40.08 MHz from the LHC 9.6192 Gbps i.e. 240x the 40.08 MHz from the LHC To make the ratio from 40.08 MHz to the Ref Clock frequency about the same as the ratio from Ref Clock frequency to the PLL output frequency, i.e. to balance the multiplications, we want Ref Clock frequencies of about: sqrt 60 is about 7.75 or sqrt 60 x 40.08 = 310 MHz sqrt 80 is about 8.94 or sqrt 80 x 40.08 = 358 MHz sqrt 120 is about 10.6 or sqrt 120 x 40.08 = 439 MHz Recall that the PLL output frequency is typically 1/2 of the Line Rate in our range of line rates, i.e. D is typically 1. So making the first multiplication be 8x to 320.64 MHz is not over doing it. The alloed Ref Clock Freq Range is 60 to 820 MHz (for both GTH and GTY) and 320.64 MHz is more or less in the middle and less than 1/2 the max. To get from a 320.64 MHz Reference Clock to these Line Rates using the CPLL (for either GTH or GTY): Using CPLL -------------------- Line Rate N1 N2 M D VCO ----------- -- -- - - ------ 4.8096 Gbps: 5 3 2 1 2.4048 <-- OK 6.4128 Gbps: 5 2 1 1 3.2064 <-- nice in the middle 9.6192 Gbps: CPLL does not support line rates over 8.5 Gb/s Recall for CPLL: N1 = 4, 5 N2 = 1, 2, 3, 4, 5 M = 1, 2 D = 1, 2, 4, 8 CPLL VCO = 2.0 to 4.25 GHz N1 x N2 Fvco = --------- x Fref M To get from a 320.64 MHz Reference Clock to these Line Rates using the QPLL (for either GTH or GTY): N VCO is Using QPLL ------- N ------------- D x M --- x 320 Line Rate N M D must be M ----------- --- --- --- ----------- --------- 4.8096 Gbps: 60 2 2 15 9.6192 <-- QPPL1 6.4128 Gbps: 40 1 2 20 12.8256 9.6192 Gbps: 60 2 1 30 9.6192 <-- QPPL1 where: M is 1,2,3,4 D is 1,2,4,16 N is 16, 20, 32, 40, 60, 64, 66, 75, 80 84, 90, 96, 100, 112, 120, 125, 150 QPLL0 VCO range 9.8 GHz min 16.375 GHz max QPLL1 VCO range 8.0 GHz min 13.000 GHz max N Recal: Fvco = Fpllin x --- M Note: for 4.8 and 9.6 Gb/s, that N, M could also be 120 and 4 but that is probably not a smart option. Note: for 6.4 Gb/s, that N, M could also be 80 and 2 which may or may not be a smart option depending on the type of phase comparator that Xilinx uses in the QPLL. Note: for 4.8 and 9.6 Gb/s, for the GTY only, M, N could also be 30 and 1 which may be a smart option. Note: the only values of "N" available for the Virtex-7 QPLL were: 16, 20, 32, 40, 64, 66, 80, 100. That's why we needed both a 320 MHz and a 240 MHz Reference Clock for the Virtex-7. While on the topic of MGT Reference Clocks let's get straight the signal requirements for Virtex-7. - It's 100 Ohm differential. - It's AC coupled. - They reccomment 100 nFd caps but let's think about this as they specifically consider this cap as a high pass filter. We need Cx << 100 Ohm at 100 MHz are higher. Even 1 nFd is less than 2 Ohms at 100 MHz - so 10 nFd is just fine and is a better high pass filter. Note also that in Virtex-6 they said 10 nFd. - Jitter requirement it protocol dependent. - Differential Amplitude requirement is specified in the Xilinx standard, i.e. the difference between P-N in the low state and P-N in the high state. With this definition the Differential Amplitude requirement is > 250 mV < 2000 mV for either the CPLL or QPLL in the UltraScale Virtex. In other places this would be called > 125 mV < 1000 mV. - I believe that they still hind that PECL is prefered. GE DCDC Converter Input Filter: 24-July-2015 ------------------------------- This section is notes on the design of the Input Filter for the DCDC Converters on the Hub Module. - The 7 GE DCDC Converters on the Hub Module all run from the Isolated +12V bus that comes from the Synqor 25 Amp isolated supply PQ60120QEA25. This supply can handle a maximum capacitive load of 12,000 uFd. - I will assume that half of this 12,000 uFd is on the ROD and half is on the Hub Module itself. - There is no isolation between the inputs of the 7 GE DCDC Converters on the Hub. That is there are no series filter inductors between them an no series input current measuring shunts between them. There was no space on the Hub Module for such components. - Rather all 7 GE DCDC Converters are directly connected to the Isolated +12V bus. In that sense - they are all sharing one Input Filter that at maximum can have 6,000 uFd of capacitance - In the design I will break up this filter into two logical sections: Each of the 7 DCDC Converters will have in its design just the "close in" decoupling capacitors, e.g. a 10 nFd or a 47 uFd as typically called CI1 in the GE drawings and the close in larger ceramic caps, typically 2 or 3 22 uFd in the GE drawings. The 7 Converters will share one common "Bulk" part of the filter. I will include the placement and net connections to this "Bulk" filter section in the comps and nets file for the DCDC-1 converter. - Most of the components in the Bulk section of this input filter will need to be placed on the back side of the Hub PCB. Because of this these components are limited to a 2.0 mm maximum installed component height. - Thus the two types of components that are used in the Bulk section of the Input Filter are the following: T520V226M020ATE040 22 uFd 20V 40 mOhm V case 2.2 Rip Amps 1.9 mm thick rated for continuous operation at 80% of Vr at up to 105 deg C. C1206C106K3RACTU 10 uFd 25V 1206 X7R 1.8 mm thick The hope is that the Tantalum parts will provide some physical protection for the ceramic parts against shorting to the side 2 cover. The hope is that the ceramic parts will provide some protection against spikes getting into the Tantalum caps, although these Tantalum parts are rated for spikes right up to their Vr voltage. - Note that this Bulk section of the Input Filter for the GE DCDC Converters on the back side of the Hub PCB will be mostly located under the section of the Hub where the ROD is mounted. - In this way the Bulk section of the Input Filter for the GE DCDC Converters is also a filter for the Isolated +12V power that is feed up on MegArray Connector #1 to the ROD mezzanine. - The following list the typical Input Filters shown in the GE drawings for their converters and then expands these numbers to what I assume GE would conside appropriate for the operation of their converters on the Hub Module: Converter Size: 40 Amp 20 Amp 12 Amp Number on the Hub: 2 3 2 Local Decoupling: 1x 10 nFd 1x 47 nFd 1x 47 nFd per converter 3x 22 uFd 3x 22 uFd 2x 22 nFd Bulk Input Filter: 1x 470 uFd 1x 470 uFd 1x 470 uFd per converter Total Bulk Filter: 940 uFd 1410 uFd 940 uFd for the number of this type of converter on the Hub Module Grant Total of All Sections of the Bulk Input Filter: 3,290 uFd - 3,290 uFd is an OK number for the Bulk Filter in the sense that it is about 1/2 of our maximum possible allocation on the Hub half of the Isolated +12V supply. - Using a 50/50 mix of the 22 uFd Tant caps and 10 uFd ceramic caps it would take over 200 parts to reach 3,290 uFd. That's a square array with 14 parts on a side. - Recall that in the SW corner of the PCB at the output of the Isolated +12V supply we have some additional capacitors on this bus. At that point there are: 4x 10 uFd ceramic, 2x 22 uFd Tantalum, and 2x 330 uFd Polymer Aluminum electrolytic capacitors. This is a total of 744 uFd. - In the initial layout of the Bulk Input Filter capacitors we have 48x 22 uFd Tant and 96x 10 uFd Ceramic capacitors. This is a total of 2016 uFd with 960 uFd from ceramic and 1056 uFd from Tantalum. - This initial layout of the Bulk Input Filter capacitors plus the capacitors at the output of the Isolated +12V supply in the SW corner of the card makes a total of 2760 uFd with 1100 uFd Tantalum, 1000 uFd Ceramic, and 660 uFd of Polymer Aluminum electrolytic capacitors. GE DCDC Converter OUTput Filter: 28-July-2015 -------------------------------- This section is notes on the design of the OUTput Filter for the DCDC Converters on the Hub Module. - The 7 GE DCDC Converters on the Hub Module all have minimum and maximum specifications on their output filter capacitors. The following table is a summary of this information about the Output Filter capacitors for the 3 types of converters used on the Hub Module. Converter Size: 40 Amp 20 Amp 12 Amp Without Loop Tune ESR > 1 mOhm Min: 6x 47 2x 47 22 uFd Max: 6x 47 2x 47 47 uFd With Loop Tune ESR > 0.15 Min: 6x 47 2x 47 22 uFd mOhm Max: 7,000 1,000 1k uFd With Loop Tune ESR > 10 Min: 6x 47 2x 47 22 uFd mOhm Max: 8,500 10,000 5k uFd - On some of the power supply rails there is a large amount of bypass capacitance at the load itself. This table is the bypass capacitors located at the FPGA loads: DCDC-1 FPGA_CORE Bus VCCINT & VCCBRAM 8x 470 uFd 2.5V case V 9 mOhm C10 : C17 1.000 V Supply 4x 10 uFd 10V 0805 X7R C20 : C23 3760 uFd total Tant 10x 2.2 uFd 10 V 0603 X7R C30 : C39 62 uFd total Ceramic DCDC-6 BULK_1V8 Bus 2x 470 uFd 2.5V case V 9 mOhm C50, C51 VCCAUX, VCCAUX_IO, 10x 10 uFd 10V 0805 X7R C60 : C69 VCCO Bank 0 10x 2.2 uFd 10 V 0603 X7R C70 : C79 VCCO per Bank, 12 Banks 940 uFd total Tant 122 uFd total Ceramic DCDC-2 GTH_AVCC Bus 2x 470 uFd 2.5V case V 9 mOhm C90, C91 1.000 V 6x 10 uFd 10V 0805 X7R C100 : C105 940 uFd total Tant 6x 2.2 uFd 10 V 0603 X7R C110 : C115 73 uFd total Ceramic DCDC-3 GTH_AVTT Bus 2x 470 uFd 2.5V case V 9 mOhm C120, C121 1.200 V 6x 10 uFd 10V 0805 X7R C130 : C135 940 uFd total Tant 6x 2.2 uFd 10 V 0603 X7R C140 : C145 73 uFd total Ceramic DCDC-4 GTH_AVAUX Bus 2x 470 uFd 2.5V case V 9 mOhm C150, C151 1.200 V 6x 10 uFd 10V 0805 X7R C160 : C165 940 uFd total Tant 6x 2.2 uFd 10 V 0603 X7R C170 : C175 73 uFd total Ceramic - The combination of the Output Filter capacitors located at the DCDC converter plus the bypass capacitors located at the load: All of this counts towards the total capacitance on the DCDC converter and must be accounted for in its loop compensation. All of this counts towards controlling the ripple voltage noise from the converter. All of this counts towards controlling the transit response of the converter. - At least for the Virtex FPGA converters, it looks like we need to pack as much ceramic as we can right at the converter output in order to get the required ripple noise voltage performance as possible. This is partly because the Xilinx specified bypass capacitors at the FPGA load are mostly for lower frequency, i.e. heavy on Tantalum. GE DCDC Converter Design for the Virtex MTG Transceivers: 27-July-2015 --------------------------------------------------------- This section is a summary of the GE design of the supply for the Virtex-7 MTG Transceivers. This is from GE application note AM3_V3 Supply Supply Bus Local Input Output Loop Bus Module Volt & Amp Filter Caps Filter Caps Tune RC ------ ------- ----------- ------------ ------------ ------- AVCC UDT020A 1.000V 12A 1x 100 nFd C 1x 100 nFd C 249 Ohm 2x 22 uFd C 4x 47 uFd C 10 nFd 2x 330 uFd T AVTT PDT012A 1.200V 8A 1x 100 nFd C 1x 100 nFd C 249 Ohm 2x 22 uFd C 4x 47 uFd C 10 nFd 2x 330 uFd T AVAUX PDT012A 1.800V 2.6A 1x 100 nFd C 1x 100 nFd C 249 Ohm 1x 22 uFd C 4x 47 uFd C 3.3 nFd 1x 330 uFd T Notes: In addition to the per supply input filter capacitors listed in the table above, the module has 2x 470 uFd Aluminum electrolytic caps on its input +12 Volt bus. This is a power supply module design and there would be additional capacitors on its three output power buses down on the circuit board with the Virtex part. Sequencing the GE DCDC Converters: 19-Oct-2015 ---------------------------------- Now that we have moved to using the GE DCDC Converter we must re-visit the issue of sequencing the power rails using these new converters. The "standard" GE converters, i.e. withOUT the -4 part number option, have negative On/Off control logic. That is, voltage Hi to the On/Off pin tells the converter to shut-down. This is a dumb stupid setup but this is how their standard parts work. I checked and the -4 part number option GE converters with rational On/Off control do not appear to be out in distribution. I think that it is possible to program the polarity of the On/Off control signal from the PMBus connection to the controller on this part but there is no clean way to handle this without making up a jig to pre-process these parts. The On/Off input to the converters is not Hi Z. We must supply significant pull UP current to turn the converter Off. They recommend a 20k pull-up to Vin for Vin between 3V and 14V. Recall that we have 6 of these inputs in parallel. A little reverse engineering of their schematic suggests that 0.1 mA of HI current into the On/Off pin should shutdown the converter. The specification sheet says: Logic Hi, Module Off, > 2 V, < 1 mA Logic Low, Module On, < 0.6 V, < 10 uA The On/Off control pin to these converters looks like a 20k Ohm series resistor to the base of a NPN transistor, whose emitter is grounded, in parallel with another 20k Ohm resistor to ground. Recall that the specified ramp time for all of the Xilinx supplies is > 200 usec < 50 msec The "middle" of this range is about 3 to 5 msec. Recall how the SEQ input to the GE modules works. You need a Vseq voltage that for each converter is scaled down by the same ratio as the Vout loop is scaling up the 600 mV reference in the TPS-40400 controller chip. In that way a number of converters can be tied to the same source of Vseq and they will all track it up, volt per volt, until the voltage at their SEQ pin is > 600 mV at which point their voltage regulation loop takes over. So for the Vseq source it must be able to linearly ramp up to > 3.3 V in about 5 msec and supply about 1 mA of pull up current. The Sequencing plan is the following: - Use the currently unused isolated auxiliary +5V output from the ATCA Power Entry module to power the startup sequencing circuits. This isolated auxiliary +5V output is "Always ON" whenever the ATCA Power Entry module receives its 48V input power. This isolated auxiliary +5V supply can provide up to 150 mA and can have a miximum capacitive load of 1000 uFd. Note that this isolated auxiliary +5V supply will be ON before the IPMC has received permission to turn on the main isolated +12V supply. This auxiliary "Always On" +5V supply is used to power the TI TPS3808 startup supervisor circuits. The TI TPS3808 parts must have a Vcc of less than 6.5V so this "Always ON" +5V supply is just fine for this use. - Supervisor #1 This supervisor waits until Isolated +12V is above 10 volts, then delays for 1 second, then it turns ON the DCDC Converters and allows Supervisor #2 to start. Note that the standard model of the GE DCDC Converters have a Hight --> ON ON/OFF pin. Thus the output of Supervisor #1 must be inverted before it is sent to the ON/OFF control pin on these converters. - Supervisor #2 Delay and then start the ramp - Supervisor #3 Delay and then turn on the Switch_1V2 supply - The linear POD_2V5 and AVAUX_1V8 regulators are always ON and their output will ramp up as the BULK_3V3 converter's output ramps up. Reset Signals to the: 3 Switch Chips and to the 2 Phys Chips Orientation and Air Flow of the GE DCDC Converters: 3-Aug-2015 --------------------------------------------------- For all 3 types of GE DCDC Converters on the Hub Module the required orientation to put the ATCA upward air flow in the reccommended direction for these converters leaves their Vin, Vout, and Gnd pins in very bad positions for good routing and for giving sufficient space for capacitors. Thus I'm giving up on puting the air flow in the recommended direction. Note that the data sheet days nothing about how much better the recommended air flow direction is compared to the other directions. In any case who knows how the air is flowing when you are right up against the edge of the ROD card. The 40 Amp and 20 Amp converters are placed with their long axis vertical, i.e. along the direction of the upward ATAC air flow. This looks like it should be OK as in this orientation the air flow can get between the bottom of the ferrite inductor and the top of the power module's pcb. ROD Schematics from Ed on 13-Aug-2015 Reader's Guide: 14-Aug-2015 ------------------------------------------------------- Page Contents 1 Title and Reminders 2 MegArray S1 3 MegArray S2 4 GTH Quads 110, 111, 112 MG Clk 7 SC Clk C 5 GTH Quads 113, 114, 115, 116 MG Clk 4 R Cal Resistor 6 GTH Quads 117, 118, 119 MG Clk 1 FLX CLK 0 7 GTH Quads 210, 211, 212 MG Clk 6 AC Coupling Caps 8 GTH Quads 213, 214, 215, 216 MG Clk 5 R Cal Resistor 9 GTH Quads 217, 218, 219 MG Clk 3 FLX CLK 1 10 Sel IO Banks 14, 15 Flash Config Memory Sel Io Bank 16 not used all 3 with 100 Ohm VRN VRP 11 Sel IO Banks 17, 19 not used all 3 with 100 Ohm VRN VRP Sel Io Bank 18 LOC_ADRS 1:8 PWR_CON 3,4 T_WRN_B T_CRIT_B TEST1 1:4 12 Sel IO Bank 34 not used all 3 with 100 Ohm VRN VRP Sel IO Bank 35 CK_INT LHC_CLK1 P/N Sel IO Bank 36 Ethernet Phys connection 13 Sel IO Bank 37 MiniPOD RST & Int all 3 with 100 Ohm VRN VRP Sel IO Bank 38 Front Panel 6,7,8 TBD Diff Links to Hub 0,1,2,3 Sel IO Bank 39 I2C and other serial buses 14 FPGA Core and BRAM Power and bypass caps 15 FPGA: Configuration lines CCK, DONE, INIT_B PROG_B, M lines 3x FPGA: CFGBVS_0 FPGA: AUX_IO power, VCC0_0 power, VCCBAT power FPGA: System ADC and its PS, LM82 Temp 16 4x MiniPODs, MiniPOD AC coupling caps, Translators 1v8 3v3: SCL2_3v3 SDA2_3V3 POD_RST POD_INT 17 CLOCKS 40.08 MHz SI5338B-B-GM CDCE62005RGZ 18 Clock Fanout 8x GTH CDCLVP111 19 Ethernet PHYS KSZ9031 and its 25 MHz rock AT24MAC on the 1V8 SCL2/SDA2 bus 20 Power Supply Control, AUX Power Supply 3V3 I think Translator 1V8 to 3V3 for SCL0 and SDA0 21 40 Amp module for VCC_1V0 Adrs 0011 010 No LC 22 40 Amp module for GTH AVCC Adrs 0011 011 With LC 23 6 Amp module for VCC_1V8 Adrs 0011 101 No LC 12 Amp module for GTH AVTT Adrs 0011 100 With LC 24 6 Amp module for VCC_3V3 Adrs 0011 117 No LC 6 Amp module for VCC_2V5 Adrs 0011 110 No LC TPS74401RGW FOR GTH AVAUX No LC 25 Power Supply LEDs Green 7x FDV301N N-MOS Power Good summer with 74LVC08PW jump over all Power Good to 1V8 with 74LVC1T45 26 Config Flash Memory ?? 2x PC28F00A Configuration held off by holding INIT_B Low at Power Up Flash Chip Enables with NC7SZU04GW 74LVC1G32 all 1V8 Notes: Translators are typically: PCA9306, 74AVC4T245, 74VC1T45 PWRCON_3 PWRCON_4 Bank 18 page 11 10k Ohm Pull-Up on JTAG TCK and TMS on page 15 CFGBVS_0 ?? on page 15 Power Control on page 20: Receive PWR_CON1 with a 74VC1T45, PWR_CON1 is pulled down with 1k Ohm Mix in T_CRIT_B from a 74UP1G74 with a NC7SZ08 and that enables the LM38880 sequencer mostly all powered from AUX_SUPPLY and the Enables to modules flipped with N-MOS transistors PWR_CON 1,2,3,4 connections to Hub on pages: 3, 11, 20 INIT_B pages: 15, 26 ROD / Hub Configuration: 8-Sept-2015 ------------------------- It's not at all clear to me if there is a standard way that the FEX cards and ROD and Hub should use to Configure their FPGAs. There may be some advantage if the Hub uses the same Configuration scheme as the ROD, i.e. to help them appear as one object to the users. Ed is using a Master BPI Configuration scheme that uses two large parallel flash chips wired into a contiguous memory space. The ROD will always start by booting an engineering image at address 0.    This image will perform some basic diagnostics, as well as determine the module's location and which functional image to use.   It will then trigger a reconfiguration, and load the appropriate functional image.  For now I will use the Virtex-7 UG470 Configuration Guide to work up a Configuration Scheme for the Hub. The Master BPI mode is either 8 bit or 16 bits wide and uses Parallel NOR Flash memory. Master BPI can run in either a synchronous or asynchronous mode. I think that synchronous mode uses and external configuration clock and is faster. I think that a wider range of memory chips are available in synchonous mode. By default the FPGA uses asynchronous mode of BPI. By default it starts at address 0. It can start from another address as set by the MultiBoot ReConfiguration described in Chapter 7. In asychronous mode during reads it can autodetect whether it has 8 or 16 bits of input date. See: XAPP587 BPI Fast Configuration and Impact Flash Programming XAPP518 In-System Programming of BPI PROM Micron: P33 Axcell Sync/Async P30 Strata Flash, Axcell Sync/Async M29EW Async G18F Sync/Async Micron has a ton of different parts types available in this size of Parallel NOR Flash. Getting parts that work at 1V8 limits the range a lot. PC28F00AP30 EFA BFA TFA BGA JS28F00AP30 EFA BFA TSOP MT28GU01GAAA1GC BGA The only part that appears to be in stock at DK is the PC28F00AP30TFA. This is different from the part that Ed is using. This is a 100 nsec, 64 pin BGA 16 bit parallel part. If I want to mount TSOP on the bottom then I think that the rational parts are: JS28F00AP30BFA JS28F00AP30EFA JS28F00AP30EF0 JS28F00AP30TFA All of these parts are in the Micron Axcell family. There is also the Miron StrataFlash family. Arrow, Avnet, and DK are all distributors but DK appears to stock only one part. No problem - Arrow has the JS28F in the EFA or BFA in stock and has the MT28GU01GAAA1EGC-OSIT. Dig througt the datasheets. The MT28GU01GAAA1EGC-0SIT is the good part to use from the newer G18 StrataFlash family but it only comes packaged as a BGA and I don't know if we can fit it on the top side. But the pinout of the BGA package looks much cleaner, and it is a smaller package. Going with a BGA G18 StrataFlash and using asynchronous mode looks like the cleanest and most straight forwrd way to go. We could put a TSOP part on the bottom side. The part numbers at Arrow look correct: JS28F00AP30EFA and JS28F00AP30BFA for the Uniform and Bottom Boot parts. Top Boot, Uniform, and Bottom Boot have something to do with putting four 16k Word Blocks at the Top or Bottom of thedevices address space with 64k Block in the bulk of theaddress space or having Uniform 64k Work Blocks throughout the devices address space. Setting the M Lines - On Ultra they want these lines tied to Ground or to VCCO Bank 0. either directly or through less than 1k Ohm. - On Virtex-7 Configuration Bit-Stream Length: - XCVU125 401,441,280 bits Bit-Stream Length about 50.18 MegaBytes 101,980 Configuration Frames 123 32 bit words per Configuration Frame 12,543,540 Configuration Array Size in Words 1,500 Configuration Overhead Words - XC7VX550T 229,878,496 bits Bit-Stream Length about 28.73 MegaBytes Master/Slave Recall that Master means that the FPGA drives the CCLK line. Slave means that an external source drives the CCLK line. Bothe Ultra and Virtex-7 have the Master BPI mode POR_OVERRIDE Power On Reset Delay Override is a dedicated pin. Connect to Ground for standard operation. Connect to VCCINT (not VCCO Bank 0) for a shorter Tpor time from power up to INIT_B rising edge. This delay lets the Flash Memory wake up and get itself ready to rock & roll. Other Bank(s) Used for Master BPI Configuration: - XCVU125 just Bank 65 - XC7VX550T Banks 14 & 15 Configuration Signals to Understand: POR_OVERRIDE VBATT CFGBVS M[2:0] PROGRAM_B INIT_B DONE CCLK PUDC RDWR_FCS_B D00_MOSI D01_DIN D02 D03 D[07:04] D[15:08] A[15:00]_D[31:16] EMCCLK CSI_ADV_B DOUT_CSO_B [28:16] FOE_B FWE_FCS2_B RSO_RSI TCK TMS TDI TDO Wurth Power Inductor Parts Number System: 18-Aug-2015 ------------------------------------------ It's not complicated but it's hidden behind a thick layer of web gui parameter selector stuff: - Series HCC High Current Cube abcd is in tens of uH Size Part Number Base Core ---- ---------------- ------- 8070 744 334 abcd ferrite 1090 744 333 abcd ferrite 1210 744 332 abcd ferrite 1210 744 331 abcd Irom Powder - Series HCM High Current Flat Wire abc is in tens of uH plus: 7050, 7070, 1050, 1070, 1350, 1390 Size Part Number Base Core ---- ---------------- ------------ 1078 744 308 abc MnZn ferrite 1152 744 306 abc MnZn ferrite 1190 744 301 abc MnZn ferrite 1240 744 304 abc MnZn ferrite - Series HCI High Current Flat Wire abc is in tens of uH typically flat form factor plus: 5040, 7030, 7040, 7050, 1890, 2212 Size Part Number Base Core ---- ---------------- ------------ 1030 744 323 abc Superflux ferrite 1040 744 3552 abc WE-PERM ferrite 1050 744 325 abc Superflux ferrite 1335 744 313 abc Superflux ferrite 1350 744 355 abc WE-PERM ferrite 1365 744 3551 abc WE-PERM ferrite KEMET Spice Models for Capacitors: 24-Aug-2015 ---------------------------------- The Kemet spice models are on the web at http://webspice.kemet.com For the switching noise and servo loop stability simulation I'm simplifying the Kemet version of these models and keeping only the main part of the capacitance and the series R and L. I'm dumping things like the leakage resistance and such. For the ceramic caps this seems to get you down to a simple series RLC circuit with the values of R L and C being a function of frequency. 22 uFd 1206 10V X7R C1206C226M8RACTU Note that the Kemet models did not include the 22 uFd part in this 1206 X7R 10 Volt series. What I show next is ALL data from the 10 uFd part in this series except that the capacitance component is scaled up to 22 uFd (i.e. the 10 uFd data times 2.2). The 10 uFd and 22 uFd parts are the same package size/height. Minimum Z is 4.3 mOhm at about 1.3 MHz < 20 mOhm from 660 kHz to 3.5 MHz Freq 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz ------- ------- ------- ------- ------- ------- Cap 21.8 uF 21.2 uF 20.5 uF 19.9 uF 19.2 uF 19.2 uF Res 135 17.3 5.57 4.34 5.04 11.7 mOhm Ind 1.54 nH 1.54 nH 1.54 nH 1.54 nH 824 pH 750 pH 10 uFd 0805 10V X7R C0805C106K8RACTU Minimum Z is 2.1 mOhm at about 1.8 MHz < 10 mOhm from 1.1 MHz to 3.1 MHz Freq 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz ------- ------- ------- ------- ------- ------- Cap 9.93 uF 9.64 uF 9.34 uF 9.04 uF 8.74 uF 8.74 uF Res 1230 mO 124 mO 13.6 mO 2.61 mO 4.81 mO 35.7 mOhm Ind 800 pH 800 pH 800 pH 800 pH 720 pH 620 pH 2.2 uFd 0603 10V X7R C0603C225K8RACTU Note that the Kemet models did not include the 2.2 uFd part in this 0603 X7R 10 Volt series. What I show next is ALL data from the 1 uFd part in this series except that the capacitance component is scaled up to 2.2 uFd (i.e. the 1 uFd data times 2.2). The 1 uFd and 2.2 uFd parts are the same package size/height. Minimum Z is 14.9 mOhm at about 4.79 MHz < 50 mOhm from 2.63 MHz to 10 MHz Freq 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz ------- ------- ------- ------- ------- ------- Cap 2.18 uF 2.12 uF 2.05 uF 1.99 uF 1.92 uF 1.92 uF Res 1630 mO 176 mO 30.7 mO 16.2 mO 15.3 mO 21.8 mOhm Ind 1.25 nH 1.25 nH 1.25 nH 1.25 nH 1.06 pH 650 pH 47 nFd 0402 25V X7R C0402C473K3RACTU Minimum Z is 22 mOhm at about 42 MHz < 100 mOhm from 26.3 to 69.2 MHz Freq 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz ------- ------- ------- ------- ------- ------- Cap 46.6 nF 45.3 nF 43.9 nF 42.7 nF 41.1 nF 41.1 nF Res 118 11.8 1.20 0.137 0.031 0.025 Ohm Ind 350 pH 350 pH 350 pH 350 pH 350 pH 350 pH note the range of the ESR over frequency 330 uFd V case 2.5 Volt 9 mOhm Tantalum T520V337M2R5ATE009 This model is more complicated. There is a series LRC this being L1 R1 C1. C1 is shunted by a series R2 C2. C2 in turn is shunted by a series R3 C3. C3 in turn ... through C5. Minimum Z is 6.9 mOhm at about 209 kHz < 25 mOhm from 20 kHz to 2.75 MHz C1 = 10.65 uFd C2 = 21.29 uFd C3 = 42.58 uFd C4 = 85.16 uFd C5 = 170.32 uFd Freq 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz ------- ------- ------- ------- ------- ------- Ind 1.90 nH 1.90 nH 1.90 nH 1.90 nH 1.63 nH 1.45 nH R1 45.5 8.15 4.42 4.09 4.47 8.66 mOhm R2:R5 21.8 3.11 1.24 1.07 1.26 3.36 mOhm 470 uFd V case 2.5 Volt 9 mOhm Tantalum T520V477M2R5ATE009 This model is more complicated. There is a series LRC this being L1 R1 C1. C1 is shunted by a series R2 C2. C2 in turn is shunted by a series R3 C3. C3 in turn ... through C5. Minimum Z is 6.02 mOhm at about 174 kHz < 25 mOhm from 13.8 kHz to 2.75 MHz At 10 MHz the Z is about 0.1 Ohm At 100 MHz the Z is about 1 Ohm C1 = 15.2 uFd C2 = 30.3 uFd C3 = 60.7 uFd C4 = 121.3 uFd C5 = 242.6 uFd Freq 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz ------- ------- ------- ------- ------- ------- ------- Ind 1.90 nH 1.90 nH 1.90 nH 1.90 nH 1.61 nH 1.45 nH 1.45 nH R1 34.9 6.76 3.95 3.71 4.03 7.48 42.1 mOhm R2:R5 16.5 2.41 1.01 0.885 1.04 2.77 20.1 mOhm Modeling the TPS40400 Based GE DCDC Converters: 21-Aug-2015 ----------------------------------------------- The power modulator section of the TPS40400 based GE converters is I think "easy" to model because the power modulator section has a constant gain of 6 (note not -6). Page 15 of the TPS40400 manual says, "For modeling purposes, the gain from the COMP pin to the average voltage at the input of the L-C filter is 6V/V". Recall that different models are needed for the continuous and discontinous inductor current modes of operation. An issue is that the LRC values in the Kemet Spice models are a function of frequency. The approach that I will take is to for a given capacitor type use the values of LRC for the frequency range where one expects that capacitor type to be effective. Note that this may/will for example over estimate the effectiveness of the Tantalum capacitors above 10 MHz. The other rational approach is to set the capacitor spice model LRC values for a given frequency and then run spice just in that frequency range - change the capacitor LRC values and run spice again. An issue is the R and L values of the Via, Trace, and Pad running from the PCB planes to the SMD capacitor, either ceramic or Tantalum. Xilinx suggests that typical values for the via, trace, and pad inductance are in the range 300 pH to 4 nH. Another rational looking web page showns about 600 pH for well done side via 0402 capacitors. This typically about doubles to have the capacitor on the other side of the PCB that the testing circuit. Long but not irrational traces get you up to about 1.5 uH. Tight side vias look slightly better than tight end vias. For now I will use 1 nH i.e. the middle of the range for all capacitor SMD layouts. Side via small ceramics may be less and big V case Tants may be more. The big Tants have multiple vias and thicker traces so perhaps they are not much more. Any trace resistance estimare must clearly be a function of frequency and probably grows as the sqrt of frequency. The "bandwidth" of the Error Amplifier in the TPS40400 is another parameter that we need for an accurate simulation of the power supply servo loop. TI specifies a Gain Bandwidth Product of the Error Amplifier as 15 MHz minimum and 20 MHz typical. The DC gain is 60 dB minimum. The Bias currents are 250 nAmp maximum. The Output Source and Sink currents are 1 mA minimum. But the TPS40400 is more complicated than this. The Remote Voltage Sense Amplifier is also in the feedback look or at least in the DC part of the loop. The Closed Loop Bandwidth of the Remote Coltage Sense Amp is specified as 2 MHz minimum and its Output can Source or Sink 1 mA minimum. For modeling I will start by putting the pole from the Error amplifier at 20 MHz/60dB = 20 kHz. The Remote Voltage Sense amp is 2 orders of magnitude above this and I'm taking the high speed part of the feedback before the Remote Sense amp so I will ignore it in the simulation for now. Resistance of the High Current Traces on the Hub: 24-Aug-2015 ------------------------------------------------- There are at least 3 high current traces, actually Area Fills, on the Hub Module and we need to know their approximate resistances. As a starting point the resistivity of copper is about 1.68**-6 Ohm-cm. That is measering the resistance across oposite faces of a 1 cm cube of copper gives about 1.68**-6 Ohms. Now make some initial estimates of the trace length and width, i.e the current path length and width, of these three high current area fills. Core 5.5cm South, 4.0cm East, 2cm Wide, 2x 1oz --> about 1.2 mOhm AVCC 2cm East, 5.5cm South, 2.5cm West, 2cm Wide, 2x 1oz --> about 1.2 mOhm AVTT 5.5cm South, 2.5cm West, 2cm Wide, 1x 1oz --> about 1.9 mOhm Study of the VCU108 Evaluation Board with VU095 FPGA: 31-Aug-2015 ----------------------------------------------------- In the User's Guide a good picture on page 104. See: Wurth 744323068, 744311100, 74479887310A, 74408943033, 744025001, 74437324220, 7443320068, 74479787210B some "C" 1208R1, CL1108-3-50TR-R which are 3 phase power inductors. In the pdf version of the Gerbers and when viewing the Allegro Gerbers with the Mentor Fablink I can not see any dog-bone on the vcu108 FPGA BGA. I will look with Philipp's PowerBook viewer. VCU108 Schematic Page Index 2 Power Supply Block Diagram 3 "Bank" 0 POR-Override, 4 Banks 44, 45 5 Bank 46 6 Banks 47, 48 7 Banks 49, 50 8 Bank 51 9 Bank 65 10 Banks 66, 67 11 Banks 68, 69 12 Banks 70, 71 13 Banks 84, 94 14 Banks 125, 136, 127 15 Banks 128, 129, 130 16 Banks 224, 225, 226, 227, 228 17 Banks 229, 230 18 Power Connections to FPGA: AVCC, AVTT, AVAUX 19 " " " " CORE, INT_IO, VCCAUX, BRAM 20, 21 Ground connections to FPGA 22 ByPass INT, INT_IO, BRAM, AUX_IO, VCCO 23 ByPass AVCC, AVTT, AVAUX 24 JTAG 25-34 DDR4 35-37 RLD3 38-45 FMC Connector 46 PCIE Card Edge Connector 47 Clocks: EMCLK, System Clock 48 Clock Programmable and Buffer 49-52 System Controller 53 QSFP+ 54-55 CFP2 Connector 56 Bullseye and SMA Connectors 57 Clock 5328 Recovery 58 Ethernet PHY Chip SGMII and Connector 59 BPI Flash Memory 60 Micro SD Memory Card 61 Dual USB UART and EEPROM 62 Buttons, Switches, and LEDs 63 Level Shifters 64 blank 65-66 SYSMON and its alalog parts 67-68 HDMI CODEC and Connector 69 PMODs and its Level Shifters 70 I2C (aka IIC) Port Expander 71 PMBus Header and Level Shifter 72 Power Connector, Switch and Power Supervisor 73 VCCINT 60A Reg 74 VCC 1V8 10A Reg 75 VADJ 10A Ref 1V8 default 76 VCC 1C2 10A Reg 77 MGTAVCC 17A Reg 1V0 78 MGTAVTT 17A Reg 1V2 79 MGTVCCAUX 1A Reg 1V8 80 UTIL 1V35 10A Reg 81 UTIL 3V3 20A Reg 82 SYS 5V0 Reg 83 SYS 2V5, SYS 1V8, SYS 1V0 REGs 84 DDR4 Terminator Supply 85 RLD3 Term Supply 86 Power Status LEDs 87 Mechanical XCVU125-FLVC2104 ByPass Capacitor & Power Requirements: 1-Sept-2015 ------------------------------------------------------- Virtex UltraScale Recommended Operating Conditions: VCCINT 0.950 V +- 3.0% VCCINT_IO 0.950 V +- 3.0% VCCBRAM 0.950 V +- 3.0% VCCAUX 1.800 V +- 3.0% VCCAUX_IO 1.800 V +- 3.0% VCCO HR 1.140 V to 3.400 V VCCO HP 0.950 V to 1.890 V VBATT MGTAVCC 1.000 V +- 3.0% MGTAVTT 1.200 V +- 2.5% MGTVCCAUX 1.800 V +- 2.8% VCCINT_IO must be connected to VCCINT VCCAUX_IO must be connected to VCCAUX If VBATT is not used then connect VBATT to either ground or to VCCAUX VCCO_0 must be a minimum of 1.425V during configuration. Quiescent Supply Currents: VCCINT 2875 mA VCCINT_IO 178 mA VCCBRAM 162 mA VCCAUX 373 mA VCCAUX_IO 148 mA VCCO 1 mA (assume per Bank) Power Supply Sequencing and Common Supplies: At Power ON: VCCINT / VCCINT_IO then VCCBRAM then VCCAUX / VCCAUX_IO then VCCO Power OFF is the reverse. VCCINT / VCCINT_IO and VCCBRAM can all be powered from the same supply and ramped simultaneiously. VCCAUX / VCCAUX_IO and VCCO can all be powered from the same supply and ramped simultaneiously. VCCINT and MGTAVCC may be ramped simultaneously. MGTAVCC should ramp before MGTAVTT. No recommended sequencing for MGTVCCAUX. Besides the Quiescent currents listed above the supplies must be able to provide the following minimum currents during power up: VCCINT / VCCINT_IO supply 4397 mA minimum additional current VCCBRAM 200 mA VCCAUX / VCCAUX_io supply 533 mA VCCO supply 54 mA All ramp times are 200 usec minimum and 40 msec max. 3.0 msec is about in the middle 16x from either side. ByPass Capacitors on the VCU108 Demo Board that has an XCVU095-2FFVA2014E FPGA with: 28 GTH, 24 GTY, 52 HR, 780 HP. Note: the Hub FPGA has: 1.43x as many GTH and 1.67x as many GTY. MGTAVCC 4x 4.7 uFd X5R - Xilinx 10x 100 uFd X6S - Maxim 10x 4.7 uFd X5R - Maxim 7x 0.22 uFd X6S - Maxim MGTAVTT 4x 4.7 uFd X5R - Xilinx 10x 100 uFd X6S - Maxim 3x 4.7 uFd X5R - Maxim 7x 0.22 uFd X6S - Maxim MGTVCCAUX 4x 4.7 uFd X5R - Xilinx 3x 4.7 uFd X5R - Maxim VCCINT & 2x 470 uFd - Xilinx VCCINT_IO 2x 100 uFd X6S - Xilinx 4x 4.7 uFd X5R - Xilinx 2x 470 uFd - Maxim 6x 100 uFd X6S - Maxim 2x 4.7 uFd X5R - Maxim VCCBRAM 1x 47 uFd X6S - Xilinx 1x 4.7 uFd X5R - Xilinx 2x 470 uFd - Maxim 2x 4.7 uFd X5R - Maxim VCCAUX & 2x 100 uFd X6S - Xilinx VCCAUX_IO 8x 4.7 uFd X5R - Xilinx 1x 100 uFd X6S - Maxim From the "ultrascale pcb design guide" ug583 ByPass Capacitor Requirements for the XCVU125-FLVC2104: VCCINT / VCCINT_IO 2x 680 uFd 3x 100 uFd 5x 4.7 uFd VCCBRAM 1x 47 uFd 1x 4.7 uFd VCCAUX / VCCAUX_IO 2x 47 uFd 4x 4.7 uFd VCCO HR or HP 1x 47 uFd MGTAVCC, MGTAVTT, MGTVCCAUX One 4.7 uFd per Power Group The XCVU125-FLVC2104 has a from the GTH & GTY Guides total of 6 Power Groups. 6 Power Groups includes both the GTH and GTY. There is the same one 4.7 uFd capacitor requirement for both the GTH and GTY transceivers. Notes: VCCINT and VCCINT_IO must be tied together on PCB. VCCAUX and VCCAUX_IO must be tied together on PCB. One 47 uFd capacitor is required for up (to) four HP/HR Banks when powered from the same VCCO voltage. 470 uFd can be used for 680 uFd in a 4 to 3 ratio. Recommended Capacitors: 680 uFd 2917/D/7343 Tant 2.1 nH <40 mOhm T530X687M006ATE018 470 uFd 2917/D/7343 Poly Al 1.5 nH <40 mOhm EEF-GXOD471R 100 uFd 1210 X7R/X5R 1.5 nH <40 mOhm GRM32EE70G107ME19 C3216X6SOG107M160AC 47 uFd 1210 X7R/X5R 1.5 nH <40 mOhm GRM32ER70J476ME20L C3225X6SOJ476M250AC 4.7 uFd 0805 X7R/X5R 1.0 nH <20 mOhm GRM21BR71A475KA73 C1005X5ROJ475M KSZ9031RNX Ethernet Phys Chip: 8-Sept-2015 ------------------------------- In our Hub application the KSZ9031RNX Phys chip requires 3 power rails: 3V3, 1V8, and 1V2 to supply 5 internal loads. These rails are used in the following way: Hub KSZ9031RNX Load Supply -------------------------- ------ AVDDL_PLL Analog Vdd PLL 1.200V -- AVDDL Analog Vdd 1.200V --| 1.2 V Core DVDDL Digital Vdd 1.200V -- DVDDH Digital Vdd 1.800V --- RGMII I/O Power AVDDH Analog Vdd 3.300V --- Transceiver Power Expect about: 221 mA on the 1V2 supply, 25 mA on the 1V8 supply, and 70 mA on the 3V3 supply. The operating range voltage requirements for these power rails is the following: 1V2 1.140 to 1.260 V +- 5% 1V8 1.710 to 1.890 V +- 5% 3V3 3.135 to 3.465 V +- 5% With a 221 mA load on the 1V2 supply and assuming that 80% of it goes into DVDDL we need its chokes to have well below 0.33 Ohm DC resistance. With a 25 mA load on the 1V8 supply we need its choke to have well below 3.6 Ohm DC resistance. With a 70 mA load on the 3V3 supply we need its choke to have well below 2.3 Ohm DC resistance. For now select our 1206 size 60 mOhm chole for all 5 applications but we can probable use our 0603 200 mOhm choke for: AVDDL_PLL, AVDDL, DVDDH, and AVDDH. In that case the large 1206 choke is only needed for the DVDDL supply. Bypass Capacitors for the KSZ9031RNX: Bypass the 3 rails with an 0805 10 uFd 10V near the chip. The 5 inductors come after these "bulk" bypass. Each of the 5 chokes has an 0805 10 uFd 10V after it. Then have one 0402 100 nFd or one 0402 47 nFd per pin so: 1 cap AVDDL_PLL Analog Vdd PLL 1.200V -- 2 caps AVDDL Analog Vdd 1.200V --| 1.2 V Core 6 caps DVDDL Digital Vdd 1.200V -- 3 caps DVDDH Digital Vdd 1.800V --- RGMII I/O Power 2 caps AVDDH Analog Vdd 3.300V --- Transceiver Power Level Translators and LED Driving for the Hub Module: 23-Nov-2015 ------------------------------------- The world has 10**9 level translators and just like on the CMX card I want to use a very limited rational set on the Hub Hub Module. Keep it simple and don't screw it up. I2C Level Translator and Buffer PCA9517A 1.2 <--> 3.6 74AVC*T245 * = 1,2,4,8,16,20,24,32 1.8 <--> 5 74LVC*T245 * = 1,2,8,16 For reference the old HC logic was specified for operation with Vcc between 2.0 V and 6.0 V. The Fairchild ULPA (aka ULP-A) TinyLogic is the same basic family as their VCX logic. VCX is designed for 1.8 / 2.5 / 3.3 Volt operation with input tolerance up to 3.6 Volt. It is designed for symmetric drive current. It is more or less equivalent to TI's ALVC. I think that Fairchild, OnSemi and Toshiba went VCX and that TI and others took the ALVC path. For now try to focus on 3 versions of translator: 74AVCH8T245 8 channels all in 1 control block 74AVCH2T45 2 channels all in 1 control block 74AVCH1T45 1 channel in 1 control block The 1T is 6 pins and the 2T is 8 pins so basically the same size. Thus where space permits use the 2T and setup the un-used section as a spare. For the 74AVCH8T245 use the TI part in the TSSOP-24 package TI SN74AVCH8T245PWR For the 74AVCH2T45 use the TI part with 0.65mm pin spacing: TI SN74AVCH2T45DCTR TI Package SM8, Industry Package 8-LSSOP, TI drawing DCT Note that NXP only makes this in the 0.5mm pin spacing and smaller packages. List of signals on the Hub that need Level Translation: - 1V8 LED signals from the ROD to LEDs on the Hub - 1V8 LED signals from the ROD's Phys to RJ45 LEDs on the Hub - 1V8 LED signals from the Hub's FPGA to Hub LEDs - 1V8 LED signals from the Hub's Phys Chips to Hub LEDs - JTAG Translator/Buffer/Driver at least buffer/driver part and translator if we want to get into the IPMC. For driving LEDs from the ROD and from the Hub's FPGA and Phys chips: the 1V8 input side is the "A" side the LED Driver output side is the "B" side to translate A-->B the Dir pin needs to be HI OE_B needs to be LOW to enable the Output else Hi_Z For the small 0805 LEDs for the 4 per row light pipes I'm targeting a 8 mA LED current. At 8mA the output of the driver should put down to no more than 0.45V above ground. at 8 mA the osram_red_0805_lsr976 LED has a Vfd of about 1.90 V at 8 mA the osram_yellow_0805_lyr976 LED has a Vfd of about 1.90 V at 8 mA the osram_green_0805_lgr971 LED has a Vfd of about 2.10 V at 8 mA the avago_blue_0805_hsmr-c170 LED has a Vfd of about 3.25 V The Red, Yellow, and Green LEDs will run off of the BULK_3V3 supply. The Blue LED will run off of the MSTR_5V0 supply. Thus the series resistors for the 0805 size LEDs are: Red ( 3.3V - 1.9V - 0.45V ) / 8 mA = 119 Ohm --> 120 Ohm Yellow ( 3.3V - 1.9V - 0.45V ) / 8 mA = 119 Ohm --> 120 Ohm Green ( 3.3V - 2.1V - 0.45V ) / 8 mA = 94 Ohm --> 100 Ohm Blue ( 5.0V - 3.25V - 0.45V ) / 8 mA = 163 Ohm --> 162 Ohm Note the problems of driving the Blue LEDs for the ROD: It requires a 5 Volt supply to run them. The translator chip can not directly drive them because: Whatever drives them has to have an output that can swing up to +5V We can not allow current to feed from the LED's Always ON MSTR_5V0 rail, through the output pin of the driver, to the Vcc supply pin on the driver and thus pull up this Vcc supply when this Vcc supply is not yet turned ON. Thus the best way to accomplish driving the Blue LEDs is with an Open Drain driver. One could use a discrete FET but I will use a 74LVC07A and use the other channels of this part to drive the Lemo connector. The data sheet for the 74LVC07A shows that its open drain can go above its Vcc pin voltage, i.e. its ouput pin is not diode clamped to its Vcc pin, so I can run the 74LVC07A from the 3V3 rail and have it switch the 5V LED with no coupling of the 5V power to the 3V3 rail. This part can handle a 24 mA pull-down current so a couple of its channels can handle the Lemo output. Power Supply V Set and Ramp Scale Resistors: 6-Nov-2015 -------------------------------------------- Collect the information about the values of the V-Set Resistors and the Ramp Scale Resistors for the 7 Hub Module DCDC Converters. V-Set V-Set Ramp Scale Ramp Scale Ramp Scale Ramp Scale DC/DC Resistor Resistor Series Gnd Shunt Tot Series Parallel Converter Theory Real Resistor Resistor Resistance Resistance --------- -------- -------- ---------- ---------- ---------- ---------- 1 0.950 34.286k 34.0k 20k 34.0k 54k 12.6k 2 1.000 30k 30k 20k 30k 50k 12k 3 1.200 20k 20k 20k 20k 40k 10k 5 1.200 20k 20k --- SWCH_1V2 supply is not ramped --- 6 1.800 10k 10k 40k 20k 60k 13.3k 7 1.800 10k 10k 40k 20k 60k 13.3k 8 3.300 4.444k 4.42k 40k 8.87k 48.87k 7.26k - A V-Set resistor of 34.0k will give a 0.953 Volt output. - A V-Set resistor of 4.42k will give a 3.315 Volt output. - Recall that we do not ramp the SWCH_1V2 supply at the same time as we ramp the 6 other supplies. Thus the common ramp control setup only needs to work with the 6 "FPGA" supplies. - The parallel compination of all 7 of the Ramp Scale series resistor networks is: 8.524k Ohm. - The point of knowing the parallel resistance of each Ramp Scale resistor network is that this is the Voltage Source resistance of the Ramp to that DCDC Converter. Holding these all within a factor of 2 of each other helps keep all of their RC time constants well matched. That's the reason for going to 40k series resistors for the higher output voltage DCDC converters. - Over temperature the Track pin Bias Current is typically 130 nA or less. 130 nA with a 15k Ohm source resistance is a 2 mV offset. Over temperature the Track pin Offset Voltage is typically 5 mV or less. So the total tracking error in the Hub setup should be 7 mV or less. - The GE data sheets show a 100 pFd noise filter capacitor across the track scale shunt resistor to ground. In our typical setup this would give a time constant of about 10k Ohm x 100 pFd = 1 usec. With our Ramp time of a few msec we can move this Track Noise Filter up to a 10 usec time constant and still have the filter time constant be less than 1% of the Ramp time, i.e. the filter well tracks the Ramp. I2C Buses: 8-Dec-2015 ---------- Recall that the IPMC masters two different I2C buses: - the Management I2C Bus and - the Sensor I2C Bus Management I2C: The functions of the Management I2C Bus is basically defined for us by the ATCA specification. The Management I2C Bus connects only to the I2C port on the ATCA power entry module and to the ATCA card's FRU&SDR EEPROM. The SynQor ATCA Power Entry Module has a limited range of I2C addresses. The SynQor Power Entry Module I2C Address is of the form: 0101xyz where only the 3 low order bits may be changed. Questions about the Management I2C bus: - Why does page 8 of the IPMC manual say that we need to put a FRU&SDR EEPROM on the Hub and then on page 4 it shows a FRU&SDR EEPROM on the IPMC itself ?? Is the EEPROM on the IPMC itself an "Event Memory" ?? - What I2C address should I assign to our SynQor ATCA Power Entry Module so that the IPMC can find it ?? - How does the IPMC magically know how to read the SynQor format data ?? - Does the IPMC give us access to the data from the Power Entry Module module so that we can see it and monitor it (like we do the data from the IPMC's Sensor I2C bus) ?? - Does the IPMC need to have the Geographic Address lines from the crate backplane isolated, i.e. so that the Hub's FPGA does not load them before the FPGA is powered up ?? Sensor I2C: The Sensor I2C Bus is sharred by the Hub and the ROD. All monitoring information that is reported through the IPMC is obtain over this one Sensor I2C Bus. I2C Address must be shared by the ROD and Hub. I2C Addresses used by the ROD are the following: 0100 000 ROD FPGA 0011 001 LM82 Temperature Monitor 0011 010 MDT040 1V0 Power Supply 0011 011 MDT040 1V05 Power Supply 0011 100 PDT012 1V2 Power Supply 0011 101 PDT006 1V8 Power Supply 0011 110 PDT006 2V5 Power Supply 0011 111 PDT006 3V3 Power Supply 1110 000 SI5338 Clock Generator The Sensor I2C Bus connections on the Hub Module are the following: - 7 power supply DCDC Converters - FPGA slave I2C port to the FPGA's System Monitor - FPGA master I2C port so that we can manage the Hub's 7 power supply modules Note that the IPMC, Hub, ROD Sensor I2C Bus will have multiple masters. This is necessary because both the ROD and the Hub need to be able to setup and control there GE power supply modules and the IPMC can not make these I2C bus cycles for us. Note that the Hub has a mixture of 1V8 and 3V3 Sensor I2C Bus targets. The TI controllers in the GE power supply modules appear to provide control over only 6 of the 7 I2C Address bits. I *think* this is the lower 6 bits. Thus the TI controllers must have an address in the range: 0 000 000 through 0 111 111 Neither the GE module or the TPS40400 data sheets ever explains how this addressing works. From other TI datasheets I believe that the high order address bit is always a zero. Note that a number of addresses in this range are reserved: 0:12, 40, 44, 45, 55, ( 64:68, 72:77, 120:127) all in decimal. I2C Buffer Issues: - the buffer needs to be able to translate from 3V3 to 1V8 in either direction. Most do not go to 1V8 and 1V8 is not defined in SMBus and PMBus. - the buffer needs to be able to cascade and to work with the NXP PCA9306 translator used on the ROD. Note that the PCA9306 does not buffer, i.e. all of the drive must come from the Hub. - the buffer needs to work with the I2C master on either side of it. - it's an advantage if the buffer has an enable that would allow us to isolate parts of the overall ROD-Hub I2C bus. recall that overall ROD-Hub will have 3 masters. - we think that it's an advantage to not use a I2C mux switch kind of buffer or an I2C address translator thing. I2C Buffer Choice: LTC4315 LTC4315IMS#PBF LTC4315IMS#PBF-ND $6.13 12 pin TSSOP 0.65mm pitch 3.2/3.45 inside space 5.23 outside Note that the LTC4315 needs only 3V3 power when translating from 3V3 to 1V8. To run the TI "Fusion" software to control the TPS40400 DCDC Controller chip one needs the Fusion software (free from TI) and one needs their usb to pmbus adapter which TI calls usb-to-gpio this is the actual part number. DK uses this TI part number $75. I2C to the SysMon We need/want to be able to see the Virtex System Monitor via I2C. The I2C interface to the System Monitor is a new feature in V7 or US. Note that this is actually a full PMBus interface. The I2C address for the SysMon can be set either through registers (via the Dynamic Reconfiguration Power DRP) or via resistors at power up. The resistors at power up allow you to set the I2C address before Configuration. There are two kins of UltraScale SysMon blocks. SYSMONE1 for the UltraScale and SYSMONE4 for the UltraScale+. Note that the big UltraScale parts with the SSI Stacked Silicon Interconnect technology that each Super Logic Region (each SLR) has a SysMon to provide monitoring within that SLR. The I2C, DRP, and JTAG access is liimited to the master SLR only, that is to SYSMONE1_X0Y0 for devices with two SLRs or to SYSMONE1_X0Y1 for devices with three SLRs. Front Panel I2C It's still not clear if we need or want a front panel I2C connection. Would need 3V3 power on to run the LTC4315 I2C buffer/translators. Hub Module Clock Generation and Distribution: 22-Dec-2015 --------------------------------------------- Recall that above some place there was a big study of what Reference Clocks were needed for the GTH Transceivers on a Hub Module based. That section has now been moved from Virtex-7 to UltraScale Virtex. I *believe* that for either Virtex-7 or for UltraScale Virtex that we need both a 240.48 MHz and a 320.64 MHz Reference Clock to get to the required Line Rates. At this time there are only 3 Line Rates under consideration: 4.8, 6.4, and 9.6 Gbps. All of these line rates are LHC locked so by this I mean that for a 40.08 MHz LHC frequency that the line rates would be: 4.8096 Gbps i.e. 120x the 40.08 MHz from the LHC 6.4128 Gbps i.e. 160x the 40.08 MHz from the LHC 9.6192 Gbps i.e. 240x the 40.08 MHz from the LHC The main questions right now are: - What logic levels do the GTH and GTY Reference Clocks need to be ?? e.g. LVDS LVPECL ?? - How to send these clocks to the FPGA Fabric Global Clock inputs ?? can the HP Global Clock inputs take a full normal LVDS signal ?? is it better to go to a Global Clock input in a HR Bank ?? Virtex UltraScale GTH Reference Clock Requirements: AC coupled. They do show an LVDS example. They show 10 nFd couple caps. They show a LVPECL example. For unused GTH referench clock inputs leave their pin unconnected. The GTH reference clock input circuit is powered by MGTAVCC. The GTH reference clock Differential peak-to-peak input voltage: 250 mV min 2000 mv max. GTH Ref Clk frequency range: 60 MHz min 820 MHz max with typical 200 psec edge time and the maximum duty cycle range of 40/60. With speed grade -1 and 0.95V power, the GTH PLL range: CPLL 2.0 GHz min 4.25 GHz max QPLL0 9.8 GHz min 16.375 GHz max QPLL1 8.0 GHz min 13.0 GHz max Virtex UltraScale GTY Reference Clock Requirements: AC coupled. They do show an LVDS example. They show 10 nFd couple caps. They show a LVPECL example. For unused GTH referench clock inputs leave their pin unconnected. The GTH reference clock input circuit is powered by MGTAVCC. The GTY reference clock Differential peak-to-peak input voltage: 250 mV min 2000 mv max. GTY Ref Clk frequency range: 60 MHz min 820 MHz max with typical 200 psec edge time and the maximum duty cycle range of 40/60. With speed grade -1 and 0.95V power, the GTY PLL range: CPLL 2.0 GHz min 4.25 GHz max QPLL0 9.8 GHz min 16.375 GHz max QPLL1 8.0 GHz min 13.0 GHz max GTH / GTY Reference Clock Executive Summary The reference clock requirements and PLL ranges look exactly the same for GTH and GTY. The RCAL circuit associated with GTH and GTY transceivers look the same: 100 Ohm to MGTRREF, other side of 100 Ohm to MGTAVTTRCAL and to MGTAVTT, with equal length under 0.5 Ohm symmetric traces MGTAVTTRCAL and MGTRREF. Select I/O HP and/vs HR I/O Banks: 52 Select I/O pins per HP Bank (in our device) 48 pins can be diff pairs, 4 pins are single-ended only 26 Select I/O pins per HR Bank (in our device) Both can do Open Drain Series Termination for outputs available in HP only Digitally Controlled Impedance DCI is available in HP only This is for inputs or outputs and used 240 Ohm from VRP to Gnd. When NOT Configured, I/O drivers are 3-stated and I/O receivers are weakly pulled-down. Let's get straight the VRP pin and the VREF pin. Vcco is what you think it is: sets the single-ended output swing VREF for single-ended standards, that use the differential input buffer, the VREF pin can be used as the reference for the other side of the diff input buffer. You can also use "Internal_Vref" or Vref_Scan" as the reference for the other side of the diff input buffer. Important Note: In band where the input I/O standard has and input reference voltage requirement (i.e. is using the diff input buffer) and and internally generated Vref is used (either Internal_Vref or Vref_Scan) then connect the dedicated VREF pin to Gnd with a 500 or 1k Ohm resistor. In banks that the I/O standard does not have an input reference requirement (i.e. normal 1/3 single-ended CMOS stuff) connect the dedicated VREF pin to GND with 500 or 1k Ohm or leave it floating. Vccaux "global auxiliary supply rail" supplies power to "interconnect logic of the vairous blocks" supplies power to input buffers for 1V8 and below standards and supplies power to the diff input buffers (which are used for diff input and single-ended input that uses a reference). Vccaux_io the "auxiliary I/O supply" powers I/O circuits must be 1V8 Vccint_io the "internal supply for I/O banks" must be connected to the Vccint supply. Can the VRP pin also do single-ended I/O ? Page 11 says yes and the pins names say yes, e.g. AU36 IO_T0U_N12_VRP_68 During Configuration, in our device, Banks 0, and 65 run wide open, LVCMOS 1V8 Fast slew 12 mA drive. In devices with multiple Super Logic Regions, banks 60 and 70 also do stuff during configuration. Our device has a bank 70 which is currently not used. For DCI to work we must tie the VRP pin to Gnd with 240 Ohm. DCI is available in HP Banks only. Single-Ended CMOS Levels: LVCMOS1V8 Vinlow max 35% Vcco --> 0.630 HP Bank Vinhi min 65% Vcco --> 1.170 Voutlow max 0.450 Vouthi min Vcco-0.450 --> 1.350 LVCMOS3V3 Vinlow max 0.800 Vinhi min 2.000 HR Bank Voutlow max 0.400 Vouthi min 2.900 UltraScale Virtex LVDS in the HP and HR I/O Banks: Min Typ Max HP Bank Diff Output Voltage: 0.247 0.350 0.600 1V8 Vcco Output Common Mode V: 1.000 1.250 1.425 Diff Input Voltage: 0.100 0.350 0.600 DC Coupled In Com Mod: 0.300 1.200 1.425 AC Coupled In Com Mod: 0.600 - 1.100 Min Typ Max HR Bank Diff Output Voltage: 0.247 0.350 0.600 2V5 Vcco Output Common Mode V: 1.000 1.250 1.485 -------- Diff Input Voltage: 0.100 0.350 0.600 DC Coupled In Com Mod: 0.300 1.200 1.500 AC Coupled In Com Mod: 0.600 - 1.100 Must read the Select I/O User Guide, the LVDS section, in the range of pages 124 through 130. Yes, AC coupled LVDS input is possible, without the user needing to provide any DC bias connection at all for the FPGA LVDS input pins. To do this you need to set the "DQS_BIAS" AND "EQ_LEVEL_0" (EQ_LEVEL_0 provides no equalization which is correct for our Logic Clock inputs). With both "DQS_BIAS" AND "EQ_LEVEL_0" then internally the correct DC common mode bias will be provided to the LVDS input pins. For DQS_BIAS also see pages 68 and others especially 127. UltraScale Virtex LVPECL - but for what type of Bank with what value Vcco ?? Min Typ Max LVPECL Diff Input Voltage: 0.100 0.350 0.600 Input Common Mode V: 0.300 1.200 1.425 So it wants a diff signal that is centered at 1.200 Volts that swings between 1.025 V and 1.375 V but can easily take a swing 0.900 V and 1.500 V while holding the 1.200 Com Mode Recall the Classic LVDS standard: Output Current from the H Bridge 3.5 mA Output Common Mode 1.2 Volts CDCLVC1216 Fanout LVDS 16 Way: Min Typ Max ----- ----- ----- Vcc Power Supply Voltage: 2.500 V Differential Input Voltage pp: 0.300 --- 1.600 V Input Common Mode Range: 1.000 --- Vcc-0.30 V Internal Reference Voltage Supply: 1.100 1.250 1.350 V Differential Output Voltage: 0.250 --- 0.450 V Common Mode Output Voltage: 1.100 --- 1.375 V Supply Current 100 MHz: --- 147 180 mA Points: I can clearly drive this with AC coupled LVPECL from the ConWin PLL. Input Select pin: Low --> In0, High --> In1 This thing only guarantes 250 mVpp output, but I guess that is at 800 MHz at minimum Vcc. I think that it will make 320 mV at 100 MHz with nominal Vcc. Can one boost it to 450 mV with under-termination ? MC100LVEP111 Fanout LVPECL 10 Way: Min Typ Max ----- ----- ----- Vcc Power Supply Voltage: 2.500 V Single-Ended Input High Voltage: 1.335 --- 1.620 Volt Single-Ended Input Low Voltage: 0.505 --- 0.875 Volt --> average of 1.355 and 0.875: 1.115 Volt best hint at optimum input CMV Output High Voltage: 1.355 1.480 1.605 Volt Output Low Voltage: 0.505 0.730 0.900 Volt --> Differential Output Voltage: 0.750 Volt --> Common Mode Output Voltage: 1.105 Volt --> Hi Output Current 50 Ohm to Vtt: 19.6 mA --> Low Output Current 50 Ohm to Vtt: 4.6 mA --> Hi Output Current 86 Ohm to Gnd: 17.2 mA --> Low Output Current 86 Ohm to Gnd: 8.49 mA --> Hi Output Current 150 Ohm to Gnd: 9.87 mA --> Low Output Current 150 Ohm to Gnd: 4.87 mA --> Hi Output Current 220 Ohm to Gnd: 6.73 mA --> Low Output Current 220 Ohm to Gnd: 3.32 mA Vtt is defined as Vcc - 2.0 Volts i.e. Vtt is 0.50 V in our case Supply Current 100 MHz: 60 90 120 mA Points: Un-Used outputs may be left open. Vbb supply not available with Vcc < 3.0 V Clock Select pin: Low --> Clk 0, Hi -> Clk 1 Figure 10 shows them setting single ended threshold at the mid point between Vcc and Gnd with two 1k Ohm resistors and a bypass cap to ground. Figure 7 in the TI document shows an AC coupled Thevin terminator for used with 2.5 Volt Vcc LVPECL for the input to this fanout chip: 105 Ohm to Gnd & 96 Ohm to 2V5 Vcc 105 Ohm parallel 96 Ohm is 50 Ohm The 96 Ohm 105 Ohm voltage divider from 2V5 gives 1.306 V ConWin PLL Characteristics: Min Typ Max ----- ----- ----- PLL VCC Supply Voltage: 3.300 V Power Supply Current: 80 mA Fin Reference Signal: 0.800 --- 3.300 Vpp Internally AC Coupled ADF4111 Reference Input: 0.400 --- 3.300 Vpp Differential Output Voltage: 0.650 Vpp into Internally Biased Output Stage 100 Ohm Use external AC Coupling Diff Load Receiver for the Single Signal Point-to-Point LVDS Clock runs SN65LVDT2DBV in a 5 pin SOT-23 package. Estimated Clock Generation and Distribution Power for the 40.08 MHz and 320.64 MHz Clocks: CLK_3V3: two of the ConWin PLLs at 80 mA each typ. 160 mA total typ. CLK_2V5: two of the SN65LVDT2DBV at 7 mA each max one of the MC100LVEP111 at 120 mA max ten pull-down current at 74 mA total one of the CDCLVC1216 at 180 mA max 381 mA total max Use the Wurth 744311470 4.7 uH 19.5 mOhm 7mmx7mm power filter inductor for both supplies. Estimated Clock Generation and Distribution Power for the 25.000 MHz Ethernet Clock: ECLK_3V3 ConWin CWX813 Oscillator at 30 mA TI CDCLVC1106 Fanout at 25 mA Total of 55 mA of 3V3 power for the 25 MHz Ethernet Clock Generation and Distribution. Use a Wurth 742792116 inductor in the 1206 package for the ECLK_3V3 filter. This inductor has 60 mOhm of resistance so expect about a 3.3 mV drop in this application. This inductor is rated for 2.5 Amps. One Final Look at FPGA Current Requirements: 15-Jan-2016 -------------------------------------------- The following is a very brief summary of Philippe's detailed look at the expected current requirements for the XCVU125 with a focus on the GTH GTY requirments. For comparison I have also listed Ed's 16-July-2015 Virtex-5 estimates. Summary: Philippe Full 109 Column #2 Ed's Estimates Port Hub UltraScale Virtex 7 UltraScale ---------- -------------- ---------- Core: 18.28 Amps 17 A 15.5 A 20.77 Amps AVCC: 6.39 20 16.2 10.76 AVTT: 7.89 9 3.96 10.01 AVAUX: 0.43 0.232 0.59 The UltraScale numbers have been upped from the Column #2 in Philippe's note by: Core 2.49A, AVCC 4.37A, AVTT 2.12A, AVAUX 0.16A to account for the 12 additional GTH Transmitters sending out Combined Data. This still needs to be checked in the Power Estimator to verify that all of the GTH/GTY connections were divided up correctly. An appearant big difference wrt the all GTH Virtex-7 is that in the UltraScale GTH/GTY: GTH takes more AVCC than GTY GTY takes more AVTT than GTH The biggest change from what was expected based on older parts is the the UltraScale GTY takes a lot of AVTT power. Per transceiver (both rec and trans running) the current requirements are about: AVCC AVTT AVAUX 1.000V 1.200V 1.800V ------ ------ ------ GTH: 0.126A 0.047A 0.0033A GTY: 0.081 0.341 0.0047 From the Hub point of view one wonders: - Is AVCC now low enough so that both AVCC and AVTT could be 20 Amp supplies ? - AVTT being bigger than AVCC, is we have one of them being a 40 Amp supply should not it be the AVTT ? Look at the VCU110 Demo Board for the XCVU190: 15-Jan-2016 ---------------------------------------------- Look at the MGT power supplies on the VCU110 demo board. It has a XCVU190 FPGA vs the XCVU125 on the Hub Module. Recall that the XCVU190 has 52 GTH and 52 GTY transceivers vs the 40 of each on the XCVU125. Thus I would expect the power supplies on the VCU110 to be 52/40 = 1.3 times bigger than what we need on the Hub. The VCU110 provides 80 Amps of Core power including that for the BRAM. It provides 45 Amps of both AVCC and AVTT. It provides only 1 Amp of AVAUX. The 80 Amp Core supply is 4 phase: after the inductor it has 2x 100 uFd 4V X6S, then 0.5 mOhm current sense, then 2x 470 uFd 2V Tant_D, then 2x 100 uFd 4V ?? (C2725), then MMSZ4680T1G 2.2V zener. The 45 Amp MGT supplies are 3 phase: after the inductor it has 2x 100 uFd 4V X6S, then 1.0 mOhm current sense, then 1x 470 uFd 2V Tant_D, then MMSZ4680T1G 2.2V zener. Both the AVCC and AVTT 45 Amps supplies include a Steward (Laird) MP0350-000 ferrite EMI plate - I assume placed under the associated power inductor. The 1 Amp MGT AVAUX supply has a 25 Amp 330 nH inductor then: 2x 100 uFd 4V X6S, no current monitor shunt resistor, then MMSZ4683T1G 3.0V zener. Decoupling Capacitors on the VCU110: CORE: Xilinx: 2x 470 uFd 2V Tant_D, 4x 100 uFd 4V X6S, 8x 4.7 uFd 6.3V X5R Maxim: 12x 100 uFd 4V X6S, 17x 4.7 uFd 6.3V X5R, 26x 47 uFd 6.3V X6S AVCC: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 3x 470 uFd 2V Tant_D, 8x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R, 14x 0.22 uFd 6.3V X6S, 14x 4.7 uFd 10V X5R AVTT: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 3x 470 uFd 2V Tant_D, 10x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R, 14x 0.22 uFd 6.3V X6S AVAUX: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 8x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R Recall from above adding up some power buses: --------------------------------------------- BULK_3V3 3.300 V Switch Ethernet 1.5 A Exptd 20 Amps DCDC-8 Phys Chips 0.2 A Exptd Clock Gen & Fan 0.2 A Exctd Optical Comps 0.3 A Exptd Supply Linear Regs. 1.9 A Exptd 0.6 + 0.4 + 0.9 ------------- 4.1 A Exptd SWCH_1V2 1.200 V Switch Ethernet 3.5 A Exptd 12 Amps Phys Chips 0.5 A Exptd ------------- 4.0 A Exptd BULK_1V8 1.800 V FPGA VCCAUX 147 mA qscnt 12 Amps FPGA VCCAUX_IO 2 mA qscnt FPGA VCCO 1 mA/bnk q Phys Chips 0.2 A Exptd ------------- ? A Exptd BULK_2V5 2.500 V Clocks 0.4 Optical Comps 0.9 A Exptd ------------- 1.3 A Exptd Notes about CMX and Hub Fill Generation: 15-Sept-2016 ---------------------------------------- Start of Notes from CMX First Random Try: BSPT_CORE fill on SIGNAL_8 Modify Net Type Rules for Area Fill Generation: Pin Via Trc Fil Pin 0.5 Via 0.1 0.3 Trc 0.13 0.2 0.17 Fil 0.13 0.25 0.3 0.3 <----== Modify the Setup Area Fill i.e. Setup Routing --> Area Fill Pad Isolation Shape = Polygon Tolerance = 0.01 Manufacturing Aperture Size = 0.1 Minimum Pad Sloting Threshold = 0.01 Solid Keep Islands = NO Allow Area Fill Merge = YES Ignore area fill to via clearance for same net = YES Ignore area fill to pin clearance for same net = YES Thermal Tie SMD = Thermal Tie, prefer 4, min 3, 45-135, 0.13 Pin = Flood Via = Flood In Layout: Pull Down Setup --> Shape Edit Mode ON Select the shape from the Shape Edit layer Right Click --> Change Shape to Fill: Area Fill ? vs Power Fill ? This is an Area Fill because it is on a trace layer and not on a power plane layer. Select Layer = Signal_8 Select Net = BSPT_CORE Keep all Area Fill defaults NO delete the original shape Tools and Rules Actually Used: ------------------------------ Setup Routing --> Net Type Rules Fill_to_Trace = 0.3 mm Fill_to_Fill = 0.3 mm 0.1 mm Tool requires: Fill_to_Pin = 0.13 mm Fill to Via = 0.17 mm 0.2 mm Tool requires: Fill_to_Pin = 0.25 mm Fill to Via = 0.17 mm @@ Set the Fill_to_Via = 0.20 ## During generation of the fills under the MiniPOds set Fill_to_Pin = 0.20 ** During the generation of the overall BULK_2V5 and BULK_3V3 Fills set Fill_to_Fill = 0.6 mm During Fill Generation Set: Layer = Bla Net = Foo Tool Size = 0.1 or 0.2 mm Min Slot = 0.1 mm Fill Type = Solid Thermal = SMD Pin Via Flood Flood Flood Setup Routing --> Setup Area Fill Pad Isolation Shape: Polygon Pad Isolation Tolerance: 0.005 Manufacturing Aperture Size: 0.2 Minimum Pad Slotting Threshold: 0.1 Solid Keep Islands: No Allow Area Fill Merge: Yes Ignore same net fill to via clearance: Yes Ignore same net fill to pin clearance: Yes Thermal Tie: SMD Flood Pin Flood Via Flood End of the old CMX section ===== Notes about PAL FPGA Usage: 9-Jan-2018 --------------------------- Xilinx Configuration Bit-Stream Size -------------------------------------- Rev. 9-Jan-2018 This file list the size of the "Configuration Bit-Stream" for some of the various devices that we have used in cards that were designed at MSU. The size of the Configuration Bit-Stream is assumed to be a reasonable measure of how much programmable logic is inside the PAL or FPGA device. Early MMI Programmable Logic Devices: PALs and CPALs Typical Trigger Card Device Size Bits Date -------------- ------- --------- ---- Fixed Target: TIC 16L6 800 1983 D-Zero: Run I Trig FW 16R8 2,048 1987 Run I Cal Trg 22V10 5,908 1990 Later Xilinx CPLD and FPGA Devices: XC95 CPLD, 4000, Virtex, and Ultra-Scale Trigger Card Device Size Bits Date -------------- ------ --------- ---- D-Zero: Run I Cal Trg 4002A 31,628 1994 Run II Smallest Trig FW 4013E 247,920 1997 Run II Largest Trig FW 4036XL 832,480 1997 Run IIb ADF-2 XC95144XL 124,440 2004 Run IIb ADF-2 2V1000 4,082,592 2004 HAWC: GPS MEZ-456 2V1000 4,082,592 2011 Atlas: CMX Virtex-6 LX550T 143,999.072 2013 Hub Ultra-Scale XCVU125 401,441,280 2016 Configuration Size at the D-Zero System Level: D-Zero Run II Trig FW: 791,000,000 bits This 791,000,000 number comes from: 500,000 (Average of TFW FPGA Config Size) x 1582 FPGAs and is known to be a low estimate because it does not count the 92 cards x 247,920 bits per VME IF FPGA which is an additional 22,808,640 configuration bits. The 1582 FPGA count comes from TRICS log file for just the TFW and Routing Master. D-Zero Run II Cal Trig: 653,214,720 bits This 653,214,720 number comes from: 80 ADF-2 Cards x 2 2V1000 per card x 4,082,592 per 2V1000 and is known to be a low estimate because it does not count the 80 x 124,440 for the XC95144XL CPLDs which is an additional 9,955,200 configuration bits. Notes about MGT and MiniPOD Level and Equalization: 5-Oct-2018 --------------------------------------------------- GTH Transceiver Specifications: ------------------------------- GTH Differential peak-to-peak Input 150 mV min 1250 mV max > 6.6 Gbps voltage with external AC coupling 150 mV min 2000 mV max < 6.6 Gbps GTH Differential peak-to-peak Output 800 mV min max is not specified Voltage with transmitter output swing set to 1100 which has a nominal output swing of 950 mVpp Lowest setting 0000 has nominal 170 mVpp output. Highest setting 1111 has nominal 1080 mVpp output. Recall that Xilinx defines differential peak to peak as taking the signed difference between the DIR and CMP sides of the signal and then measuring the absolute peak -to-peak value of this difference. GTH Reference Clock Input 250 mV min 2000 mV max Differential peak-to-peak GTH Reference Clock Frequency 60 MHz min 820 MHz max 200 psec edges typ 40/60 min/max duty cycle GTH Reference Clock Phase Noise Mask: with 312.5 MHz Reference Clock 10 kHz 100 kHz 1 MHz 50 MHz ------ ------- ----- ------ QPLL -105 -124 -130 -- dBc/Hz CPLL -105 -124 -130 -140 GTH Receiver Equalization: LPM mode aka Low Power Mode or DFE mode aka Decision Feedback Equalization Starts on page 189 and see especially page 203 of the GTH Transceivers book GTY Transceiver Specifications: ------------------------------- GTY Differential peak-to-peak Input 150 mV min 1250 mV max > 6.6 Gbps voltage with external AC coupling 150 mV min 2000 mV max < 6.6 Gbps GTY Differential peak-to-peak Output 800 mV min max is not specified Voltage with the transmitter output swing set to 0x1F i.e. the highest possible output with a nominal output swing of 933 mv. The lowest output swing 0x00 nominal 191 mVpp. GTY Reference Clock Input 250 mV min 2000 mV max Differential peak-to-peak GTY Reference Clock Frequency 60 MHz min 820 MHz max 200 psec edges typ 40/60 min/max duty cycle GTY Reference Clock Phase Noise Mask: with 312.5 MHz Reference Clock 10 kHz 100 kHz 1 MHz 50 MHz ------ ------- ----- ------ QPLL -103 -123 -143 -- dBc/Hz CPLL -103 -123 -143 -145 GTY Receiver Equalization: LPM mode aka Low Power Mode or DFE mode aka Decision Feedback Equalization Starts on page 197 and see especially page 210 of the GTY Transceivers book MiniPOD Receiver: ----------------- Differential Output Voltage PP 400 mV min 500 mV typ 600 mV max with Default De-emphasis Optical Modulation Amplitude (OMA) +3 max dBm Receiver Sensitivity (OMA) -11.3 min dBm Receiver Damage Threshold +4 dBm Optical Fiber Pull Force 0.98 N max long term or risk permanent damage MiniPOD Transmitter: -------------------- Differential Input Voltage 1.0 V absolute max LOS de-assertion threshold 210 mVpp max Tx Data Input Diff PP Tx data input must conform to IEEE 802.3ba-2010 TP1a electrical host compliance specification. From the TP1A eye diagram (at input to MiniPOD) I think: must see some differential signal by 0.11 UI must have at least 180 mV Diff by 0.31 UI diff input must not exceed 700 mV Note these values may be 95 and 350 mV but I do not think so. Peak power +4 max dBm each lane Average launch Power -7.6 min +2.4 max dBm each lane Launch Power in OMA minus TDP -6.5 min dBm each lane Transmitter and Dispersion Penalty 3.5 max dB each lane MiniPOD Channel Number - MPO Fiber Number: 25-Jan-2019 ------------------------------------------ This section is a description of the MiniPOD Channel numbering vs the MPO Connector Fiber numbering. MiniPOD Channels are numbered 0:11 MPO Connector Fibers are numbered 1:12 In addition, at least in the Molex Prizm to MPO Ribbon Cable Assemblies, the two numbering schemes run in opposite directions. This results in a Molex Prizm to MPO map of: MiniPOD Molex Prizm MPO Channel Fiber Number Number ------- ------- 0 12 1 11 2 10 3 9 4 8 5 7 6 6 7 5 8 4 9 3 10 2 11 1 <-- White Dot on MPO Connector - Looking at our Prizm to MPO cable, then the MiniPOD Channels run across the optical face of the MPO connector in the opposite way to normal MPO order, i.e. MiniPOD Channel #11 is on the fiber next to the MPO connector's White Dot, i.e. MPO Fiber Number 1. - This MiniPOD Channel to Molex MPO Fiber Numbering explains how the Felix light on MPO Octopus Fiber 6 connects to Hub #1 MiniPOD Receiver Channel 6. The standard pinout for an MPO connector is: - Looking at the optical face of the MPO connector with the key up and the white dot on your left-hand side. - Fiber number 1 is on the left and fiber number 12 is on the right. - The white dot is on the fiber number 1 side - just like the dot on an integrated circuit package is next to its pin 1. I verified that our Octopus cables have their individual fibers numbered according to the standard MPO scheme. I verified that our Mid-Board MPO and Front-Panel MPO feed through connectors are both "key-up key-down", i.e. Fiber #1 on one side mates with Fiber #1 on the other side. I looked at the male and female types of Prizm to MPO cables and find that they are exactly the same except for the pins on the male cables. - The ribbon fiber color order going into the Prizm connector is the same on both cable types. - The MPO white dot and key up/down alignment stuff is the same on both types of Prizm to MPO cables. - The only difference that I see is that on the male version of our Prizm to MPO cables there are pins in the MPO connector. Describe Our Hub's Molex Prizm to MPO cables: - Lay the Prizm to MPO cable on a table with the Prizm connector on your Left and the MPO connector on your Right. Look down on this cable. - Put the Optical Face of the Prizm connector Down, i.e. in the orientation so that it is ready to snap into a MiniPOD. - There is NO twist in the optical ribbon cable. - Then the MPO connector key is UP and the White Dot is on the side close to you. - By standard MPO Numbering, Fiber #1 is close to you and Fiber #12 is away from you. Implications (assuming the above is correct): - Given a MiniPOD Receiver and Transmitter, two of our Prizm to MPO cables, two "key up - key down" MPO feed through connectors, and one type A MPO Patch Cable then: The electrical signal sent into the D0 pins of the MiniPOD Transmitter will come out of the D0 pins of the MiniPOD Receiver. On its trip it will travel on fiber #12 of the MPO Patch Cable. - Given a MiniPOD Receiver or Transmitter, one of our Prizm to MPO cables, one "key up - key down" MPO feed through connector, and one of our MPO to LC Octopus cables then: MiniPOD Channel #0 will be on Octopus fiber #12. MiniPOD Channel #11 will be on Octopus fiber #1. Next Steps in understanding Prizm vs MPO Numbering: - A thing that seems strange in all the above maps is the Prizm to MPO cable. If the Prizm to MPO cable were the other way around then things would make more sense. - Is there an "official" mapping for Prizm to MPO cables ? i.e. will all Prizm to MPO cables used in the overall L1Calo have the same MiniPOD Ch # to MPO Fiber # map ? - Why is it sometimes called "Prizm" and sometimes called "VersaBeam". - Is there anything besides MiniPOD that uses Prizm / VersaBeam. ROD 4x MiniPOD Prizm to MPO Cable from Ed: 15-July-2019 ------------------------------------------ Compare the following description of the 4x ribbon cable that Ed uses on his ROD to connect his MiniPODs with the backplane MPO connector to the description of the Molex Prizm-MPO ribbon cable that we use on the Hub. Our Hub ribbon cable is described in the section "Describe Our Hub Molex Prizm to MPO cables" in the 25-Jan-2015 entry above. The Prizm to MPO fiber mapping appears to be the same. Describe Ed's 4x Prizm to MPO cables for the ROD: - Lay the 4x Prizm to MPO cable on a table with the Prizm connectors on your Left and the MPO connector on your Right. Look down on this cable. - Put the Optical Face of the Prizm connectors Down, i.e. in the orientation so that it is ready to snap into a MiniPOD. - There is NO twist in the optical ribbon cables. - Then the MPO connector key is UP and the White Dot is on the side close to you. - By standard MPO Numbering, Fiber #1 is close to you and Fiber #12 is away from you. Added notes for Ed's 4x Prizm to MPO cables: - In the stack of 4x ribbons, the longest ribbon is on top and the shortest ribbon is on the bottom. - The color of the fiber closest to you is Dark Blue. The color of the fiber furthest from you is Light Blue Aqua. At the MPO end the white dot and the Dark Blue fiber are on the same side. - Ed's cable's MPO connector does have male pins. - Ed's cable is: Complete Connect part no. M313-EMPL-48BRF-0.46m |/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\| /-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ -\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/- \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\ Standard Values: ----------------------------- 1% 5% 10% --- -- --- 100 10 10 102 105 107 110 11 113 115 118 121 12 12 124 127 130 13 133 137 140 143 147 150 15 15 154 158 162 16 165 169 174 178 182 18 18 187 191 196 200 20 205 210 215 221 22 22 226 232 237 243 24 249 255 261 267 274 27 27 280 287 294 301 30 309 316 324 332 33 33 340 348 357 365 36 374 383 392 39 39 402 412 422 432 43 442 453 464 475 47 47 487 499 511 51 523 536 549 562 56 56 576 590 604 619 62 634 649 665 681 68 68 698 715 732 750 75 768 787 806 825 82 82 845 866 887 909 91 931 953 976 |/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\| /-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/ -\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/- \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\ The following are old redundent block of notes: FMC Connectors: --------------- The "FMC" connectors are manufactured by Samtec and Molex. This is the Samtec "SeaRay" series of connectors. This is a whole series of parts and I'm not yet exactly certain which parts are "FMC" or whether the ROD Mezzanine actually will use the exact FMC part. I believe that to be FMCish that the Hub_Module will use a female connector and the ROD Mezzanine will use a male "FMC" connector. I assume that we are using the 400 pin version of these FMC connectors. This is 10 rows of 40 pins each, also called 5 rows of 80 pins each. In use I think that 1/2 of the pins are grounds so this connector can carry up to 100 differential pairs. The rows are called A,B,C,D, E,F,G,H,J,K. I think that FMC sometimes also uses an auxiliary power connector. I think that FMC connectors are sometimes called a VITA 57 Connector, i.e. project/specification #57 from the VME Trade Association. Samtec Part Number for the FMC connector that goes on the main board may be: ASP-134486-01 or SEAF-40-06.5-S-10-2-A-K or SEAF-40-06.5-S-10-2-A-K-TR-VITA57. This kind of stuff is listed at DK but not stocked. It costs in the range of $18 to $25 per connector.