Hub Work To-Do Hub Must/Should Do: In Random Order 9-Jan-2016 -------------------- 1. Last chance for anyone to ask for design changes. 2. Fix the 45 deg borders between fills on Art 5 and Art 8 under the FPGA. Generally move them East 0.50 mm. This requires editing 60 coordinates in two of the Shapes files. 3. Fix the Fill generation design rules for Fill-to-Fill in the Hi-Res areas. This design rule is currently 0.50 mm and the Shapes are designed for 0.40 mm separation. 4. Finalize Aperture Table: - Why did I need to append 4 or 5 apertures to get the Gerber plots to run without errors on Saturday ? This all worked in 19Dec2016 gerber plots. - What are the two apparently required zero diameter Thermal apertures for ? - I want to bury (aka flood) all ground via connections into the 10 Gnd Planes. How do I setup the Thermal Power apertures to do this ? Currently I'm displaying these connection as minimum wagon wheels. 5. Add "Mill Here" text to the back side silkscreen. 6. Finalize the High-Speed MGT Vias and pads for the FPGA and MegArray BGA. Currently this are NOT correct and do not match the MiniPOD or Diff Via Pair comps. Bring down to the 0.25 mm drill an minimum pad size. 7. Finalize the MegArray Ground Vias and the amount of criss-cross Ground connections to the MegArray BGA pads that do not have their own private Gnd Via. 8. The Switch Chip Solder Paste Stencil and Solder Mask layout are a mess. Currently they match the Broadcom specification - i.e. what I now understand is for a minimal cost pcb. We need a standard QFN package version of this geom. 9. The OnSemi specified Fanout chip perimeter pad to center pad spacing is too little for a workable solder mask. Move the back edge of the perimeter pad to a Solder Mask Defined layout and more the center pad close to this. This will require moving both the Top and Bottom versions of the Fanout chip goem to 4 version each of its perimeter pads, i.e. N, S, E, W. 10. The 40.08 MHz PLL differential output runs on the top layer of the PCB. Verify that this is clear of any routing on the Bottom of the PLL component. 11. Multiple runs of the Design Rule Checker. Note that this run OK on Friday in my first run of it on the Hub with default clearances for the 3 net types. There are only 3 cases of overlapping vias that need to be cleaned up. I have started a notes/log file for capturing the information from the DRC runs. Multiple runs of DRC should be made with tighter and tighter clearances to see where things fall apart, i.e. lots of places all at once or some isolated problem that can be fixed. 12. Add Ground Hash Fill under both ATCA Power Modules as their data sheets suggest for lowest noise. Will take a bit of experimentation as I have not used this part of Mentor before. 13. Add some Spare Layout SMD pads on the backside. There is very little space for this but in an emergency they could be very very useful. 14. Verify the plotting of the Mechanical Holes and comp pin Electrical Mounting Holes. A quick look at the Gerber plots from Saturday and I believe this all looks OK. 15. Edit the Top and Bottom Silkscreens to: make the 2918 Reference Designators legible add the text that we need to work with the cards, e.g. detailed labels on all jumpers 16. Make an engineering estimate as to whether or not there is enough copper in the High Current paths. What is the expected resistance in these paths and the expected Voltage drop during normal operating conditions. High Current paths include: 48V Input, 48V into ISO_12V module, all ISO_12V nets, all FPGA_CORE nets, All MGT_AVCC nets, all MGT_AVTT nets. Note that I have already duplicated all of these routes on all available layers - but no estimate has yet been made as what we should expect these Voltage Drops to be. 17. Move the Power Via Array comps from their current 0.46mm drill to either 0.50mm or 0.60mm if there is space for it. I want the bigger circumference for lower loss connection and also to separate these vias from the very specialized Advanced Differential Backplane Connector vias. I've changed my mind about this and now thing that this is worth while even if it requires another drill size. 18. Want to improve the Ground Relief on the backplane connectors and MegArray connectors for the High-Speed MGT pins. That is I want to move to an oval relief around each pin pair. The Hub design is all setup to do this - I just need to add it to this comps. 19. Generate and then seriously read through the pin number, net name, data sheet pin name list. 20. Generate the: Fills, Gerber Plots, and Through Hole Drill data. 21. Generate the Back-Drill Data. 22. Check the visual display of back-drill data. Do all categories of it make sense. Written check off list. 23. Check the Gerber files against a written check off list. 24. Check the Drill files against a written check off list. 25. Generate final version of the Bill of Materials, XY Placement data and other assembly data. 26. Final edits to the Assembly Instructions and the Base Board Description/Instructions (to match final counts and such). Hub Rational things that we Could do: In Random Order -------------------------------------- 1. Make some of the FPGA System Monitor Analog Inputs available in case we need them. 2. Connect the Ready lines from the I2C Buffers to FPGA inputs so we could see an I2C hang. 3. Add a 4th I2C Buffer/Isolator to improve the ways that we can partition the Sensor I2C Bus on the Hub Module. 4. Route out the pins that are requires to implement the Clocked version of the FPGA Configuration, i.e. provide for both Master BPI mode and Clocked Master BPI mode. 5. Add RC filtering of the Power Enable signal to the ROD, i.e. don't risk that the ROD power circuit can respond to a fast nsec glitch in the Power Enable to it. Can RC filter on Hub but actually best implemented on the ROD. 6. Route out some/more emergency access to Select I/O pins.