Hub Virtex FPGA Select I/O Usage -------------------------------------- Original Rev. 8-Dec-2015 Current Rev. 28-Dec-2016 A significant number of Select I/O signals are used on the Hub Module's UltraScale Virtex FPGA. The intent of this document is to list in a single place all of the Select I/O lines that are used on the Hub FPGA. About 183 Select I/O pins are connected in the Hub design. Notes: - Currently all Select I/O connections to the Hub FPGA are made to Banks: 65, 67, 68, 70, 71, 72, 84, and 94. - Bank 65 is used for Configuration of the FPGA from FLASH memory - Master BPI mode Configuration. Currently none of the Bank 65 Select I/O pins are used after Configuration except for the two pins that allow I2C slave access to the FPGA's System Monitor. - Banks 84 and 94 are operated with a Vcco of 3V3. The Select I/O lines from Banks 84 and 94 are used for all of the 3V3 logic connections to the Hub Virtex FPGA. - The Net List files that are used to assign Select I/O pins on the Hub FPGA are listed in the file: aa_list_of_files_with_fpga_connection.txt in the Net List sub-directory. - The only signals that are routed to Select I/O Banks: 70, 71, 72 are: the 13 Equalizer Enable signals that control the MGT Fanout equalizers (these are static low current output lines with non-critical routing), the 2 PLL Lock-Detect inputs to the FPGA which sould be static durning normal operation, the 1 "clock select" signal that controls whether or not the 40.08 MHz reference clock outputs in Zone 2 are active or not. This is a static low current output, and 3 differential clock signals inputs that use Bank 71 because it is adjacent to the clock generation chips. Bank 71 is of the HP type and is on SLR #1. These clock signals are the 40.08 MHz Logic Clock, the 320.64 MHz Logic Clock, and the 40.08 MHz Reference Clock from the Other Hub Module. - Currently there are no connections to Bank 66. The reason for this is to facilitate routing access for required configuration signals to the very deep rings on Bank 65. These configuration signals need to go 14 or 15 rings in. Except for this - Bank 66 is perfectly usable HP type Select I/O signals. Bank 66 does have Vcco power. - All banks that must handle high speed Select I/O signals have their VRP and VREF pins connected to the appripriate resistors. I have listed the reference designators of the resistors associated with these pins (instead of listing a not interesting net name). - Recall that when additional pins in these Select I/O Banks are put into service that these pins need to be removed from the ultra_no_connect_pins_nets netlist. - All of the Select I/O Banks that we are using in the Hub design come from Super Logic Region #0 in the XCVU125 stacked silicon FPGA, except for Banks 70, 71, and 72 which are part of Super Logic Region #1. Bank 65: 1V8 I/O HP SLR #0 44 Hub Connections -------- mostly Configuration BE20 IO_L24P_T3U_N10_EMCCLK_65 'NO_CONN_FPGA_BANK_65_BE20' BF20 IO_L24N_T3U_N11_DOUT_CSO_B_65 'NO_CONN_FPGA_BANK_65_BF20' BD20 IO_T3U_N12_PERSTN0_65 'NO_CONN_FPGA_BANK_65_BD20' BE16 IO_L23P_T3U_N8_I2C_SCLK_65 'HUB_I2C_TO_FPGA_SCL' BF16 IO_L23N_T3U_N9_I2C_SDA_65 'HUB_I2C_TO_FPGA_SDA' BE19 IO_L22P_T3U_N6_DBC_AD0P_D04_65 'FLASH_D04' BF19 IO_L22N_T3U_N7_DBC_AD0N_D05_65 'FLASH_D05' BD18 IO_L21P_T3L_N4_AD8P_D06_65 'FLASH_D06' BE18 IO_L21N_T3L_N5_AD8N_D07_65 'FLASH_D07' BE17 IO_L20P_T3L_N2_AD1P_D08_65 'FLASH_D08' BF17 IO_L20N_T3L_N3_AD1N_D09_65 'FLASH_D09' BD17 IO_L19P_T3L_N0_DBC_AD9P_D10_65 'FLASH_D10' BD16 IO_L19N_T3L_N1_DBC_AD9N_D11_65 'FLASH_D11' BC20 IO_L18P_T2U_N10_AD2P_D12_65 'FLASH_D12' BC19 IO_L18N_T2U_N11_AD2N_D13_65 'FLASH_D13' BA19 IO_L17P_T2U_N8_AD10P_D14_65 'FLASH_D14' BB19 IO_L17N_T2U_N9_AD10N_D15_65 'FLASH_D15' BA21 IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 'FLASH_A00' BB21 IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 'FLASH_A01' BB18 IO_L15P_T2L_N4_AD11P_A02_D18_65 'FLASH_A02' BC18 IO_L15N_T2L_N5_AD11N_A03_D19_65 'FLASH_A03' AY20 IO_L14P_T2L_N2_GC_A04_D20_65 'FLASH_A04' BA20 IO_L14N_T2L_N3_GC_A05_D21_65 'FLASH_A05' BC21 IO_T2U_N12_CSI_ADV_B_65 'NO_CONN_FPGA_BANK_65_BC21' AY19 IO_L13P_T2L_N0_GC_QBC_A06_D22_65 'FLASH_A06' AY18 IO_L13N_T2L_N1_GC_QBC_A07_D23_65 'FLASH_A07' AV20 IO_L12P_T1U_N10_GC_A08_D24_65 'FLASH_A08' AW20 IO_L12N_T1U_N11_GC_A09_D25_65 'FLASH_A09' AV19 IO_T1U_N12_PERSTN1_65 'NO_CONN_FPGA_BANK_65_AV19' AW18 IO_L11P_T1U_N8_GC_A10_D26_65 'FLASH_A10' AW17 IO_L11N_T1U_N9_GC_A11_D27_65 'FLASH_A11' AV21 IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 'FLASH_A12' AW21 IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 'FLASH_A13' AU18 IO_L9P_T1L_N4_AD12P_A14_D30_65 'FLASH_A14' AV18 IO_L9N_T1L_N5_AD12N_A15_D31_65 'FLASH_A15' AT21 IO_L8P_T1L_N2_AD5P_A16_65 'FLASH_A16' AU21 IO_L8N_T1L_N3_AD5N_A17_65 'FLASH_A17' AT19 IO_L7P_T1L_N0_QBC_AD13P_A18_65 'FLASH_A18' AU19 IO_L7N_T1L_N1_QBC_AD13N_A19_65 'FLASH_A19' AR20 IO_L6P_T0U_N10_AD6P_A20_65 'FLASH_A20' AT20 IO_L6N_T0U_N11_AD6N_A21_65 'FLASH_A21' AR19 IO_L5P_T0U_N8_AD14P_A22_65 'FLASH_A22' AR18 IO_L5N_T0U_N9_AD14N_A23_65 'FLASH_A23' AM21 IO_L4P_T0U_N6_DBC_AD7P_A24_65 'FLASH_A24' AN21 IO_L4N_T0U_N7_DBC_AD7N_A25_65 'FLASH_A25' AM19 IO_L3P_T0L_N4_AD15P_A26_65 'NO_CONN_FPGA_BANK_65_AM19' AN19 IO_L3N_T0L_N5_AD15N_A27_65 'NO_CONN_FPGA_BANK_65_AN19' AN20 IO_L2P_T0L_N2_FOE_B_65 'FLASH_OUTPUT_ENB_B' AP20 IO_L2N_T0L_N3_FWE_FCS2_B_65 'FLASH_WRITE_ENB_B' AP21 IO_T0U_N12_VRP_A28_65 R101 AN18 IO_L1P_T0L_N0_DBC_RS0_65 'NO_CONN_FPGA_BANK_65_AN18' AP18 IO_L1N_T0L_N1_DBC_RS1_65 'NO_CONN_FPGA_BANK_65_AP18' AM18 VREF_65 R106 This is a complete list of all pins in Bank 65 including 9 No_Conn_ spare unused pins. Bank 66: 1V8 I/O HP SLR #0 2 Hub Connections -------- Except for the resistor pins, no pins in Bank 66 are currently in use - all are "No_COnn_" spare not connected pins. AM27 IO_T0U_N12_VRP_66 R102 AM22 VREF_66 R107 Bank 67: 1V8 I/O HP SLR #0 27 Hub Connections -------- BE25 IO_L23P_T3U_N8_67 'OVERALL_ADRS_1_TO_RES_NET' BF25 IO_L23N_T3U_N9_67 'OVERALL_ADRS_0_TO_RES_NET' BE27 IO_L22P_T3U_N6_DBC_AD0P_67 'OVERALL_ADRS_3_TO_RES_NET' BE28 IO_L22N_T3U_N7_DBC_AD0N_67 'OVERALL_ADRS_5_TO_RES_NET' BF26 IO_L20P_T3L_N2_AD1P_67 'OVERALL_ADRS_2_TO_RES_NET' BF27 IO_L20N_T3L_N3_AD1N_67 'OVERALL_ADRS_4_TO_RES_NET' BA29 IO_L18P_T2U_N10_AD2P_67 'Hub_I2C_to_FPGA_SCL' BB29 IO_L18N_T2U_N11_AD2N_67 'Hub_I2C_to_FPGA_SDA' AW27 IO_L14P_T2L_N2_GC_67 'ROD_PRESENT_B_TO_FPGA' AW28 IO_L14N_T2L_N3_GC_67 'ROD_Power_Control_2_FPGA' BB28 IO_T2U_N12_67 'FPGA_RODs_SMBALERT_B' AY27 IO_L13P_T2L_N0_GC_QBC_67 'TBD_SPARE_LINK_2_DIR' AY28 IO_L13N_T2L_N1_GC_QBC_67 'TBD_SPARE_LINK_2_CMP' AV29 IO_L12P_T1U_N10_GC_67 'ROD_Power_Control_4_FPGA' AV30 IO_L12N_T1U_N11_GC_67 'ROD_Power_Control_3_FPGA' AU28 IO_L11P_T1U_N8_GC_67 'SPARE_OSC_TO_FPGA_DIR' AV28 IO_L11N_T1U_N9_GC_67 'SPARE_OSC_TO_FPGA_CMP' AT30 IO_L10P_T1U_N6_QBC_AD4P_67 'ACCESS_SIGNAL_1_FROM_FPGA' AT31 IO_L10N_T1U_N7_QBC_AD4N_67 'ACCESS_SIGNAL_2_FROM_FPGA' AT29 IO_L9P_T1L_N4_AD12P_67 'TBD_SPARE_LINK_3_DIR' AU29 IO_L9N_T1L_N5_AD12N_67 'TBD_SPARE_LINK_3_CMP' AT27 IO_L8P_T1L_N2_AD5P_67 'TBD_SPARE_LINK_1_DIR' AU27 IO_L8N_T1L_N3_AD5N_67 'TBD_SPARE_LINK_1_CMP' AV26 IO_L7P_T1L_N0_QBC_AD13P_67 'TBD_SPARE_LINK_0_DIR' AW26 IO_L7N_T1L_N1_QBC_AD13N_67 'TBD_SPARE_LINK_0_CMP' AP31 IO_T0U_N12_VRP_67 R103 AM28 VREF_67 R108 The remaining Bank 67 pins are not connected and are not listed here. Bank 68: 1V8 I/O HP SLR #0 41 Hub Connections -------- mostly RGMII to Phys Chips BF30 IO_L24P_T3U_N10_68 'HUB_FPGA_LED51_DRV' BF31 IO_L24N_T3U_N11_68 'HUB_FPGA_LED52_DRV' BA30 IO_T3U_N12_68 'Phys_U21_MDIO' BC31 IO_L23P_T3U_N8_68 'Phys_U21_RXD0__MODE0' BD31 IO_L23N_T3U_N9_68 'No_Conn_FPGA_BD31' BE29 IO_L22P_T3U_N6_DBC_AD0P_68 'OVERALL_ADRS_6_TO_RES_NET' BF29 IO_L22N_T3U_N7_DBC_AD0N_68 'HUB_FPGA_LED50_DRV' BA31 IO_L21P_T3L_N4_AD8P_68 'Phys_U22_INT_B' BB31 IO_L21N_T3L_N5_AD8N_68 'Phys_U21_RX_DV__CLK125_EN' BD30 IO_L20P_T3L_N2_AD1P_68 'No_Conn_FPGA_BD30' BE30 IO_L20N_T3L_N3_AD1N_68 'OVERALL_ADRS_7_TO_RES_NET' BC29 IO_L19P_T3L_N0_DBC_AD9P_68 'No_Conn_FPGA_BC29' BC30 IO_L19N_T3L_N1_DBC_AD9N_68 'Phys_U21_INT_B' BA36 IO_L18P_T2U_N10_AD2P_68 'Phys_U21_TXD0' BB36 IO_L18N_T2U_N11_AD2N_68 'Phys_U21_TXD2' BB32 IO_L17P_T2U_N8_AD10P_68 'Phys_U21_MDC' BB33 IO_L17N_T2U_N9_AD10N_68 'Phys_U21_RXD2__MODE2' BA34 IO_L16P_T2U_N6_QBC_AD3P_68 'Phys_U21_GTX_CLK' BB34 IO_L16N_T2U_N7_QBC_AD3N_68 'Phys_U21_TX_EN' AY32 IO_L15P_T2L_N4_AD11P_68 'Phys_U21_RXD1__MODE1' BA32 IO_L15N_T2L_N5_AD11N_68 'No_Conn_FPGA_BA32' AW33 IO_L14P_T2L_N2_GC_68 'Phys_U22_RX_CLK__PHYAD2' AY33 IO_L14N_T2L_N3_GC_68 'Phys_U21_RXD3__MODE3' BA35 IO_T2U_N12_68 'Phys_U21_TXD3' AY34 IO_L13P_T2L_N0_GC_QBC_68 'Phys_U22_CLK125__LED_MODE' AY35 IO_L13N_T2L_N1_GC_QBC_68 'Phys_U21_TXD1' AU33 IO_L12P_T1U_N10_GC_68 'Phys_U21_CLK125__LED_MODE' AU34 IO_L12N_T1U_N11_GC_68 'Phys_U22_TX_EN' AW32 IO_T1U_N12_68 'Phys_U22_RX_DV__CLK125_EN' AV33 IO_L11P_T1U_N8_GC_68 'Phys_U21_RX_CLK__PHYAD2' AV34 IO_L11N_T1U_N9_GC_68 'Phys_U22_RXD2__MODE2' AV36 IO_L10P_T1U_N6_QBC_AD4P_68 'Phys_U22_RXD1__MODE1' AW36 IO_L10N_T1U_N7_QBC_AD4N_68 'Phys_U22_MDC' AV35 IO_L9P_T1L_N4_AD12P_68 'Phys_U22_RXD0__MODE0' AW35 IO_L9N_T1L_N5_AD12N_68 'Phys_U22_MDIO' AU31 IO_L8P_T1L_N2_AD5P_68 'No_Conn_FPGA_AU31' AU32 IO_L8N_T1L_N3_AD5N_68 'Phys_U22_RXD3__MODE3' AV31 IO_L7P_T1L_N0_QBC_AD13P_68 'Ref_40.08_MHz_from_FPGA_to_Rec_Dir' AW31 IO_L7N_T1L_N1_QBC_AD13N_68 'Ref_40.08_MHz_from_FPGA_to_Rec_Cmp' AR36 IO_L6P_T0U_N10_AD6P_68 'Phys_U22_TXD0' AT36 IO_L6N_T0U_N11_AD6N_68 'Phys_U22_TXD1' AP33 IO_L5P_T0U_N8_AD14P_68 'No_Conn_FPGA_AP33' AR33 IO_L5N_T0U_N9_AD14N_68 'No_Conn_FPGA_AR33' AR35 IO_L4P_T0U_N6_DBC_AD7P_68 'Phys_U22_TXD2' AT35 IO_L4N_T0U_N7_DBC_AD7N_68 'Phys_U22_TXD3' AR32 IO_L3P_T0L_N4_AD15P_68 'No_Conn_FPGA_AR32' AT32 IO_L3N_T0L_N5_AD15N_68 'No_Conn_FPGA_AT32' AR34 IO_L2P_T0L_N2_68 'No_Conn_FPGA_AR34' AT34 IO_L2N_T0L_N3_68 'Phys_U22_GTX_CLK' AU36 IO_T0U_N12_VRP_68 R104 AN32 IO_L1P_T0L_N0_DBC_68 'No_Conn_FPGA_AN32' AP32 IO_L1N_T0L_N1_DBC_68 'No_Conn_FPGA_AP32' AM32 VREF_68 R109 This is a complete list of all pins in Bank 68 including 12 No_Conn_ spare unused pins. Bank 84: 3V3 I/O HR SLR #0 24 Hub Connections -------- AP17 IO_L24P_T3U_N10_84 'ROD_Power_Enable_B' AR17 IO_L24N_T3U_N11_84 'ROD_Power_Enable' AM16 IO_T3U_N12_84 'ALL_HUB_POWER_GOOD_TO_FPGA' AN15 IO_L23P_T3U_N8_84 'Trans_MiniPOD_SCL' AP15 IO_L23N_T3U_N9_84 'Trans_MiniPOD_SDA' AV16 IO_L22P_T3U_N6_DBC_AD0P_84 'FPGA_SW_C_LOOP_DETECTED' AV15 IO_L22N_T3U_N7_DBC_AD0N_84 'FPGA_SW_C_ATC_LOOP_DET' AN16 IO_L21P_T3L_N4_AD8P_84 'Trans_MiniPOD_INTR_B' AP16 IO_L21N_T3L_N5_AD8N_84 'Hubs_SMB_Alert_B' AT17 IO_L20P_T3L_N2_AD1P_84 'No_Conn_FPGA_AT17' AU17 IO_L20N_T3L_N3_AD1N_84 'No_Conn_FPGA_AU17' AT16 IO_L19P_T3L_N0_DBC_AD9P_84 'FPGA_SW_B_MDC' AU16 IO_L19N_T3L_N1_DBC_AD9N_84 'FPGA_SW_B_MDIO' AP13 IO_L18P_T2U_N10_AD2P_84 'Trans_MiniPOD_RESET_B' AR13 IO_L18N_T2U_N11_AD2N_84 'Recvr_MiniPOD_SDA' AU12 IO_L17P_T2U_N8_AD10P_84 'ISO_SLOT_HW_ADRS_2' AU11 IO_L17N_T2U_N9_AD10N_84 'ISO_SLOT_HW_ADRS_3' AR15 IO_L16P_T2U_N6_QBC_AD3P_84 'Recvr_MiniPOD_INTR_B' AR14 IO_L16N_T2U_N7_QBC_AD3N_84 'Recvr_MiniPOD_RESET_B' AR12 IO_L15P_T2L_N4_AD11P_84 'Recvr_MiniPOD_SCL' AT12 IO_L15N_T2L_N5_AD11N_84 'ISO_SLOT_HW_ADRS_0' AT15 IO_L14P_T2L_N2_GC_84 'CLOCK_25_MHz_FPGA' AT14 IO_L14N_T2L_N3_GC_84 'FPGA_SW_B_ATC_LOOP_DET' AT11 IO_T2U_N12_84 'ISO_SLOT_HW_ADRS_1' AU14 IO_L13P_T2L_N0_GC_QBC_84 'No_Conn_FPGA_AU14' AU13 IO_L13N_T2L_N1_GC_QBC_84 'FPGA_SW_B_LOOP_DETECTED' AM17 VREF_84 R111 This is a complete list of all pins in Bank 84 including 3 No_Conn_ spare unused pins. Bank 94: 3V3 I/O HR SLR #0 22 Hub Connections -------- AW13 IO_L12P_T1U_N10_GC_94 'FPGA_SW_A_MDC' AW12 IO_L12N_T1U_N11_GC_94 'ISO_SLOT_HW_ADRS_5' AY13 IO_T1U_N12_94 'FPGA_SW_C_MDC' AV14 IO_L11P_T1U_N8_GC_94 'No_Conn_FPGA_AV14' AV13 IO_L11N_T1U_N9_GC_94 'FPGA_SW_A_ATC_LOOP_DET' BA11 IO_L10P_T1U_N6_QBC_AD4P_94 'SHELF_ADRS_7_TO_FPGA' BB11 IO_L10N_T1U_N7_QBC_AD4N_94 'SHELF_ADRS_5_TO_FPGA' AY12 IO_L9P_T1L_N4_AD12P_94 'ISO_SLOT_HW_ADRS_7' BA12 IO_L9N_T1L_N5_AD12N_94 'SHELF_ADRS_6_TO_FPGA' BB13 IO_L8P_T1L_N2_AD5P_94 'SHELF_ADRS_3_TO_FPGA' BB12 IO_L8N_T1L_N3_AD5N_94 'SHELF_ADRS_4_TO_FPGA' AV11 IO_L7P_T1L_N0_QBC_AD13P_94 'ISO_SLOT_HW_ADRS_4' AW11 IO_L7N_T1L_N1_QBC_AD13N_94 'ISO_SLOT_HW_ADRS_6' AY17 IO_L6P_T0U_N10_AD6P_94 'No_Conn_FPGA_AY17' BA17 IO_L6N_T0U_N11_AD6N_94 'No_Conn_FPGA_BA17' BA14 IO_L5P_T0U_N8_AD14P_94 'SHELF_ADRS_2_TO_FPGA' BB14 IO_L5N_T0U_N9_AD14N_94 'SHELF_ADRS_1_TO_FPGA' BB17 IO_L4P_T0U_N6_DBC_AD7P_94 'No_Conn_FPGA_BB17' BB16 IO_L4N_T0U_N7_DBC_AD7N_94 'I2C_Buf_1503_ENABLE' BA16 IO_L3P_T0L_N4_AD15P_94 'I2C_Buf_1501_ENABLE' BB15 IO_L3N_T0L_N5_AD15N_94 'SHELF_ADRS_0_TO_FPGA' AW15 IO_L2P_T0L_N2_94 'FPGA_SW_A_MDIO' AY14 IO_L2N_T0L_N3_94 'FPGA_SW_C_MDIO' BC16 IO_T0U_N12_94 'No_Conn_FPGA_BC16' AY15 IO_L1P_T0L_N0_DBC_94 'FPGA_SW_A_LOOP_DETECTED' BA15 IO_L1N_T0L_N1_DBC_94 'I2C_Buf_1502_ENABLE' AW16 VREF_94 R112 This is a complete list of all pins in Bank 94 including 5 No_Conn_ spare unused pins. Bank 70: 1V8 I/O HP SLR #1 3 Connections PLL-Det, FEX Ref Clk Enb -------- B26 IO_L24P_T3U_N10_70 'PLL_320.64_MHz_Lock_Detect_to_FPGA' B27 IO_L22P_T3U_N6_DBC_AD0P_70 'PLL_40.08_MHz_Lock_Detect_to_FPGA' A26 IO_L24N_T3U_N11_70 'Select_Input_Second_40_Fanout' Only the Bank 70 signals used in the Hub design are listed. Bank 71: 1V8 I/O HP SLR #1 15 Connections Clocks and Equalizer Enb -------- B22 IO_L24N_T3U_N11_71 'MGT_FO_EQU_ENB_GRP_6' B25 IO_L23P_T3U_N8_71 'MGT_FO_EQU_ENB_GRP_3' A25 IO_L23N_T3U_N9_71 'MGT_FO_EQU_ENB_GRP_2' C25 IO_L21N_T3L_N5_AD8N_71 'MGT_FO_EQU_ENB_GRP_1' A24 IO_L20P_T3L_N2_AD1P_71 'MGT_FO_EQU_ENB_GRP_4' A23 IO_L20N_T3L_N3_AD1N_71 'MGT_FO_EQU_ENB_GRP_9' C24 IO_L19N_T3L_N1_DBC_AD9N_71 'MGT_FO_EQU_ENB_GRP_5' H23 IO_L14P_T2L_N2_GC_71 'Ref_40.08_MHz_from_Other_Hub_Dir' G23 IO_L14N_T2L_N3_GC_71 'Ref_40.08_MHz_from_Other_Hub_Cmp' J24 IO_L12P_T1U_N10_GC_71 'Logic_Clk_40.08_MHz_to_FPGA_Dir' H24 IO_L12N_T1U_N11_GC_71 '"Logic_Clk_40.08_MHz_to_FPGA_Cmp' K22 IO_L11P_T1U_N8_GC_71 'Logic_Clk_320.64_MHz_to_FPGA_Dir' J22 IO_L11N_T1U_N9_GC_71 'Logic_Clk_320.64_MHz_to_FPGA_Cmp' P22 IO_T0U_N12_VRP_71 R105 P21 VREF_71 R110 The remaining 39 pins in Bank 71 are not used in the Hub design and are not listed here. Bank 72: 1V8 I/O HP SLR #1 6 Connections Equalizer Enables -------- A18 IO_L24N_T3U_N11_72 'MGT_FO_EQU_ENB_GRP_13' A20 IO_L23P_T3U_N8_72 'MGT_FO_EQU_ENB_GRP_11' A19 IO_L23N_T3U_N9_72 'MGT_FO_EQU_ENB_GRP_12' A21 IO_L21N_T3L_N5_AD8N_72 'MGT_FO_EQU_ENB_GRP_10' D20 IO_L20P_T3L_N2_AD1P_72 'MGT_FO_EQU_ENB_GRP_7' C20 IO_L19P_T3L_N0_DBC_AD9P_72 'MGT_FO_EQU_ENB_GRP_8' Only the Bank 72 signals used in the Hub design are listed.