Hub-Module IPMC Connections -------------------------------- Original Rev. 3-Apr-2015 Current Rev. 16-Jul-2018 The Hub Module design includes a large number of connections to the IPMC mezzanine card. These connections are described in following sections of this document and are shown in Hub Circuit Diagrams: #09, #13, #14, #16, #37, #57. Additional details of the Hub Module connections to the IPMC are shown in Circuit Diagrams: #6, #24, #28, #29, #30, #30, #30_blk, #31, #31_blk, #48. IPMC Connections Shown in Drawing #13: -------------------------------------- - Backplane IPMB A and B: The IPMC is connected to the Shelf Manager by the two IPMB buses. The A and B IPMB Buses enter the Hub Module on the Zone 1 connector and have a rather long path up to near the top of the IPMC socket. These two I2C buses are routed to keep them away from noise sources as much as possible. - Slot Hardware Address: The 8 Slot Hardware Address signals allow the Hub Module's IPMC to know what slot it is in (but not what Shelf it is in in the overall L1Calo system). The Slot Hardware Address enters the Hub Module on its Zone 1 connector and is routed up to near the top of the IPMC socket. Here next to the IPMC socket are located the required pull-up resistors to the IPMC_3V3 power bus and the 100 nFd noise filter capacitors. Note that both the IPMC and the Hub's FPGA need to know the Slot Hardware Address. The backplane Slot Hardware Address is connected through isolation resistors to Select I/O input pins in a 3.3 Volt I/O Bank on the Hub's FPGA. These isolation resistors are required because the IPMC will probably ingest the Slot Hardware Address before the Hub FPGA has been powered up. In that situation these lines would be held low by the input protection diodes on the FPGA. The isolation resistors allow the IPMC to receive the correct HW Address even when the Hub's FPGA is not powered. Recall that the 8 bit Slot Hardware Address is really a 7 bit address and an Odd Parity bit. The actual addressing scheme is explained in the ATCA Specification and is a bit complicated, e.g. Physical Slot Address, Logical Slot Address, Physical Address Site Number and Site Type. - Front Panel Handle Switch: The Hub Module uses a front panel Handle Switch that is mounted in the lower front panel handle and wired to solder terminals on the Hub PCB. This Handle Switch is part of the ATCA "hot swap" scheme. The required sense of this switch is not well explained in the IPMC documentation. I believe that it should be "open circuit" when the front panel handle is fully closed and the Hub Module is latched into the Shelf. The switch wiring is up-side-down from common rational practice, i.e. the switch connects to 3V3 and uses a pull-down resistor) but it is connected as the IPMC document recommends. A 100 Ohm fire protection resistors is used in the 3V3 power connection to this switch. IPMC Connections Shown in Drawing #14: -------------------------------------- - Front Panel LEDs: The IPMC directly drives the 4 ATCA front panel LEDs. The required setup of these LEDs is not explained in the IPMC documentation. I believe that they use normal GPIO pins on their ARM uProcessor to drive these LEDs. I believe that the user needs to supply the LED series resistor but this is never explained. I believe that they are trying to drive the anode of the LED (backwards from rational practice) but this is not explained in their document. On the Hub I have connected the LED cathode pins to Ground and put the series resistor between the LED anode and the LED pin on the IPMC. - Pay Load Enable Signal: I believe that the Pay Load Enable signal goes Hi when it wants to turn ON the card. Opto-Coupler isolation is used (as required) between the IPMC and the Control pin on the Isolated +12V power supply. The cathode of the Opto-coupler LED is Grounded and its anode is tied to the IPMC's 12V_Enable pin through a 330 Ohm LED series resistor. The Opto-Coupler's LED will illuminate when the IPMC's 12V_Enable pin goes HI, and that will turn ON the Opto- Coupler's transistor and that will turn ON the Isolated +12V supply. To allow power up the Hub Module in the absence of an IPMC or on the bench in the absence of a Shelf Manager for the IPMC to talk to, I have included two jumper locations JMP5 and JMP6. Install JMP5 and remove JMP6 for normal operation controlled by the IPMC. Install JMP6 and remove JMP5 to turn ON the Hub's Isolated +12V supply all of the time. Note that the 12V_Enable signal is also routed to the Hub's power supply supervisor circuits. This signal is used both as part of the startup sequence for the Hub Module's DCDC converters and is also used during the shutdown sequence. The falling of the IPMC's 12V_Enable signal is the first indication that the Hub is going to power down. Using this signal to shutdown the Hub's DCDC converters allows then time to ramp down their outputs before the Isolated +12V power bus falls below operational threshold. - Power Entry Module Alarm: The single Alarm pin signal from the ATCA Power Entry Module is connected to the ALARM_A pin on the IPMC. This connections includes a 4.99k Ohm pull-up to IPMC_3V3. The Hub Module makes no connection to the IPMC's ALARM_B pin. - Management I2C Bus: The IPMC's Management I2C bus is connected to both the ATCA Power Entry Module and to the FRU-SDR EEPROM. The I2C bus address of the Power Entry Module is set by resistor R955 connected between its pin #10 and Ground. The IPMC documentation does not say what I2C address it expects the Power Entry Module to appear at. The FRU-SDR EEPROM is a ST Micro M24256 that is configured by its Ex pins to appear as 32k words of 8 bits at I2C address 1010000. The EEPROM's WC pin is tied Low to allow write operations. IPMC Connections Shown in Drawing #16: -------------------------------------- - Power for the IPMC: 3.3 Volt power for the IPMC is supplied by the ATCA Power Entry Module. This power bus is called IPMC_3V3 and is used only by the IPMC and the components immediately associated with it. The IPMC_3V3 bus is energized any time that the Power Entry Module receives backplane 48 Volt power. That is, as expected, the IPMC is powered even when the rest of the Hub Module is turned Off. - IPMC Ethernet Port: The Hub Module provides the Ethernet Magnetics and RJ45 connector for the IPMC. The current IPMC is a 10/100 speed only device that uses only 2 of the 4 pairs in the standard Ethernet connection. This device requires an old "current" mode type of connection to its magnetics. The Hub Module provides the required environment for the existing IPMC and can also be setup via jumpers for a 10/100/1000 speed voltage mode operation that a future IPMC would most likely require. The Ethernet connection to the IPMC is via a front panel RJ45 connector on the Hub Module. In this way the IPMC can be connected to the DCS Ethernet in a Two Hub Shelf or operated with a single Ethernet up-link in a One Hub Shelf test setup. The Ethernet Phys chip on the IPMC provides LED control signals to indicate Ethernet Link and Activity but these signals are not routed on the IPMC to its connector pins. Thus the LEDs on the Hub's RJ45 connector for the IPMC can not be functional. - Shelf Address The IPMC needs to obtain the Shelf Address of the shelf that it finds itself in from the Shelf Manager. Then the IPMC needs to make the Shelf Address available on 8 of its User I/O output pins. These IPMC User I/O pins are connected to pins on the Hub's FPGA through isolation resistors. The point of this is to send the Shelf Address to the Hub FPGA. The Hub FPGA will use a combination of this Self Address and the Slot Hardware Address to generate the Ethernet Address that it will use for its IPBus communication. A combination of the Shelf Address and the Slot Hardware Address is also sent to the ROD so that it can also generate the Ethernet Address that its FPGA will use for its IPBus communication. - JTAG Master and Slave Ports on the IPMC The Hub Module make no connection to the IPMC's master or slave JTAG ports. - Sensor I2C Bus The IPMC Senor I2C Bus is used to collect monitoring data about power supply voltages and currents and device temperatures on the ROD and Hub. The IPMC will forward this hardware monitoring information over Ethernet to the Atlas DCS system. The layout of the Sensor I2C Bus is shown in drawings #37 and #57. As shown in these drawings, three I2C bus buffer/translators are used both to drive the large number of devices on this bus, a combination of ROD and Hub devices, and also to translate between the sections of the Sensor I2C Bus that are 3V3 and the sections that are 1V8 signal level I2C bus. The buffer/translator part that is used on the Hub is the Linear Technology LTC4315. If necessary these buffer/ translators can also be used to separate the various sections of overall Sensor I2C bus under control of the Hub FPGA. At times other devices will need to initiate and master cycles on the Sensor I2C Bus, e.g. to setup parameters in the GE DCDC power converters on both the ROD and Hub modules. A User I/O input pin on the IPMC to disable its collection sweeps of monitoring data might be useful during the short and infrequent periods when other devices need to initiate and master cycles on this bus. I2C Addresses on the Hub-ROD Sensor I2C Bus: 7 Bit TI-GE Binary Decimal Octal Hex -------- ------- ----- --- ROD FPGA Master 0100 000 32 -- 20 LM82 Temp Monitor 0011 001 25 -- 19 MDT040 1V0 0011 010 26 32 1A MDT040 1V05 0011 011 27 33 1B PDT012 1V2 0011 100 28 34 1C PDT006 1V8 0011 101 29 35 1D PDT006 2V5 0011 110 30 36 1E PDT006 3V3 0011 111 31 37 1F SI5338 Clk Gen 1110 000 112 -- 70 Hub FPGA I2C Master 0110 110 54 -- 36 FPGA SysMon Slv 0111 000 56 -- 38 MDT040 FPGA_CORE 0101 000 40 50 28 UDT020 MGT_AVCC 0101 001 41 51 29 UDT020 MGT_AVTT 0101 010 42 52 2A PDT012 SWCH_1V2 0101 011 43 53 2B PDT012 BULK_1V8 0101 100 44 54 2C UDT020 FAN_1V8 0101 101 45 55 2D PDT020 BULK_3V3 0101 110 46 56 2E Notes about this Address Table: Recall that a number of I2C addresses are reserved: 0:12, 40, 44, 45, 55, 64:68, 72:75, 99, 120:127 all in decimal. I2C addresses are only 7 bits long (not 8 bits). The MSB of the I2C address of the GE/TI converters must be zero. TI-GE Octal means take the 6 least significant address binary bits and represent them as 2 octal digits, i.e. the setup of the address programming resistors on the TPS40400. Decimal means take the whole 7 bit I2C address and represent it as a decimal number.