Non-MGT Rod-Hub Connections ------------------------------- Initial Rev. 4-Mar-2015 Current Rev. 1-Dec-2016 The intent of this note is to describe all of the non-MGT ROD-Hub connection signals. The Meg-Array pinout of these signals is presented in Ed's document, "ROD Hub Pinout" Rev. 1.4 from 6-May-2015. JTAG: ----- The Hub Module provides a front panel "Access" connector". One of the functions available on this J2 access connector is a JTAG string that runs to components on both the ROD and Hub. On the ROD this JTAG string connects only to the ROD's FPGA. On the Hub this JTAG string connects only to the Hub's FPGA. This JTAG string is not connected to either the IPMC's "Master" or "Slave" JTAG ports. Manually installed jumpers are provided so that the JTAG string can be jumpered around the Hub's FPGA. An automatic jumper is provided so that this JTAG string jumpers around the ROD when the ROD Power Good signal is not asserted. The JTAG signal level at the Hub's front panel is 3V3 CMOS. The front panel pinout is standard for Xilinx signal/ground pair type of JTAG wiring and includes a fused 3V3 reference. On the Hub Module the JTAG signals are buffered and translated to 1V8 levels. The JTAG signal level to the ROD is 1.8 Volt. The Hub Module JTAG String is shown in drawing #33. Sensor I2C Bus: --------------- The I2C Bus connection to the ROD is normally mastered by the IPMC's Sensor I2C port. The normal function of the Sensor I2C bus is to allow collection of monitoring information (e.g. power supply voltages and currents and device temperatures). The IPMC initiates and masters the Sensor I2C Bus cycles that collect this monitoring data. The Sensor I2C bus from the IPMC is shared by the ROD and the Hub and is used to collect the Atlas DCS monitoring information from both of them. At times either the Hub or ROD FPGA may need to initiate and master a Sensor I2C Bus cycle for example to set a parameter in one of their GE power supplies. Thus not only sensors and GE power modules are connected to the Sensor I2C Bus but also both the Hub and ROD FPGAs make a master connection to this bus. In addition the Hub's FPGA makes a second slave only connection to the Sensor I2C Bus that provides a port to the System Monitor in the Hub's FPGA. The I2C addresses are shared between the Hub and ROD on this IPMC Sensor I2C Bus. Some parts of the overall Sensor I2C bus are 3V3 level and some parts are 1V8 level. The Hub Module provides the required translation and uses buffered translator chips, to provide the required drive for the large number of devices that are connected to the Sensor I2C Bus. These translators can have their ports enabled or disables under control of the Hub's FPGA. The Hub's Sensor I2C Bus is shown in drawing #37. Note that the Sensor I2C Bus can also be accessed from the front panel of the Hub Module via its J2 "Access Connector". The ROD-Hub Sensor I2C bus has the potential problem that when a section of it is either powered off or has a power supply problem, that the the ESD diodes in the devices in that section of the bus may clamp the I2C signals to ground. Comments on this potential problem: - We really only need monitoring information when the ROD Hub are up and running so a brief lack of monitoring data at the start of a normal power up is probably OK. - It would be very useful the IPMC could report in its monitoring data when the Sensor I2C cycles are not working vs just sending junk data or no data to the DCS monitoring system. - The Linear Technology I2C bus translators/buffers may automatically isolate stuck sections of the Sensor I2C bus and allow good monitoring data to be read from the sections of the bus that are fully powered up. - It may be useful to run the Ready signals from the I2C bus translators/buffers back to the Hub FPGA so that it can see if a section of the Sensor I2C bus is stuck. ROD Front Panel Signals: ------------------------ The ROD provides a total of 8 front panel control signals. The net-names of these signals, both old and new netnames are shown in the table below. - Drawing #50 shows the resources on the Hub that are connected to these 8 front panel control signals from the ROD. - Two of these front panel signals control the two LEDs in the RJ45 connector for the ROD. - One of these front panel signals is the input to the LEMO driver and thus controls the output of the ROD's LEMO connector on the Hub's front panel. - Five of these front panel signals control five of the LEDs on the Hub's front panel. - All 7 of the front panel control signals from the ROD that control LEDs are Low active 1V8 logic signals. When these signals are voltage Low the LED illuminates. - The one front panel control signal from the ROD that controls the LEMO output is also a 1V8 logic signal. When this control signal is voltage Low the open drain LEMO output pulls Low. - All of these front panel signals from the ROD are 1V8 CMOS level, i.e. they do not directly drive the LEDs. - Front panel signal table: MegArray Old New LED S1 Pin# Name Current Name Color -------- ------ ---------------- ------ B1 LED-0 Phy_LED2_B Green B2 LED-Y Phy_LED1_B Yellow B3 LED-B Prog_Done_LED_B Green B4 LEMO-0 LEMO -- C1 LED-1 Pwr_Good_LED_B Green C2 LED-R SMB_Alert_LED_B RED C3 LED-G GP_LED_B Blue C4 LEMO-1 Run_LED_B Blue - GP_LED_B is a General Purpose LED which can be used by firmware to signal some condition (TBD) - "The Run_LED_B is the "Up and Running" signal that you had proposed a while back.   It indicates to the Hub and to the Front Panel that the ROD is running a functional firmware image. This will not be turned on if the ROD is running an initialization, error recovery, or other engineering image. My configuration sequence is to always boot an engineering image first.  That image will check to see the board context, and will then trigger the boot of the appropriate "RUN" image.     I've allowed for the ROD to carry several images for [efex, gfex, jfex * hub1, hub2] + the engineering image = 7 configuration images.  I will turn on "Run" when the second image has booted." Clock 40.08 MHz ---------------- This is a clock signal from the Hub to the ROD. This 40.08 MHz clock is always running - even when the Hub is not receiving an Optical Timing reference signal from the LHC. This is an LVDS signal. It is AC coupled on the Hub before being sent to the ROD. It is synchronous with the Clock signal that the Hub sends to the other 12 FEX slots in the ATCA Shelf. Geographic Address: ------------------- These 8 lines are 1V8 signals from the Hub to the ROD. The net-names of these signals are: LOC_ADD1:LOC_ADD8. These signals indicate a unique Geographic Address within the overall L1Calo system. That is, these lines indicate both a Slot Number and a Shelf Number within the overall L1Calo system. These lines are not just the backplane Geographic Address signals from the ATCA Zone 1 connector. The details of how the Hub obtains the Shelf Number and encodes the Shelf Nmbr + Slot Nmbr before sending it to the ROD on these 8 lines are currently being discussed with Ian and David. Ethernet Connection: -------------------- These 8 lines come from the Micrel KSZ9031RNX Phys chip on the ROD. The net-names of these signals are: TR01_P, TR01_N, through TR04_P, TR04_N. The Hub provides the "magnetics" and the RJ45 connector for the ROD's Base Interface Ethernet connection. The components on the Hub are specified for 10/100/1000 Base-T operation. The components currently in the Hub design are Pulse Engineering HX5201NL magnetics and TE Connectivity 1888653-x connectors. The colors of the LEDs in the RJ45 connector are Green and Yellow. Careful attention must be paid while routing the Hub to confirm that it correctly implements the polarity of the Ethernet signals coming from the ROD. Module_Present: --------------- This ROD_PRSNT_B signal is pulled to Ground with a 1k Ohm resistor on the ROD. The Hub has a high value pull-up resistors on this signal. The resulting logic signal goes Low when the ROD is plugged in. This signal can be used to let the Hub FPGA know if a ROD mezzanine card is installed. ROD-Hub Power Control Signals: ------------------------------ All 4 of the Power Control Signals are 1V8 CMOS level logic signals. These are single ended signals and the direction of each of them is given below. OK for ROD to Power Up: --- Net PWR_CON1 This is a signal from the Hub to the ROD that tells the ROD when everything on the HUB has been brought up and is running. By using this signal the ROD can delay its power up until the Hub is fully running and presenting a stable environment to the ROD. The ROD includes a 1k Ohm pull-down resistor on this signal. Before telling the ROD to power up the Hub will have configured its FPGA and will have all clocks running. It will take several (many) seconds from the time that the Shelf Manager gives the Hub the OK to power up until the Hub gives the ROD the OK to power up. During an overall power up sequence, once the Hub asserts the PWR_CON1 signal voltage Hi it will not return this signal Low until the Shelf Manager tells the Hub to turn off or the backplane 48V goes away or a process is started to re-power-up the ROD. ROD Power Supplies Are All Running OK: --- Net PWR_CON2 This is a signal from the ROD to the Hub. As soon as the ROD has all of its power supplies up and running with their outputs within the required voltage range then it will assert this signal. The Hub will not "believe or use" any other signals that it receives from the ROD until this signal is asserted. ROD Has Completed Its Power Up: --- Net PWR_CON3 This is a signal from the ROD to the Hub. This signal means that the ROD is fully Configured and ready for normal L1Cal Trigger operation. The Hub will not indicate to any other cards that it is ready to operate in the overall L1Calo system until this signal from the ROD is asserted. Spare Power Control Signal: --- Net PWR_CON4 The spare Power Control signal will be routed to Select I/O pins on both the ROD and Hub FPGAs. PWR_CON signals 2, 3, and 4 all run directly between the ROD and Hub FPGAs. The Hub includes 470 Ohm "isolation" resistors in these line to limit current flow before both FPGAs are both powered up and configured. Spare Unused ROD-Hub HP IO Signals: ----------------------------------- We have a number of spare currently un-assigned signals between the ROD and the Hub. All of these signals are FPGA to FPGA HP IO lines. - There are 8 spare HP IO lines in the Meg-Array pinout list. These are nicely setup as 4 LVDS pairs so that we can use them as LVDS or as single-ended signals, which ever may be required in the future. - The net-names of these spare signals are: TBD_LINK0_P, TBD_LINK0_N, through TBD_LINK3_P, TBD_LINK3_N. - Both ROD and Hub have routed these 8 signals as 4 differential pairs. - When not used for some function, these 8 spare signals are to be operated with 1.8V single ended CMOS levels with the Hub driving and the ROD receiving. The Hub is required to tri-state its output drives for these signals any time that the ROD's Power Control #2 signal is NOT asserted HI. That is, the Hub will only drive these signals when the ROD reports that it is fully powered up. In any case, in this stand by service the Hub should use a low level of Drive current on these lines. - In firmware, these unused spare HP IO lines between the ROD and Hub will be connected to IPBus visible registers so that we may test them to prove that they are OK, i.e. prove that our lifeboat floats. Power from the Hub to the ROD: ------------------------------ The Hub provides bulk +12 Volt power to the ROD that is isolated from the backplane 48 Volt power feed.. This power is the same Isolated +12V bus that feeds all of the DC/DC Converters on the Hub module itself. The ROD may draw up to 100 Watts of this bulk +12V power, i.e. 8.3 Amps. This +12V power is sent to the ROD as soon as the Shelf Manager tells the Hub that it may power up. The current parts in the Hub design that provide the bulk Isolated +12V power are: SynQor IQ65033QMA10SNF-G power entry module and SynQor PQ60120QEA25NNS-G Isolated +12V supply. Note that the Isolated +12V supply module has a maximum capacitive load of 12,000 uFd that it can support when fully loaded with a resistive load. The Hub itself places 3118 uFd on the output of the Isolated +12V converter or about 26% of the assumed total available budget. ROD-Hub MGT Signals: -------------------- Not covered in this note.