Hub Module PCB Layer Strategy ---------------------------------- Original Rev. 17-Mar-2015 Current Rev. 26-Sep-2016 The intent of this document is to describe the "layers" in the Hub Module circuit board. The word "layer" means different things to different people, e.g. - Physical layers in the actual pcb stackup copper and dielectric - Mentor design Logical layers - Thinking about just the Signal Trace layers in either physical pcb or in the Mentor design - "Artwork" File for each Layer - Recall that a Physical Layer may be used for example as a signal trace layer in one part of the Hub PCB and as a power plane in another area of the card. Considerations in the Hub Module PCB Layer Strategy: ---------------------------------------------------- This section describes the some of the points that drove the design of the Hub Module PCB Layers: - It's clear that we need 4 layers for 100 Ohm Diff Pair traces at the bottom of the stack. This is needed because it is the cleanest way (basically only way) to connect to the Zone 2 ADFplus connectors that require a long section of their press fit pin holes to be plated. - Routing out of the MGT Fanout we need at least 4 layers to run up to the MegArray connectors and at least 4 layers to run to the Hub's FPGA. - Both for routing needs and to keep the PCB "balanced" to facilitate bare board manufacturing, it makes sense to have the second set of 4 layers of 100 Ohm Diff Pair traces at the top of the stack. - Note that using the top and bottom signal layers as 100 Ohm diff pair layers for the high speed signals means that some of these "long" high speed runs are strip-line and some are micro-strip. Some folks do not like "long" micro-strip high speed runs on the PCB surface. - This gives for the top and bottom sections of the stackup: L1 Trace 100 Ohm Diff Microstrip L2 Ground L3 Trace 100 Ohm Diff Stripline L4 Ground L5 Trace 100 Ohm Diff Stripline L6 Ground L7 Trace 100 Ohm Diff Stripline L8:L15 Power Distribution Layers and Grounds. L16 Trace 100 Ohm Diff Stripline L17 Ground L18 Trace 100 Ohm Diff Stripline L19 Ground L20 Trace 100 Ohm Diff Stripline L21 Ground L22 Trace 100 Ohm Diff Microstrip Note that Ground plane L8 is not included in the top sub-assembly and that Ground plane L15 is not included in the bottom sub-assembly. The point of this is to terminate the upper blind vias with pads on L7 and terminate the lower blind vias with pads on L16. Specifically we do not have to terminate the blind vias with pads in either L8 or L15. - Can one prove that topologically 8 layers of Diff Pairs is enough to route this card. In fact one can prove that 8 high speed diff pair layers is NOT enough because we also need to run the FEX card Clock lines and the FEX card Combined Data lines to the backplane Zone 2 connectors and they must run right under the MGT Fanout area. This requires a minimum of 10 high quality diff pair layers. But even that is NOT enough because within the MGT Fanout array we also need to route the Equalizer Enable lines to groups of 6 between the NB7VQ14M chips and Hub's Virtex FPGA. These Equalizer Enable traces are low current and DC speed so they can be thread through rest of the traces as necessary just so long as they do not cause problems for the high speed lines. - For the high speed signals it is clear that the PCB needs Blind Vias that run through either just L1-L7 or through just L16-L22. But I think that for PCB manufacturing they *may* need the Blind Vias to run just L1-L8 and just L15-L22 with pads on both extreme layers. - To provide relief around high speed Blind Diff Pairs and to close up the Ground plane on the other side of the PCB, some complicated Set of Ground Plane designs are needed. The current setup is: - a very top layer or two ground plane that closes on the lower blind vias - mid section, i.e. for all but the top and bottom layer or two that is open for all blind vias - a very bottom layer or two ground plane that closes on the upper blind vias. - These 3 or more ground plane designs are driven from one Ground plane in the Mentor design and then specialized by technology files for each application during gerber file generation. - How many Power Distribution layers are needed under the Hub's FPGA ? 6 if Brute Force: VCCINT, VCCBRAM 1V0 VCCO HP, VCCAUX, VCCAUX_IO 1V8 VCCO HR 3V3 GTH_AVCC 1V0 GTH_AVTT 1V2 GTH_AVAUX 1V8 4 is a possible minimum This requires feeding: VCCINT, VCCBRAM 1V0 only on a center West-East finger under the chip on both of the center of the board high current layers VCCO HP, VCCAUX, VCCAUX_IO 1V8 under all of the chip on the BULK_1V8 fill layer VCCO HR 3V3 under just the West side Banks 84 and 94 area of the chip on the BULK_3V3 fill layer GTH_AVCC 1V0 under just the North and South MGT areas running East-West on the Upper center of the board high current layer GTH_AVTT 1V2 under just the North and South MGT areas running East-West on the Lower center of the board high current layer GTH_AVAUX 1V8 under just the North and South MGT areas running East-West on the BULK_3V3 fill layer This description has the FPGA's pin A1 in the NE corner with the FPGA_CORE feed coming in from the West and the 3 MGT feeds coming in from the East. - There are a number of other power rails that need to be distributed on power planes / fills: BULK_3V3 BULK_2V5 Fan_1V8 BULK_1V8 SWCH_1V2 Isolated_12V 4x Isolated fills for MiniPODs: 3V3 and 2V5 3x Isolated fills for Clocks: 3V3 and 2V5 4x Backplane -48V power and returns 80V Hold Up - All of the power distribution needs to be done as fills. In areas where a given fill layer is not needed for power distribution we absolutely need to use it for trace routing, e.g. to reach Zone 2. - Draft Power Center Stackup Section: L8 Ground L9 Power Fill Layer nominally BULK_1V8 L10 Ground L11 Power Fill Layer nominally FPGA_CORE and MGT_AVCC L12 Power Fill Layer nominally FPGA_CORE and MGT_AVTT L13 Ground L14 Power Fill Layer nominally BULK_3V3 L15 Ground L11 and L12 are the high current 1 oz layers to support the FPGA_CORE supply. Another major user of L11 and L12 is the high current FAN_1V8 fill. Note that the rather high current MGT AVCC and AVTT fills use only a single 1 oz layer, i.e. either L11 or L12. Note that L11 and L12 have ground plane on only one side of them. This is were the center of the board is made symmetric and we end up with an even number of layers. The very center is not copper. L9 and L14 are used for 100 Ohm Diff Pair in places where they are not needed for power. Considerations in the Hub Module PCB Layer Strategy: ---------------------------------------------------- This section describes the actual PCB Layers used in the Hub Module and how the Mentor Design is setup to handle them. PCB Mentor Stackup Logical Layer Type and Layer Layer Usage in the Hub PCB ------- --------- --------------------------------- L1 Signal_1 Diff Pair - High Speed \ | L2 Power_1 GND Plane - Upper Type | | L3 Signal_2 Diff Pair - High Speed | | Upper L4 Power_1 GND Plane - Upper Type | Sub- | Assembly L5 Signal_3 Diff Pair - High Speed | | L6 Power_1 GND Plane - Middle Type | | L7 Signal_4 Diff Pair - High Speed / L8 Power_1 GND Plane - Middle Type \ | L9 Signal_5 Power Fills & Diff Pair | | L10 Power_1 GND Plane - Middle Type | | L11 Signal_11 Power Fills 1 oz | Middle | Sub- L12 Signal_12 Power Fills 1 oz | Assembly | L13 Power_1 GND Plane - Middle Type | | L14 Signal_6 Power Fills & Diff Pair | | L15 Power_1 GND Plane - Middle Type / L16 Signal_7 Diff Pair - High Speed \ | L17 Power_1 GND Plane - Middle Type | | L18 Signal_8 Diff Pair - High Speed | | Lower L19 Power_1 GND Plane - Lower Type | Sub- | Assembly L20 Signal_9 Diff Pair - High Speed | | L21 Power_1 GND Plane - Lower Type | | L22 Signal_10 Diff Pair - High Speed / Setup Mentor in the following way: Mentor Mentor Physical Logical Layer Layer Contents ----------- --------- ---------------------------- PAD_1 & PHYSICAL_1 SIGNAL_1 Stackup L1 Diff Pair HS PHYSICAL_2 SIGNAL_2 Stackup L3 Diff Pair HS PHYSICAL_3 SIGNAL_3 Stackup L5 Diff Pair HS PHYSICAL_4 SIGNAL_4 Stackup L7 Diff Pair HS PHYSICAL_5 SIGNAL_5 Stackup L9 Pow Fill & Diff Pair PHYSICAL_6 SIGNAL_11 Stackup L11 Power Fills PHYSICAL_7 POWER_1 Source of all GND Planes PHYSICAL_8 SIGNAL_12 Stackup L12 Power Fills PHYSICAL_9 SIGNAL_6 Stackup L14 Pow Fill & Diff Pair PHYSICAL_10 SIGNAL_7 Stackup L16 Diff Pair HS PHYSICAL_11 SIGNAL_8 Stackup L18 Diff Pair HS PHYSICAL_12 SIGNAL_9 Stackup L20 Diff Pair HS PHYSICAL_13 SIGNAL_10 Stackup L22 Diff Pair HS & PAD_2 - With only one Ground Plane in the Mentor Design, the various versions of the PCB Ground Plane are generated at Gerber Plot time by: including different Mentor Logical Layers in the definition of the ground plot, by using different Aperture Tables, and by using different Tech.Tech files where that is useful. Recall that it is the Tech.Tech file that describes the blind vias, i.e. what layers a given blind via geometry actually goes through. In general we do not route any traces above / below blind vias because basically all of our blind vias are for high speed signals and thus need the relief from copper that would shift their impedance. In this way we delay the choice of blind vias or back drilling in the design. The different tech.tech files let us shift the definition of a given blind via geometry, e.g. to generate the different types of ground planes and different drill files. Cutouts in Ground Planes and Power Fills: ----------------------------------------- To control trace impedance we need to have "cutouts" around differential via pairs and under the GTH DC Blocking Capacitors. These cutouts need to be in both the Ground Planes and in the Power Fills. Typically the cutouts go through all PCB layers of Power Fills because all Power Fill layers are near the center of the PCB. Typically the cutouts go through only some of the Ground Plane PCB layers and are allowed to "close" on the far surface of the PCB from a DC Blocking Cap or blind via pair. As before the Ground Plane cutouts are implemented as patterns on there of the PREPREG layers: - PREPREG_1 cuts out the Ground Plane near the top side of the PCB but allows it to close on the bottom side. Thus for example PREPREG_1 is used in DC Blocking caps that are placed on the top side of the PCB. - PREPREG_2 cuts out the Ground Plane near the bottom side of the PCB but allows it to close on the top side. Thus for example PREPREG_2 is be used in DC Blocking caps that are placed on the bottom side of the PCB. - PREPREG_3 cuts out the Ground Plane on all PCB Ground Plane layers. Thus for example PREPREG_3 is used for ground relief around a high speed differential pair that goes the whole way through the PCB. Cutouts in the Power fills are implemented by either including an explicit fill keep-out or by the design rules that are used to generate the fill. This is one of the reasons that Hub used special separate design rules for different types of signals, e.g. for the high speed differential signals. Many/most of the high speed differential signal via pairs are implemented as a 4 pin component in the design and thus automatically include their ground return vias and the ground plane relief around the diff signal pair.