KSZ9031RNX Phys Chip Usage on the Hub Module ----------------------------------------------- Original Rev. 12-Mar-2015 Current Rev. 21-Apr-2016 The Hub Module requires 2 Phys Chips for the Ethernet Base Interface connections to its UltraScale Virtex FPGA. Two Micrel (now Microchip Technology) KSZ9031RNX Phys chips are used to implement these Ethernet connection. An advantage of this part is that it can operate with a 1.8V RGMII port and thus directly connect to the Virtex HP I/O pins. The documentation for this Micrel part looks good and its implementation looks clean. Two drawings show the implementation of the Micrel Phys chips on the Hub Module, drawings #34 and #35. KSZ9031RNX Power Supply, ByPass, Power Up, and Reset Requirements: ---------------------------------- In the Hub application the KSZ9031RNX Phys chip requires 3 supply buses: 1.2V supply for: AVDDL the Analog Core DVDDL the Digital Core AVDD_PLL Internal PLL 1.8V supply for: DVDDH the Digital I/Os this bus can be: 1.8V, 2.5V, or 3.3V 3.3V supply for: AVDDH Transceiver Analog Power The total load on each of these 3 power buses is expected to be the following, per chip, recall that Hub has 2 chips: 1.2V supply 265 mA for Cores and PLL 1.8V supply 65 mA for Digital I/Os 3.3V supply 82 mA for Transceivers The Micrel data sheet gives a +-5% tolerance on all of this chip's supply rails. Note that the KSZ9031RNX includes a "controller" for an external MOSFET pass transistor so that by itself it can generate the 1.2V bus from the 3.3V bus if the application requires that function. The Hub Module provide all 3 buses from external supplies. Total Power Consumption with 1.8 V digital IO and 3.3 V Transceiver supply and 100% utilization at 1000 Base-T is expected to be about 706 mW per chip. ByPass and Filter Components recommended for the KSZ9031RNX: AVDDL Bus: Next to pins 4, 9 bypass with 100 nFd on each pin. Also include one or two 10 uFd and a 1 uFd on the AVDDL bus. DVDDL Bus: Next to pins 14, 18, 23, 26, 30, 39 bypass with 100 nFd on each pin. Also include a 10 uFd and use a Ferrite Bead to isolate the DVDDL bus. AVDDL_PPL Bus: Next to pin 44 bypass with 100 nFd. Also include a 10 uFd and use a Ferrite Bead to isolate the AVDDL_PLL bus. DVDDH Bus: Pins 16, 34, 40 AVDDH Bus: Pins 1, 12 Ground: Pins 29 and the exposed thermal pad pin 49 All capacitors are X5R or X7R ceramic. All ferrite beads are <0.1 Ohm DC and >60 Ohm at 100 MHz e.g. TDK MPZ1005S600C This list of Bypass and Filter requirements for the KSZ9031RNX about matches the schematic of the Micrel Eval Brd for this chip. The Mircel Eval Brd uses chokes (ferrite beads) on all 5 supply rails to the chip. They use: Steward HI1206N101R-00 on all rails. These are: 100 Ohm at 100 MHz, 144 Ohm at 500 MHz and 150 Ohm at 1 Ghz with 35 mOhm of DC resistance and 3 Amp max. Because of space limitation on the Hub module I think that we can use the smaller Wurth 782633601 0603 size chokes on 4 of these 5 power rails. The Wurth 782633601 has better AC filtering characteristic, a 1 Amp max, but has 200 mOhm max DC resistance. This should be OK for the: AVDDL, AVDDL_PLL, DVDDH, and AVDDH rails. None of these supplies can be over 100 mA and thus the maximum drop with the Wurth 782633601 choke is about 20 mV or about 1.6% on the lowest 1.2 Volt rails. I expect the current draws to be less than 100 mA, and it's possible to measure them on a running card and replace these parts if necessary so I think that this is OK. I believe that most of the current for this chip is on its DVDDL rail, probably about 225 mA so for that I will use the lower DC resistance (60 mOhm) Wurth 742792116. See pages 40 and 65 in the ver 2.2 datasheet for this chip for details about the expected current requirements. Particular Concerns from the Micrel documentation: - Because the AVDDH bus powers the transceiver output drivers, noise on this bus directly becomes noise on the transceiver output signal. - Noise on the AVDDL directly effects the receiver section of the transceivers. - Noise on the AVDDL_PLL causes jitter in the sampling point on the incoming signal. Power Up Sequence: - Basically the KSZ9031RNX wants its Cores to power up last. - Recommended power up sequence is to have the transceiver AVDDH and the digital I/O DVDDH voltages power up before the 1.2V buses to DVDDL, AVDDL, AVDDL_PLL. - There is no required sequence between the transceiver AVDDH and the digital I/O DVDDH. - The power up waveforms need to be monotonic for all power buses to the KSZ9031RNX. - After de-assertion of the RESET wait 100 usec before starting to use the part. - At power down it is best to remove the 1.2 V supply first. - For a power down cycle all buses must be less than 0.4V for at least 150 msec. - All power buses must be stable for at least 10 msec before de-assertion of the Reset signal. - All supply voltages must have a minimum of 200 usec ramp up time and have monotonic ramp. - The recommended Reset circuit, on page 75 of the data sheet is a combination of the typical R, C, Diode to guarantee a Reset at power up and another Diode to mix in an External Reset from a CPU or FPGA. RGMII Interface Port: --------------------- The RGMII port on the KSZ9031RNX is its data connection with the Hub's UltraScale Virtex FPGA. The KSZ9031RNX RGMII connects to HP I/O pins on the FPGA. The RGMII bus consists of 12 signals: Transmit Clock to the KSZ9031RNX Transmit Control (enable) to the KSZ9031RNX Transmit Data 0:3 to the KSZ9031RNX Receive Clock from the KSZ9031RNX Receive Control (enable) from the KSZ9031RNX Receive Data 0:3 from the KSZ9031RNX MDC/MIIM/MDIO Interface Port: ----------------------------- The KSZ9031RNX includes a MII Management port. This type of port is also called MDIO Management Data Input/Output. This port allows higher level devices to monitor and control the KSZ9031RNX. This port allows direct access to the IEEE defined MIIM registers, and the vendor specific registers. This port also allows indirect access to the MMD address space and registers. This port consists of signals: MDC the clock MDIO the data line The MAC in the FPGA provides the connections to this device management port. Jumpers for the KSZ9031RNX aka Strapping Pins: ----------------------------------------------- The KSZ9031RNX uses a number of jumpers that are "read" during its power up process and then the state of these jumpers control its operation of the chip once power up is completed. Most of these jumpers are the new standard type of jumper, i.e. a weak pull-up or weak pull-down on a dual purpose I/O pin. Once the jumper is "read" and the KSZ9031RNX completes its power up then the pin begins its normal function and the weak pull resistor is ignored. T For this chip the pull-up resistors connect to the DVDDH 1V8 rail. Pin Strap Normal No. Pin Name Function Jumper Function - Strapping Option --- -------- -------- --------------------------------------------- 17 PHYAD0 LED1 Pull-Up = 1 Pull-Down = 0 15 PHYAD1 LED2 PHY Address Bits 3 and 4 35 PHYAD2 RX_CLK are always 0,0 This is the PHYAD of the Management Interface port on the KSZ9031RNX. 32 MODE0 RXD0 Set operating Mode at Power Up 31 MODE1 RXD1 0100 NAND tree mode 28 MODE2 RXD2 1100 RGMII 1000 Base-T full duplex 27 MODE3 RXD3 1101 RGMII 1000 Base-T full or half duplex 1110 RGMII 10/100/100 all but 1000 half duplex 1111 RGMII 10/100/1000 full or half duplex 33 CLK125_EN RX_DV Pull-Up --> Enable the 125 MHz Clk Output Pull-Down --> Disable the 125 MHz Clk Output 41 LED_MODE CLK125 Pull-Up --> Single LED Mode _NDO Pull-Down --> 3 color or dual LED Mode KSZ9031RNX Jumpers implemented on the Hub Module: Pins 15, 17, 35 PHYAD Pull-Up and Pull-Down R1901:R1906 Pins 27, 28 MODE Pull-Up Only R1907,R1908 Pins 31, 32 MODE Pull-Up and Pull-Down R1909:R1912 Pin 33, CLK125_EN, Pull-Up Only --> Enable the 125 MHz Clk to the MAC Pin 41, LED_MODE, Pull-Up Only --> Single LED Mode R1913,R1914 Note that the Pull-Down resistors are 1k Ohm and the Pull-Up resistors are 10k Ohm. Note that some of these Pull-Up / Pull-Down resistors are on high-speed RGMII lines. They must be placed and routed with minimum parasitic effect on the high-speed signals. KSZ9031RNX LEDs: ---------------- The Hub Module runs the KSZ9031RNX LEDs in "Single LED Mode". That is it does not use tri-color or multiple LEDs per LED pin on the chip. With a 1V8 DVDDH rail I do not think that the chip can drive the LEDs directly. Rather the standard, 74AVCH8T245 non-inverting Hub circuit for controlling LEDs with 1V8 CMOS logic signals is used for the Phys chip LEDs. KSZ9031RNX ISET Resistor: ------------------------- ISET pin #48 requires a 12.1k Ohm 1% resistor to ground to set the transmitter output level. This is resistor R1915. KSZ9031RNX RESET Circuit: ------------------------- The KSZ9031RNX Phys Chips receive a reset signal from the Hub's Board Startup Reset circuits. Currently it is not understood if we want to or should provide the Phys Chips with a reset from the Hub's FPGA that would be controlled from a bit in an IPBus visible register. KSZ9031RNX Clocks: ------------------ The KSZ9031RNX contains an internal oscillator circuit for use with a 25 MHz crystal or it can use an external clock. Be sure to use the version 2.2 or later data sheet for this Phys chip to correctly understand its clock signal requirements. The Hub supplies the KSZ9031RNX with a quality external 25 MHz 3V3 clock signal. This external clock is sent into "X1" pin #46. Pin "X0" pin #45 is not connected. Internally the KSZ9031RNX manipulates this 25 MHz clock as required to sequence its various functions. One step to to multiply this up to 125 MHz. The internally generated 125 MHz clock is made available on pin CLK125 pin #41 for use by the MAC that controls the KSZ9031RNX. This 125 MHz clock is returned to the Hub FPGA as it provides the MAC for the KSZ9031RNX Ethernet circuits. Note that this Phys chip has internal series terminator resistors in the CLK125 line and the other high-speed output lines from it in the RGMII interface. The FPGA pins in its RGMII port should incorporate the correct type of DCI termination, e.g. series termination in its output pins. KSZ9031RNX RGMII Link to FPGA: -------------------------------- Reduced Gigabit Media Independent Interface between the KSZ9031RNX Phys chip and the MAC in the Hub FPGA. KSZ9031RNX MII / MIIM (aka MDIO Management Data Input Output) Link to the FPGA: --------------------------------------------------------------- This is the "Management Interface" between the MAC in the Hub FPGA and the KSZ9031RNX Phys chip. This separate interface allows an external entity to monitor and control the KSZ9031RNX via way of its MDC/MDIO Monitor Data Clock and I/O pins. The address of this port on the KSZ9031RNX is set by the PHYAD strapping jumpers. This Management Interface can talk to 32 bit registers both directly addressed IEEE defined registers and indirectly to vendor defined management registers. Full Part Number to Order: -------------------------- Micrel KSZ9031RNXCA 0-70 deg C., 48 pin QFN, Pb Free, Au Bond Wires, RGMII port, Commercial Temp. The similar but Industrial Temp range -40 +85 deg C. is part number KSZ9031RNXIA.