Rev 11-Jan-2017 Rev 29-Aug-2017 added meaning of LEDs without PROM Rev 28-Sep-2017 add pointer to PROM generator ------------------------------------------------------------------------ This file collects the current understanding of what we need to program into the Switch PROMs At the moment the only planned use for the PROM is to make the 2 LEDs per port wired in the Hub schematic display the information we want. There are 7 groups of 4 LEDs, one group for each port. For each group of 4 LEDs we want to display SPD1G on the first LED (Speed 1G) LNK/ACT on the second LED (Link / Activity) nothing on the third LED nothing on the fourth LED Note: without using a PROM to program the switch chips at power up the default power up configuration for the LEDs on the Hub front panel is expected to be, for each switch port: SPD1G on the first LED (link up at 1Gbps) SPD100M on the second LED (link up at 100Mbps) Note: information on the broadcom prom generator program and the content of the PROM files generated can be found in https://web.pa.msu.edu/hep/atlas/l1calo/hub/hardware/components/broadcom/prom_generator/ and especially in broadcom_prom_generator_notes.txt ------------------------------------------------------------------------ Quotations from the data books (Data Sheet and Design Guide) Data Sheet page 119 and Design Guide page 74 have similar but not quite identical information Data Sheet page 119 and Design Guide page 74 both say To set up the LED interface, configure strap pins LED_MODE[1:0] *OR* select the desired display the functions in the LED Function 0 Control register/LED Function 1 Control register. (note: the emphasis on "or" was added above) Design Guide page 74 FE configuration and GE configuration are available when port LED displays are set through the LED_MODE[1:0] strap pins as shown in the data sheet. The default FE configuration is set through LED function register 0, and the default GE configuration is set through LED function register 1. By default, the switch selects LED function register 1 (GE configuration). If you want to use the FE configuration with LED_MODE[1:0] strap pins, you must change the LED function map register to point to LED function register 0 instead register 1 by default. (sic) Data Sheet page 119 To configure LED display function in the two LED Function Control registers, assign each port to one of the LED Function 0 Control register and LED Function 1 Control register by enabling the bits in the LED Function Map register. The LED interface shifts out the status of the selected functions for ports enabled in the LED Enable Map register. Only four or less than four functions can be selected, and the per-port LED display occupies four LED pins (fixed four functions). The status of enabled ports is sent out from a higher port number to the lowest port number. The output order that is in the shift out is from LEDP[0], LEDP[1], LEDP[2],...LEDP[31]. The output port order for LED is from high port number to low port number, and the output bit order within the port LED is form MSB to LSB. Data Sheet page 120 The LED MODE MAP 0 and 1 registers can be set to select: - LED to blinking, - LED on, or - LED auto mode. Bit 7, LED_EN, of the LED Refresh register is default enabled. When this bit 7 is enabled, the LED display of each port status is normal and truly reflects each port link up/link down status. If bit 7 is disabled, the LED status is latched in its current state. LED signals are active low, and for the dual function LEDs, LNK, DPX,and Speed state are active low. The ACT (activity) indicator is indicated by blinking. Design Guide page 76 The BCM53128 added a flexibility to the LED function so that the user can import PHYLED1, 2, 3, and 4 display functions from the PHY registers and include them in the switch LED display function. The user selects the desired PHY LED functions in the PHY LED Control register (page 00h, address 1Dh); bits[7:4] are for the LED Function Register 1 and bits[3:0] are for the LED Function Register 0. The selected display function bits from the LED Function Register 1/0 (Page 00h, Address 12h/10h) are combined with the selected PHY LED display function bits from the PHY LED Control Register (Page 00h, Address 1Dh). The merging of two LED display functions is shown in Figure 53 on page 77, and this merge occurs in the internal hidden register. Design Guide page 77 Figure 53: Internal LED Display Register (Merging the LED Function Register and PHY LED Control Register Information) |----+-------------------| | 17 | PHYLED1 | | | 16 | PHYLED2 | | | 15 | PHYLED3 | | | 14 | BroadSync HD Link | | | 13 | 1G/ACT | | | 12 | 10/100M/ACT | | LED | 11 | 100M/ACT | | Output | 10 | 10M/ACT | | Order | 9 | SPD1G | | | 8 | SPD100M | | | 7 | SPD10M | | | 6 | DPX/COL | | | 5 | LNK/ACT | | | 4 | COL | | | 3 | ACT | | | 2 | DPX | | | 1 | LNK | | | 0 | PHYLED4 | V |----+-------------------| It also includes a reminder that the meaning of the 4 PHYLEDs is selected elsewhere Note: PHYLED1, 2, 3, and 4 are the output of the functions that are selected in the LED Selector 2 Register (Page10h-17h: Address 38P Shadow value 01110'b) In the Design Guide there is an LED display programming example on page 83-85. ------------------------------------------------------------------------ LED Control Registers Data Sheet page 149 Table 40: LED Control Register Address Summary |---------+-----------------------------------| | Address | Description | |---------+-----------------------------------| | 0Fh | LED refresh control register | | 10h-11h | LED function 0 control register | | 12h-13h | LED function 1 control register | | 14h-15h | LED function map control register | | 16h-17h | LED enable map register | | 18h-19h | LED mode map 0 register | | 1Ah-1Bh | LED mode map 1 register | |---------+-----------------------------------| LED Refresh Register (Page 00h: Address 0Fh), Data Sheet page 149 This register sets the global refresh state of all LEDs, the refresh rate (from 6Hz to 25Hz) and enable cable diagnostics during POST (Power On Self Test) The default value is x83 i.e. LEDs are allowed to refresh, with refresh rate of 40 ms/12 Hz, and no cable diagnostics during POST --> The default is a good place to start LED Function 0 Control Register (Page 00h: Address 10h), Data Sheet page 150 LED Function 1 Control Register (Page 00h: Address 12h), Data Sheet page 151 Each bit selects one LED function. A maximum of 4 bits can be selected. There are two registers so that we can have independent LED usage for two separate sets of ports. From Figure 45, page 121 |-----+---------------------| | Bit | Available Functions | |-----+---------------------| | 15 | Reserved | | 14 | BroadSync HD Link | | 13 | 1G/ACT | | 12 | 10/100M/ACT | |-----+---------------------| | 11 | 100M/ACT | | 10 | 10M/ACT | | 9 | SPD1G | | 8 | SPDI00M | |-----+---------------------| | 7 | SPD10M | | 6 | DPX/COL | | 5 | LNK/ACT | | 4 | COL | |-----+---------------------| | 3 | ACT | | 2 | DPX | | 1 | LNK | | 0 | Reserved | |-----+---------------------| The default values depend on the two LED_MODE strapping pins None of these modes work for us. We want to select SPD1G and LNK/ACT --> we need to write x0220 to LED Function 1 Control Register (and we will not be using the content of LED Function 0 Control Register) LED Function Map Register (Page 00h: Address 14h-15h), Data Sheet page 151 One bit per port to pick which Function Control register (0 or 1) is used for that port LSB is for port 0, Bit 7 is port 7, Bit 9-15 Reserved What Bit 8 is used for is not specified in the Data Sheet. Based on the Design Guide "Table 20: LED Function Map Register" this bit is referring to the IMP port (Interface Message Processor) even though there are no LED signal pins for that port. The default value is x1FF i.e. All ports use LED Function 1 Control Register --> The default is ok LED Enable Map Register (Page 00h: Address 16h-17h), Data Sheet page 152 One bit per port to enable its LEDs (LSB is for port 0, Bit 7 is port 7, Bit 8 unclear, Bit 9-15 Reserved) The default value is x1FF i.e. all port LEDs enabled --> The default is ok LED Mode Map 0 Register (Page 00h: Address 18h-19h), Data Sheet page 152 LED Mode Map 1 Register (Page 00h: Address 1Ah-1Bh), Data Sheet page 152 These two registers work together storing one bit per port (LSB is for port 0, Bit 7 is port 7, Bit 8 unclear, Bit 9-15 Reserved) The combination of the two bits from each register form a 2-bit LED mode control value From Figure 45, page 121 |-----------+-----------+-----------| | Bit from | Bit from | | | Port Mode | Port Mode | | | Map 0 Reg | Map 1 Reg | LED mode | |-----------+-----------+-----------| | 0 | 0 | LED OFF | | 0 | 1 | LED ON | | 1 | 0 | LED BLINK | | 1 | 1 | LED AUTO | |-----------+-----------+-----------| From Design Guide page 85 The user configures the LED Mode Map Register (Page 00h, address 18h and 1Ah) to set the LED display mode. Normally the user sets the LED mode to auto. Auto means that the LED will indicate any status with a steady "on" signal, while "blinking" indicates activity. Off, on, and blinking modes are unrelated to the actual status display. These represent the LED monitoring functions of off, on, and blinking (activity) regardless of the actual status. The default value is x1FF in both registers i.e. all port LEDs are set to mode AUTO --> The default is ok LED Control Register (Page 00h: Address 1Ch), Data Sheet page 153 Sets the LED behavior during POST (Power On Self Test) and especially the behavior of dual-color LEDs (which we do not use) It is not 100% clear what it does for single-color LEDs --> but the default value is probably fine until further notice PHY LED Control Register (Page 00h: Address 1Dh), Data Sheet page 153 This adds more options to LED Function 0 and 1 Control Registers and display imported PHYLED1, 2, 3, and 4 The default value for strapping mode LED_MODE=10 is x00 i.e. none of the PHYLED singals is selected --> The default is ok ------------------------------------------------------------------------ The resulting LED usage for LEDP0 to LEDP31 should then be |-----+------+-----+---------+------------------------| | LED | Port | | Fnction | Hub Usage | |-----+------+-----+---------+------------------------| | 0 | 7 | MSB | SPD1G | Port 7 Speed 1Gb | | 1 | | | LNK/ACT | Port 7 Link & Activity | | 2 | | | Unused | Not Connected | | 3 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 4 | 6 | MSB | SPD1G | Port 6 Speed 1Gb | | 5 | | | LNK/ACT | Port 6 Link & Activity | | 6 | | | Unused | Not Connected | | 7 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 8 | 5 | MSB | SPD1G | Port 5 Speed 1Gb | | 9 | | | LNK/ACT | Port 5 Link & Activity | | 10 | | | Unused | Not Connected | | 11 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 12 | 4 | MSB | SPD1G | Port 4 Speed 1Gb | | 13 | | | LNK/ACT | Port 4 Link & Activity | | 14 | | | Unused | Not Connected | | 15 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 16 | 3 | MSB | SPD1G | Port 3 Speed 1Gb | | 17 | | | LNK/ACT | Port 3 Link & Activity | | 18 | | | Unused | Not Connected | | 19 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 20 | 2 | MSB | SPD1G | Port 2 Speed 1Gb | | 21 | | | LNK/ACT | Port 2 Link & Activity | | 22 | | | Unused | Not Connected | | 23 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 24 | 1 | MSB | SPD1G | Port 1 Speed 1Gb | | 25 | | | LNK/ACT | Port 1 Link & Activity | | 26 | | | Unused | Not Connected | | 27 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| | 28 | 0 | MSB | SPD1G | Port 0 Speed 1Gb | | 29 | | | LNK/ACT | Port 0 Link & Activity | | 30 | | | Unused | Not Connected | | 31 | | LSB | Unused | Not Connected | |-----+------+-----+---------+------------------------| ------------------------------------------------------------------------ Sanity/Consitency Check on understanding these LED signals In the Design Guide page 82 there is a table with the LED usage for the four pre-defined modes given by the state of the two LED_MODE pins. This just repeats the information from Data Sheet page 130&131 (but noting that they interchangeably call these pins "LED MODE" or "LED_MODE" in various places and even that the Design Guide p96 checklist refers twice to 3 pins "LEDMODE[2:0]") When LED MODE[1:0] = 00: |----------------------+----------------------| | For FE configuration | For GE configuration | |----------------------+----------------------| | SPD100M | SPD1G | | LNK/ACT | SPD100M | | PHYLED4 | LNK/ACT | | | PHYLED4 | |----------------------+----------------------| When LED MODE[1:0] = 01: |----------------------+----------------------| | For FE configuration | For GE configuration | |----------------------+----------------------| | 100M/ACT | 1G/ACT | | 10M/ACT | 10/100M/ACT | | DPX/COL | DPX/COL | | PHYLED4 | PHYLED4 | |----------------------+----------------------| When LED MODE[1:0] = 10: |----------------------+----------------------| | For FE configuration | For GE configuration | |----------------------+----------------------| | SPD100M | SPD1G | | LNK/ACT | SPD100M | | DPX | LNK/ACT | | | DPX | |----------------------+----------------------| When LED MODE[1:0] = 11: |----------------------+----------------------| | For FE configuration | For GE configuration | |----------------------+----------------------| | 100M/ACT | 1G/ACT | | 10M/ACT | 100M/ACT | | DPX | 10M/ACT | | | DPX | |----------------------+----------------------| To raise confidence that we understand how this all works we can compare this table to the default values advertized for the relevant registers. We need to combine the information from LED Function 0 Control Register & PHY LED Control Register bits 0:3 as well as LED Function 1 Control Register & PHY LED Control Register bits 4:7 From data sheet page 150, and page 153 we can decode the default values into what bit they control LED Function 0 Control Register (Page 00h: Address 10h) |-----+---------------------+---------+----------+---------+----------| | | | Mode 00 | Mode 01 | Mode 10 | Mode 11 | | | | default | default | default | default | | Bit | Available Functions | x0120 | x0C40 | x0124 | x0C04 | |-----+---------------------+---------+----------+---------+----------| | 15 | Reserved | 0 | 0 | 0 | 0 | | 14 | BroadSync HD Link | 0 | 0 | 0 | 0 | | 13 | 1G/ACT | 0 | 0 | 0 | 0 | | 12 | 10/100M/ACT | 0 | 0 | 0 | 0 | |-----+---------------------+---------+----------+---------+----------| | 11 | 100M/ACT | 0 | 1 | 0 | 1 | | 10 | 10M/ACT | 0 | 1 | 0 | 1 | | 9 | SPD1G | 0 | 0 | 0 | 0 | | 8 | SPDI00M | 1 | 0 | 1 | 0 | |-----+---------------------+---------+----------+---------+----------| | 7 | SPD10M | 0 | 0 | 0 | 0 | | 6 | DPX/COL | 0 | 1 | 0 | 0 | | 5 | LNK/ACT | 1 | 0 | 1 | 0 | | 4 | COL | 0 | 0 | 0 | 0 | |-----+---------------------+---------+----------+---------+----------| | 3 | ACT | 0 | 0 | 0 | 0 | | 2 | DPX | 0 | 0 | 1 | 1 | | 1 | LNK | 0 | 0 | 0 | 0 | | 0 | Reserved | 0 | 0 | 0 | 0 | |-----+---------------------+---------+----------+---------+----------| PHY LED Control Register (Page 00h: Address 1Dh) |-----+---------------------+---------+----------+---------+----------| | | | Mode 00 | Mode 01 | Mode 10 | Mode 11 | | | | default | default | default | default | | Bit | Available Functions | x88 | x88 | x00 | x00 | |-----+---------------------+---------+----------+---------+----------| | 3 | PHYLED4 of LED F0CR | 1 | 1 | 0 | 0 | | 2 | PHYLED3 of LED F0CR | 0 | 0 | 0 | 0 | | 1 | PHYLED2 of LED F0CR | 0 | 0 | 0 | 0 | | 0 | PHYLED1 of LED F0CR | 0 | 0 | 0 | 0 | |-----+---------------------+---------+----------+---------+----------| So the Combined LED bit usage for LED Function 0 matches what the LED_MODE specifies for the "FE configuration" +---------+----------+---------+----------| From | SPD100M | 100M/ACT | SPD100M | 100M/ACT | LED Function 0 | LNK/ACT | 10M/ACT | LNK/ACT | 10M/ACT | Control Reggiseter | | DPX/COL | DPX | DPX | ---------------------+---------+----------+---------+----------| From PHY LED CTRL | PHYLED4 | PHYLED4 | | | +---------+----------+---------+----------| LED Function 1 Control Register (Page 00h: Address 12h) |-----+---------------------+---------+-------------+---------+----------| | | | Mode 00 | Mode 01 | Mode 10 | Mode 11 | | | | default | default | default | default | | Bit | Available Functions | x0320 | x3040 | x0324 | x2C04 | |-----+---------------------+---------+-------------+---------+----------| | 15 | Reserved | 0 | 0 | 0 | 0 | | 14 | BroadSync HD Link | 0 | 0 | 0 | 0 | | 13 | 1G/ACT | 0 | 1 | 0 | 1 | | 12 | 10/100M/ACT | 0 | 1 | 0 | 0 | |-----+---------------------+---------+-------------+---------+----------| | 11 | 100M/ACT | 0 | 0 | 0 | 1 | | 10 | 10M/ACT | 0 | 0 | 0 | 1 | | 9 | SPD1G | 1 | 0 | 1 | 0 | | 8 | SPDI00M | 1 | 0 | 1 | 0 | |-----+---------------------+---------+-------------+---------+----------| | 7 | SPD10M | 0 | 0 | 0 | 0 | | 6 | DPX/COL | 0 | 1 | 0 | 0 | | 5 | LNK/ACT | 1 | 0 | 1 | 0 | | 4 | COL | 0 | 0 | 0 | 0 | |-----+---------------------+---------+-------------+---------+----------| | 3 | ACT | 0 | 0 | 0 | 0 | | 2 | DPX | 0 | 0 | 1 | 1 | | 1 | LNK | 0 | 0 | 0 | 0 | | 0 | Reserved | 0 | 0 | 0 | 0 | |-----+---------------------+---------+-------------+---------+----------| PHY LED Control Register (Page 00h: Address 1Dh) |-----+---------------------+---------+-------------+---------+----------| | | | Mode 00 | Mode 01 | Mode 10 | Mode 11 | | | | default | default | default | default | | Bit | Available Functions | x88 | x88 | x00 | x00 | |-----+---------------------+---------+-------------+---------+----------| | 7 | PHYLED4 of LED F1CR | 1 | 1 | 0 | 0 | | 6 | PHYLED3 of LED F1CR | 0 | 0 | 0 | 0 | | 5 | PHYLED2 of LED F1CR | 0 | 0 | 0 | 0 | | 4 | PHYLED1 of LED F1CR | 0 | 0 | 0 | 0 | |-----+---------------------+---------+-------------+---------+----------| So the Combined LED bit usage for LED Function 1 matches what the LED_MODE specifies for the "GE configuration" +---------+-------------+---------+----------| | SPD1G | 1G/ACT | SPD1G | 1G/ACT | From | SPD100M | 10/100M/ACT | SPD100M | 100M/ACT | LED Function 0 | LNK/ACT | DPX/COL | LNK/ACT | 10M/ACT | Control Reggiseter | | | DPX | DPX | ---------------------+---------+-------------+---------+----------| From PHY LED CTRL | PHYLED4 | PHYLED4 | | | +---------+-------------+---------+----------| Conclusion: This consistancy test of our understanding of the meaning of this registers is passed. -------------------------------------------------------------------------------