Trace Routing Details Hub Module ------------------------------------ Original Rev. 17-Mar-2015 Current Rev. 17-Feb-2017 This file holds the details of the trace routing on the Hub Module. This includes such things as: trace widths, vias used, differential trace design, differential vias, spacings trace to trace, diff trace to diff trace, and via to pin. Note that this files started as part of a different project and some of the information in this file was never brought up to date for the Hub Module and thus is wrong. Sketch of Trace Dimension Rules: -------------------------------- Recall some typical middle of the road trace dimension rules: comfortable single ended: 0.20 mm width 0.60 mm C to C tighter single ended: 0.16 mm width 0.50 mm C to C 1mm pitch BGA escape: 0.13 mm width 100 Ohm diff pair: 0.14 mm width 0.40 mm C to C diff pair to diff pair: 2.00 mm C to C is nice pitch 1.50 mm C to C is used where necessary 1.20 mm C to C short identical clocks the zone 2 connector pitch is 2.5 mm and in 5 mm we get 6 diff pairs to the MGT fanout 1 Clock pair and 1 TTC back data pair. to bend the pair by 45 deg it takes 0.7 mm along the trace vias on both sides of the diff pair can be spaced 2.0 mm C to C Basic parallel trace to DC Caps to via pair to parallel: total length along the traces is 2.7 mm C to C spacing of the caps and diff via pair 1.00 mm side to side furthest copper is a width of 1.60 mm C to C of the Ground via pair is 3.40 mm Center of Normal size small via to closest metal of a pad in the same net: 0.5 mm Standard Via Sizes: The following vias are used to route the Hub card. The numeric field in the via name should indicate the via's pad diameter aka land diameter. via_0mm60: used in the BGA footprint via_0mm65: normal signal routing via_1mm1: some power and ground via_0mm60: finished hole diameter 0.30 mm land pad 0.60 mm plane relief 0.87 mm solder mask relief 0.50 mm --> ring width 0.150 mm --> plane isolation Air Gap 0.135 mm from the pad --> plane isolation Air Gap 0.285 mm from edge of Drill hole NOT-Tented via_0mm65: finished hole diameter 0.30 mm land pad 0.65 mm plane relief 1.00 mm solder mask relief 0.50 mm --> ring width 0.175 mm --> plane isolation Air Gap 0.175 mm from the pad --> plane isolation Air Gap 0.350 mm from edge of Drill hole NOT-Tented via_1mm1: finished hole diameter 0.60 mm land pad 1.10 mm plane relief 1.60 mm solder mask relief 1.00 --> ring width 0.25 mm --> plane isolation Air Gap 0.25 mm from the pad --> plane isolation Air Gap 0.50 mm from edge of Drill hole NOT-Tented via_2mm2: finished hole diameter 1.10 mm land pad 2.20 mm plane relief 1.90 mm solder mask relief 1.50 --> ring width 0.55 mm --> plane isolation Air Gap none from the pad --> plane isolation Air Gap 0.40 mm from edge of Drill hole NOT-Tented =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Trace Widths Used for Routing the Hub Module: --------------------------------------------- The following trace widths are used for "Normal" applications: -------------------------------------------------------------- Normal CMOS signal routing where space permits: 0.20 mm traces on 0.6 mm centers To break out by 45 degrees they stager by 0.3 mm on the 0.6 mm center to center run. use via_0mm65 vias spaced 1.2mm center to center Normal CMOS signal routing where things are tight: In the BGA escape we need to use 0.13mm traces for the optimum layout. Details: the BGA Vias are 0.58mm pad diameter and are spaced 1mm center to center. This gives 0.42mm for the escape trace and its clearance on both sides. This 0.42mm is used as a 0.13mm escape trace and a 0.145 mm clearance on both sides. Using 0.16 mm wide traces on 0.5 mm centers works out well for buses that come out of the FPGA and for the vertical busses. Translator 74AVCAH164245 Signals - 0.20 mm trace straight IN 0.7mm to via_0mm65 OUT 0.4mm bend to 0.05mm grid via_0mm65 0.9mm from pad edge Power & Ground - 0.25 mm trace to via_0mm65 centered 0.7mm from pad edge Bypass Caps - 0.60 mm trace Bypass Capacitor 0603 size connections 0.60 mm trace to via_0mm65 centered 0.5mm from pad edge Normal Bypass Capacitor 0805 size connections 0.75 mm trace to via_0mm65 centered 0.7mm from pad edge In the power supply section may use 1.0mm trace width for the 0805 ceramic capacitors. Power Bypass Capacitor 0805 size connections 1.0 mm trace to via_1mm1 centered 1.0mm from pad edge or centered 0.9mm from pad edge Tant D pads 2x 1.20 mm 1mm1 via CL on pad edges 1.1mm or 1.2mm from pad edge to via center Tant B pads 1.20 mm trace 1mm1 via CL on pad edges 0.9mm from pad edge to via center or two 0.75 mm traces to two via_0mm65 Al Electrolytic F pads 2x 1.20 mm 1mm1 via edge on pad edges Transient Suppressor pads 1.20 mm 1mm1 via in center Fuse Holder pads 2x 4x 1.20 mm 1mm1 via 0.20mm width differential pair on 0.5mm center to center with a unit cell pitch of 1.5mm from one pair to the next. Thus you can fit 8 of these differential pairs in 12mm. 0.25mm width differential pair on 0.6mm center to center. 0.35mm width for the "analog" traces in the DC/DC converters. Special "Key" Trace Widths: --------------------------- For all of these 100 Ohm differential traces: 0.14mm width 0.4mm spacing center/center 0.5mm spacing cent/cent is an alternative Notes: We want the open space between a differential pair to be about twice the width of one of the traces in the differential pair. I.E. the center to center spacing is 3 times the width of one of the traces (or a little bit more - not less). We can not use 0.13mm width as a "Key" trace width because we need this for the BGA escape routing. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Differential Trace Layout: -------------------------- All 100 Ohm differential traces on the Hub Module will be layed out using a "key" trace width to indicate that they are a 100 Ohm differential pair. This key layout pattern is: Trace Width: 0.14 mm Trace Spacing Center to Center: 0.40 mm Open Space between Traces: 0.26 mm This is fine for horizontal and vertical traces. What about differential trace routing at an angle ? Hub Module could use: Starting from the Horz or Vert parallel traces, Stager by 0.20 mm to start the trace segments at an angle: Slope: 1 Center to Center Distance: 0.4243 mm Open Space between Traces: 0.2843 mm Extra Length at the Bend: 0.3414 mm Starting from the Horz or Vert parallel traces, Stager by 0.10 mm to start the trace segments at an angle: Slope: 1 Center to Center Distance: 0.3536 mm Open Space between Traces: 0.2136 mm <-- Too Small Extra Length at the Bend: 0.3121 mm Slope: 0.5 Center to Center Distance: 0.4025 mm Open Space between Traces: 0.2625 mm Extra Length at the Bend: 0.1894 mm Slope: 0.3333 Center to Center Distance: 0.4111 mm Open Space between Traces: 0.2711 mm Extra Length at the Bend: 0.1316 mm Slope: 0.25 Center to Center Distance: 0.4123 mm Open Space between Traces: 0.2723 mm Extra Length at the Bend: 0.1000 mm The pair of traces in a high-speed differential pair need to be the same length. At 10 Gb/s - the bit length is about 100 psec - a trace 1 mm long takes about 6.6 psec (assume 1/2 c) We assume that the differential signals are isochronous at the component pins and thus there may be a skew by the time that these signals reach the straight section of the Diferential Pair. From reading lots of application notes, and from looking at many examples of commercial cards with high speed differential traces, it is clear that we need to take some care with matching trace lengths on both sides of a differential signal. We used the following guide lines for adjusting the high speed differential trace lengths on the Hub Module card. These guide lines are: - First adjust the trace lengths by modifying the circuit at the net list level, e.g. change which GTX Translator is connected to which MiniPOD channel or add a polarity swap to get a better length match within a differential pair. In general this step appears to get the trace lengths within about 1.6 mm of being equal. - Next adjust the topology of how the traces enter the MiniPOD BGA to get a better length match, e.g. change which side of the BGA the traces enter from, enter on the other side of the MiniPOD BGA pins, add a loop to the shorter trace within the BGA foot print. - As the last step add a serpentine section to the shorter trace. We are using the following rules to make the serpentines: On a vertical or horizontal trace the serpentine is: A perpendicular step out of 0.2 mm for a length of 0.5 mm. Return to the normal trace path for 0.6 mm before stepping out again. Round the 4 corners of each step out with an arc of 24 segments/rotation and a radius of 0.10 mm. Each of these step outs will add 0.225 mm of trace length. On a 45 degree diagonal trace the serpentine is: A perpendicular step out of 0.2121 mm for a length of 0.4950 mm. 0.2121 mm is 3 grid dots diagonally with a grid of 0.05 mm. 0.4950 mm is 7 grid dots diagonally with a grid of 0.05 mm. Return to the normal trace path for 0.5657 mm before stepping out again, i.e. 8 grid dots diagonally with a grid of 0.05 mm. Round the 4 corners of each step out with an arc of 24 segments/rotation and a radius of 0.11 mm. Each of these step outs will add 0.265 mm of trace length. Add serpentine until the short trace comes within about 0.3 mm of the longer trace. Do not make the short trace longer than the originally longer trace. Stopping the serpentine about 0.3 mm short of a match allows for the possibility that the added electrical delay of the serpentine is greater than its added geometric length. Note that all of the high-speed differential signals had their corners rounded. This rounding was typically done with 24 segments/rotation for bend radius up to about 2 mm and then 48 segments/rotation for larger bend radius. There is the issue of either, having a common bend radius for the inner and outer trace, or having a common center point for the bend of the inner and outer traces. If anything it is probably best to let the separation between the two traces increase a little bit during the bend. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Differential Via Layout: ------------------------ - We will use a standardized via layout pattern for all of the 100 Ohm Differential traces. - All of the Hub Module's 100 Ohm differential traces are routed as 0.14 mm trace width on 0.4 mm centers. This is a "key trace width" to identify the 100 Ohm differential traces to the bare pcb house. - For the 100 Ohm Differential traces that are spaced 0.4mm we should use Differential Vias that are spaced 1.0mm center to center. - The ground plane is removed in an oval that is a line 1.0 mm wide and runs between the centers of the two via. - The Area Fills are removed in a rectangle that is 1mm by 2mm, i.e. this rectangle has the same outer dimensions as the removed oval of ground plane. - In some places (where the ground structure is a little weak) the ground plane is allowed to fill in a little bit if neither of the traces running to the via in question are on that half of the stackup. For example if the "input" and "output" high-speed traces are both in the Top half of the card, then an Oval ground relief is used in both the Top and Middle version sof the Ground plane - where are two circles of 0.85 mm diameter are used for ground plane relief in the Bottom one third of the ground plane. - It is required to put a pair (or a quad) of ground rivet vias near the Differential Via pair. In one pattern there are two ground rivets colinear with the two via and spaced at total of 3.4 mm center to center. The intent of the ground rivets in the differential via layout is to provide a local symmetric return path for any common mode current that is flowing with the differential signal. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= At 6 Gbps What Size Imperfections Make a Difference ? ----------------------------------------------------- We have 6 G bits per second data flow to the MiniPODs. So this is basically a waveform like a 3 GHz sin wave but we need to include the 3rd and 5th harmonics. So we need transmission lines with good flat characteristics up through 15 GHz. In open space 15 GHz is 20 mm wave length. The transmission lines on the card are about 1/2 the speed of light so on these lines a wavelength is about 10 mm. To be a good flat line we must keep any imperfections down to a physical size of less then 1/20th of a wavelength or so. Thus we care about bumps that are 0.5mm in size. So for work on Hub Module lets wake up when we see bumps on the scale of 1/2 of that, i.e. 0.2mm in size. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Design Rules used for Routing the Hub Module: --------------------------------------------- We will start on 10-Apr-2013 with Net Rules for the Default Net_Type: Pin Via Trc Fill Pin 0.5 Via 0.1 0.3 Trc 0.22 0.25 0.25 Fill 0.4 0.4 0.5 0.7 The final minimal design rules that the Hub will pass are: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.20 0.35 Trace 0.12 0.20 0.185 Fill 0.14 0.20 0.30 0.40 Quad_LED Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 1.00 1.00 Trace 1.00 1.00 1.00 Fill 0.14 0.20 0.30 0.40 Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.38 1.00 Trace 0.12 0.26 0.21 Fill 0.15 0.20 0.35 0.40 Details of the Design Rules checks are in the file: hub_drc_run_notes.txt =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Switch Chip Trace Routing: -------------------------- The Switch Chips have SMD Pads that are 1.30 mm long by 0.20 mm wide. Use 0.14 mm traces at 0.40 mm C to C for the Ethernet Diff Pairs. Use 0.20 mm traces for power and ground. Use 0.16 mm traces for tight single ended CMOS. Use the 0mm60 via for the Ethernet Diff Pairs. Use the 0mm65 via for power and ground. The Vias are 0.55 mm and 1.15 mm from the end of the Pad (0mm65) Or Vias are 0.45 mm and 0.95 mm from the end of the Pad (0mm60) The via to pad spacing is an issue of both copper clearance and of having enough solder mask to keep the non-tented via from sucking in the solder. If a trace needs to run between these vias then they are 0.55 mm and 1.55 mm from the end of the Pad. In general the Ethernet pairs route outward and the power and ground traces route inward. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Resistance of Traces: --------------------- Start with the resistance of Copper at 25 degrees C. A bar of 1 square inch cross section and 1 foot long has a resistance of about 8.30 micro Ohms at 25 degrees C. The coefficient of resistance is positive and is about 0.38 % per degree C. This means that 1/2 oz copper is about 1 mOhm per square. A closer estimate for 1/2 oz is 1.0323 mOhm per square. So for 1/2 oz coper (i.e. about 0.00067 inch or 17 um thickness) we have the following: Trace Width Resistance Approximate mm mOhms per cm Wire Gauge ------ -------------- ----------- 0.13 79.41 mOhm/cm > 40 AWG 0.14 73.74 > 40 0.16 64.52 > 40 0.50 20.65 38 1.00 10.32 35 =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Backside Metal for the: QFN, Switch, and PVA Components: --------------------------------------------------------- In the Hub design I want metal on the backside of such things as the center thermal/ground pad of the QFN and Switch components and for the Power Via Arrays. Note that "backside" typically means "side 2" aka the "solder" side - but note that the QFN-16 for the OnSemi Fanout chips is placed on both sides of the card. Using Breaout_1 for the front-side copper works well. But the Breakout layers follow the Top/Bottom Layer Mapping Rules so they can not be used for copper on the opposite side from where the component is placed. This all makes good rational sense but I do not know the official way that Mentor wants me to place backside metal. For a side 1 component I can not just use Signal_10 in its geometry for backside metal as this will cause a placement clearance error where for example I overlap the backside PVA metal with the associated component pin. So I have given up trying to figure out how to officially do this and I'm just going to do something unofficial but easy to understand and rational. In the Geometries for the: QFNs, Switch, and PVAs I'm placing the backside metal by: - Components instanced on Side 1 have their backside metal on Side 2 and in their geometry this metal is described on layer Sheet-Dielectric_1. - Components instanced on Side 2 have their backside metal on Side 1 and in their geometry this metal is described on layer Sheet-Dielectric_2. Note that this does not violate the Mentor Top/Bottom Layer Mapping Rules. The specific Sheet_Dielectric layer used matches the side on which the component is instanced. In generating the Gerber Plots the ArtWork Order file needs to: - Include Sheet-Dielectric_2 in the Top side (side 1) plot. - Include Sheet-Dielectric_1 in the Bottom side (side 2) plot. Note that this is strange, i.e. I'm using a specific layer 2 during the generation of a side 1 plot. But this does not violate any rules. Note that this only works because the generic and specific Sheet_Dielectric layeres are not being used for anything else in the Hub design so that they are empty except for my use of them for the backside metal in the QFN, Switch, and PVA components. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Gerber Plot Generation: ----------------------- For the Hub project, generation of the gerber plots themselves is done by a script that is in the Tools sub-directory. Note that the Area Fills on the Hub project are being "flashed" and not "painted" as I have done on earlier cards. Even with the script to generate the Gerber Plots there are still two Gerber Plot related activities that must be done by hand: Setting up the Artwork Format Filling the Aperture Table Editing the Power Apertures Artwork Format: The Artwork Format has been setup and should not need to be changed. - I'm reporting the Artwork Format in the Aperture Table report - so you can see it there. - Note that the Artwork Format needs to include the the number of Segments used in Linear Interpolation which is currently set for 36. (but could be 24 or 48) - It is still not absolutely clear to me if I need to include anything special in the Artwork Formet to support Flashing the Area Fills. Filling the Aperature Table: NOTE: Only delete and remake the Aperture Table if you need to. ----- Once we have the Aperture Table setup the way that we want it for the Hub then do NOT delte and remake it. Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale NOT Select Flash Complex Padstacks !! still not clear Replace the table Recall that you need to Save the Aperture Table. For example: File --> Save --> Design Specific --> Aperture Table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to .../Work/Text/ Save with a filename that includes the date Currently there are about 300 apertures. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Editing the Power Apertures: ---------------------------- In many previous deisgns we have used normal Thermal Relief Power Apertures. I typically needed to edit these to setup their "Air Gap" and "Spoke Width" to get the characteristics that we wanted for a given design. Because of the high frequency signals on the Hub Module and because the Thermal Relief connections to the Ground Planes perform no useful function of the Hub Module I want to get rid of them. On the Hub Module I want to bury aka flood the Ground Pins/Vias into the Ground Planes. The only exceptions to the might be: the Ground Vias for the"Scope Loop" ground connection points the small Ground Pin on the Power Entry module the large output Ground Pin on the Iso_12V module. There are probably 3 ways to flood the Ground Pins/Vias into the Ground Planes: - Drop the "Power" attribute of these apertures and set their diameter to Zero. Risky because what does Zero diameter mean to the printer machine at the bare board house. - Drop the "Power" attribute of these apertures and set their diameter to something much smaller than the diameter of the Dill Hole that will be used at the bare board house to make this pin/via connections to the Ground Planes. Risky because how do I know that this small diameter Flash is small enough that it does not cause problems at the bare board house. - Edit the 3 Ground Plot Gerber Files and pull out of them all data associated with the Power Apertures that I want removed from these plots in order to flood these ground connections into the Ground Planes. The choice was to use a sed script to directly edit the Ground Plane gerber files produced by Mentor. This script is in the ..../Tools/ directory: remove_most_ground_thermal_relief.sh =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Special Uses of Mentor Logical Layers: -------------------------------------- In the Hub Design I have made special use of a number of Mentor Logical Layers. Special use of Mentor Layers has been made to provide Ground Cutouts and Via Plugs. Review the special use of layers in the Hub design: Ground Plane Cuts Top&Mid layers Glue_Mask_1 Ground Plane Cuts in Top layers PrePreg_1 Ground Plane Cuts in Bot layres PrePreg_2 Ground Plane Cuts in All layers PrePreg_3 Ground Plane Cuts Mid&Bot layers Component_Metal_1 Vias Plugged from the Top PrePreg_5 Vias Plugged from the Bottom PrePreg_6 Backside metal on Bot side e.g. QFN center pad Sheet_Dielectric_1 Backside metal on Top side e.g. QFN center pad Sheet_Dielectric_2 Back-Drills non-Zone_2 from Top Shallowest Sheet_Dielectric_4 Back-Drills non-Zone_2 from Top NT Shallowest Sheet_Dielectric_5 Back-Drills non-Zone_2 from Top NT Deepest Sheet_Dielectric_6 Back-Drills non-Zone_2 from Top Deepest Sheet_Dielectric_7 Back-Drills non-Zone_2 from Bot Shallowest Sheet_Dielectric_8 Back-Drills non-Zone_2 from Bot NT Shallowest Sheet_Dielectric_9 Back-Drills non-Zone_2 from Bot NT Deepest Sheet_Dielectric_10 Back-Drills non-Zone_2 from Bot Deepest Sheet_Dielectric_11 Mark All non-Zone_2 Back-Drills Sheet_Dielectric_12 Back-Drills Only-Zone_2 from Bot Shallowest PrePreg_9 Back-Drills Only-Zone_2 from Bot Mid Depth PrePreg_10 Back-Drills Only-Zone_2 from Bot Deepest PrePreg_11 Mark All Only-Zone_2 Back-Drills PrePreg_12 Front Panel, LEDs, FPGA Heat-Sink Conformal_Mask_1 ATCA LED type areas Conformal_Mask_2 Recall that Sheet_Dielectric_1 is being used for the backside metal of components that are placed on the Top side of the card. This is metal on side 2. Sheet_Dielectric_2 is being used for the backside metal of components that are placed on the Bottom side of the card. This is metal on side 1. PrePreg_5 marks the vias that are plugged from the Top PrePreg_6 marks the vias that are plugged from the Bottom. The Geometries that have backside metal or plugs include: switch_328_pin_geom, lt1764_dd_pak_dcdc9.txt, both MiniPOD_Geoms, phys_48_pin_geom, qfn_16_on_semi_bot, qfn_16_on_semi_top, qfn_16_ti, qfn_32, qfn_48, via_0mm60_bot_plug, via_0mm60_top_plug The Ground Plane cutouts are implemented as patterns on there of the PREPREG layers and two other special use layers: - PREPREG_1 cuts out the Ground Plane near the top side of the PCB but allows it to close on the bottom side. Thus for example PREPREG_1 is used in DC Blocking caps that are placed on the top side of the PCB. - PREPREG_2 cuts out the Ground Plane near the bottom side of the PCB but allows it to close on the top side. Thus for example PREPREG_2 is be used in DC Blocking caps that are placed on the bottom side of the PCB. - PREPREG_3 cuts out the Ground Plane on all PCB Ground Plane layers. Thus for example PREPREG_3 is used for ground relief around a high speed differential pair that goes the whole way through the PCB. - GLUE_MASK_1 cuts out the Ground Plane on just its Top and Middle versions. This allows only the normal "Power" type plane relief to be active on the bottom version of the Ground Plane. This allows full Oval relief on the Top & Middle with just two circle relief on the bottom type of Ground Plane. This can be used for Differential Pair Vias where both "input" and "output" signals are in the Top half of the card. - COMPONENT_METAL_1 cuts out the Ground Plane on just its Middle and Bot versions. This allows only the normal "Power" type plane relief to be active on the Top version of the Ground Plane. This allows full Oval relief on the Middle and Bottom with just two circle relief on the top type of Ground Plane. This can be used for Differential Pair Vias where both "input" and "output" signals are in the Bottom half of the card. Via Plugts are implemented in two of the PREPREG Layers: - PREPREG_5 marks the vias that are to be Plugged from the Top side of the card. - PREPREG_6 marks the vias that are to be Plugged from the Bottom side of the card. - The hub includes vias (center pad thermal/ground vias and routing vias) that are plugged from both the Top and Bottom. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=