Trace Routing Strategy Hub Module ------------------------------------ Original Rev. 17-Mar-2015 Current Rev. 25-Jan-2017 This file was started well before any actual routing work began on the Hub Module. The intent was to list the anticipated problems that we would find in routing the Hub-Module and to design a strategy around these problems before the actual routing work was started. The main routing problem on the Hub Module is the large number of high speed differential traces that run to the backplane Zone 2 connectors. Another issue is component placement on the PCB so that the noisy DCDC Converters are not in the path of the high speed traces. Start by listing the Differential Traces and their starting and ending locations on the PCB: Differential Pair Traces on the Hub PCB: ---------------------------------------- Diff Differential Pair Pair Trace Family Count Start and End Locations ------------------------ ----- ------------------------------ FEX Data from Backplane 72 Zone 2 to the MGT Fanout Other Hub Data from BckPln 2 Zone 2 to the MGT Fanout FEX Data to the ROD 72 MGT Fanout to ROD MegArray Other Hub's Data to ROD 2 MGT Fanout to ROD MegArray This Hub's Data to ROD 2 Hub FPGA to ROD MegArray FEX Data to Hub FPGA 72 MGT Fanout to Hub FPGA Other Hub Data to Hub FPGA 2 MGT Fanout to Hub FPGA This Hub's data to BckPln 2 Hub FPGA to Zone 2 40.08 MHz Clk to Backplane 13 Clock Gen&Fanout to Zone 2 Clock to ROD 1 Clock Gen&Fan to ROD MegArray Clocks to Hub FPGA 10 Clock Gen&Fan to Hub FPGA Readout Control from ROD 1 ROD MegArray to Hub FPGA Other Hub's Combined Data 1 Zone 2 to Hub FPGA Combined TTC Data to BkPln 13 Hub FPGA to Zone 2 Combined TTC Data to ROD 1 MegArray S1 Ethernet Switch to BckPln 52 Switch Chips to Zone 2 ROD Enet to Front Panel 4 ROD MegArray to Frt Pnl RJ45 IPMC Enet to Front Panel 4 IPMC Socket to Frt Pnl RJ45 Switch Enet to Front Panel 16 Switch Chip to Frt Pnl RJ45 Hub FPGA Enet to Backplane 4 Hub FPGA Enet to Zone 2 Hub FPGA Enet to Switch 4 Hub FPGA Phys Chip to Switch Intra Switch Enet 8 Within Switch Cap Coupled Enet Hub FPGA to Trans MiniPOD 12 Hub FPGA to Transmit MiniPOD Rec MiniPOD to Hub FPGA 4 Receiver MiniPOD to Hub FPGA Spare HP I/O from/to ROD 4 ROD MegArray to Hub FPGA ----- 378 Total estimated number of differential pairs Connections to the Hub FPGA's MGT Transceivers: ----------------------------------------------- All of the MGT Receivers will be used on the Hub Module along with about 29 of the MGT Transmitters. There are only 2 rules that I know of to control which signal is assigned to a given MGT Transceiver in a given MGT Quad. These rules are: - The Quad to which a given signal is assigned must have the correct Reference Clock available to generate the serial line rate required for that signal. - It is desired, but in my mind not mandatory, that all of the links from a given FEX card be routed to only 2 Quads. The intent is to be able to reduce power if not all 12 FEX cards are used in a given Hub application. Aside from that there are no other rules that govern which signal is assigned to what MGT Transceiver in what Quad. Thus in large part the MGT signals were assigned to MGT resources in whatever arrangement provides the best high frequency trace routing. The Direct and Complement sides of the differential signals were be assigned to the FPGA pins in whatever way allows the best high frequency trace routing. MGT Resources Used on the Hub Module -------------------------------------- Receivers Function --------- --------------------- 72 6 Links Receive Readout Data from each of 12 FEX 2 2 Links Receive Readout Data from the Other Hub 1 Receiver This ROD's "Readout Control Data" 1 Receiver the Other Hub's "Combined Data" 4 Signals from the Hub's MiniPOD Receiver One of these four is dedicated to receiving the Optical Timing signal. 0 Current Count of Spare MGT Receivers Transmitters ------------ 2 Send Readout Data to the ROD on This Hub 2 Send Readout Data to the ROD on Other Hub 14 Send the combined TTC + ROD1 + ROD2 Data to: 12 FEX, to This ROD, and to the Other Hub 8 Signals to Hub's MiniPOD Transmitter 54 Spare MGT Transmitter count Hub FPGA Select I/O Signals: ---------------------------- The XCVU125 FPGA in the FLVC2104 package provides about 416 Select I/O signals. These Select I/O signals are in 9 Banks. There are 7 HP Select I/O Banks with 52 I/O signals each and 2 HR Banks with 26 I/O signals each. The Hub Design uses about 166 Select I/O signals. The following is a list of some of the Hub's Select I/O signals: Count Function and Comments ----- ---------------------------------------- 4 I2C Slave for SysMon and I2C Master 40 Configuration PROM: Data, Address, and Management 8 Spare Links to/from the ROD 8 Receive the Backplane Slot Hardware Address 8 Receive "Shelf Adrs" from the IPMC 8 Send the system wide Geo Adrs to the ROD 6 ROD Power Control and ROD Present 3 Hub LEDs 34 Phys Chips RGMII 12 Switch Chip management: MDC, MDIO, Loop Det 8 MiniPOD management: SDA, SCL, INTR, Reset 1 25 MHz Ethernet Clock 3 I2C Buffer Management: 3x Enables 13 FEX MGT Data Fanout Management: 13x Equalizer Enables 2 40.08 MHz Ref from the Other Hub 2 40.08 MHz Ref to the 40.08 MHz PLL 2 40.08 MHz Logic Clock Input 2 320.64 MHz Logic Clock Input 2 PLL Management: 2x Lock Detects ----- 166 Total number of currently known Hub FPGA Select I/O signals Switch Ethernet Differential Pair and Other Routing: ---------------------------------------------------- In the P23 and P24 backplane connectors I need to escape 48 differential pair Ethernet circuits and run them to 6 blocks of dual Ethernet Magnetics and then to 2 of the 3 Switch chips. This trace routing must not interfere with the FEX traces and fanout just to the North. Routing from P23 P24 to the magnets will use the inner 8 differential pair signal layers (Signal 2:5 and 6:9). The top surface signal layer is not used because of potential problems under the backplane connectors or under the Magnetics. The bottom surface signal layer is not used as it is needed to connect the Magnetics to their Bob Jones RCs. Note that 4 layers are required to escape a given Row in the Advanced Differential backplane connector. Thus a given Ethernet connection must be spread over 4 routing layers. The lower two rows in P24, that are the Base Interface connections to non-existing slots 15 and 16, have been removed from the TE Connectivity 2065657-1 connector that is used in the P24 location. - This allows the traces between TRNS10 and Row 8 of P24 to be routed directly up into P24. - This also allows other traces to TRNS10 to run East of the P10 5:16 pins and then into P24. All of the other P23 P24 Base Interface Ethernet pairs must route out to the West of P23 P24 and then run down into the Ethernet Magnetics.. The Base Interface routing must leave space to escape the Zone 1 connector pins 5:16 (HW Adrs and I2C Bus) to the South and then run East past the fuses and under the ATCA power modules and then run North up to to the IPMC. This is on layers ?? The connections to the RCs the Bob Smith Terminations are run on the bottom surface signal layer Signal 10. Doing that eliminates most of the vias to reach these RC components. The only vias required in all of this RC routing are for the Ground connections to the side of Magnetics modules. Escaping P23 P24 there will be 6 pairs of traces running side by side on each of 8 layers (Signal 2:5 and 6:9). At 2.00 mm per pair total ( 0.40 mm trace C to C and 1.60 mm pair C to C) this will take 12 mm in the North South direction. Note that throwing the 1 oz layers Signal 11 and 12 does not help much as you still need 5 pairs side by side and things are completely mixed up. PCB Layers used to run from the Ethernet Magnetics to the P23 P24 connectors are shown in the following along with the approximate X location of the Eastern vertical trace of the differential pair in the area between TRNS7 and P24 and the pair's central Y value in the area under the magnetics: P24 Row 8 A,B Signal 6 BI Ch 14 X => 263.2 Y = 33.1 36.1 P24 Row 8 C,D Signal 7 P24 Row 8 E,F Signal 8 P24 Row 8 G,H Signal 9 P24 Row 7 A,B Signal 2 BI Ch 13 X = 260.6 P24 Row 7 C,D Signal 3 P24 Row 7 E,F Signal 4 P24 Row 7 G,H Signal 5 P24 Row 6 Signal 6:9 BI Ch 12 X = 260.6 Y = 38.0 P24 Row 5 Signal 2:5 BI Ch 11 X = 258.7 P24 Row 4 Signal 6:9 BI Ch 10 X = 258.7 Y = 39.9 42.8 P24 Row 3 Signal 2:5 BI Ch 9 X = 256.8 P24 Row 2 Signal 6:9 BI Ch 8 X = 256.8 Y = 54.6 57.6 P24 Row 1 Signal 2:5 BI Ch 7 X = 254.9 P23 Row 10 Signal 6:9 BI Ch 6 X = 254.9 Y = 59.5 P23 Row 9 Signal 2:5 BI Ch 5 X = 253.0 P23 Row 8 Signal 6:9 BI Ch 4 X = 253.0 Y = 61.4 64.4 P23 Row 7 Signal 2:5 BI Ch 3 X = 251.1 Ethernet Magnetics RC Components Traces Signal 10 Bottom With the Switch pin #1 in the SE corner the main other trace routing requirements are (Switch "C" example): East side pins 1:64 1 LEDP29 to Front Panel 9 HW_FWDG_EN to jumper R2x03 to 3V3 12 LED_MODE_0 to jumper R2x04 to Ground 13 LED_MODE_1 to jumper R2x05 to 3V3 18 CPU_EEPROM_SEL to jumper R2x06 to Ground 36 TRST to jumper R2x07 to Ground 58 LOOP_DETECTED to R2x23 and then FPGA 59 ACTIVATE_LOOP_DET to R2x22 and then FPGA 61 MDIO to R2x20 and then FPGA 62 MDC to R2x21 and then FPGA North side pins 65:128 Two ports route East to the backplane magnetics 96 GPHY2_RDAC to R2x02 and then Ground Two ports route West to Switch B and Front Panel RJ1 West side pins 129:192 160 SS to R2x15 and then EEPROM Chip Select 161 MISO to R2x18 and then EEPROM Data Out 163 SCK to R2x16 and then EEPROM Serial Clock 164 MOSI to R2x17 and then EEPROM Data In 168 LEDP0 170 LEDP1 172 EN_GREEN to R2X08 and then 3V3 174 LEDP4 174 LEDP5 178 LEDP8 179 LEDP9 182 EPROM_TYPE_1 to R2x09 and then 3V3 184 LEDP12 185 LEDP13 186 LOOP_DET_ENB to R2x10 and then 3V3 189 LEDP16 190 LEDP17 South side pins 193:256 194 LEDP20 195 LEDP21 196 DIS_IMP to R2x11 and then 3V3 198 LEDP24 199 LEDP25 Two ports route East to the backplane magnetics 228 GPHY2_RDAC to R2x01 and then Ground Two ports route East to the backplane magnetics 256 LEDP28 On top of Switch "C" has 2 ports go East, 2 ports go West, and there is R2x02 RDAC. Switch "A" is the same except that on top it has at max traces from 4 ports routing next to each other. On the East Switch "C" has 2 ports routing down, 9 resistors or jumpers, 1 LED trace to the front panel, and 4 traces to the Hub FPGA. Switch "A" is the same. On the West Switch "C" has the EEPROM and its 4 resistors, 3 other jumpers, and 10 front panel LED traces. Switch "A" is much the same. On the South Switch "C" has 5 front panel LED traces, 1 jumper, the RDAC resistor, and 4 ports routing East to the backplane. Switch "C" also has the 4 ports from Switch "A" running South of it. Start with the 2 ports on the North edge of Switch "C" to prove that they can route East and then down to the magnetics with enough clearance for the SW most FEX Fanout signal (which is not yet routed). The two ports from the top that route down the East side and then run to the backplane magnetics use only 4 layers: Signal 2-5. This leaves Signal 6-9 available for East-West routes through the Switch Chips, e.g. for the Management and Loop Detect runs to the FPGA. Power Planes vs Traces for the Swtich Chips: As noted above the routing of the ethernet traces from the backplane connectors to the magnetics is on layers: Signal 2:5 and Signal 6:9. Can these layers also be used to route the ethernet traces from the magnets to the switch chips ? Recall that Signal 5 and Signal 6 are used for both traces and fills. Is either Signal 5 or Signal 6 needed for a fill under or near the Switch chips ? - Signal 5 is OK for traces near/used the Switches as in this area it is only used for a 2V5 finger to the clocks. - Signal 6 is used for BULK_3V3 - but near and under the Swtich chips the BULK_3V3 can be moved to Signal 11 - Signal 12 is used for the SWCH_1V2 near and under the Switch chips and the Phys chips. But we also need a separate AVDDL fill under each Switch chip. AVDDL is an LC filtered version of the SWCH_1V2 power rail that feeds about 20 pins on each Switch and has a large number of bypass caps. - The fills for AVDDL are on Signal 6 and this is only directly under the chips and pokes out along the Top edge to pick up if feed inductor and big bypass caps. - The fill for SWCH_1V2 is on Signal 12. - The fill for BULK_3V3 is on Signal 11. It is moved there from its normal location on Signal 6. We can not have the BULK_3V3 Fill on Signal 6 because we also have traces on Signal 6. So Signal 2:5 and Signal 6:9 are all used to route the ethernet traces from the Magnetics to the Swtich chips with a lot of care about the location of traces on Signal 5. - The Magnetics to Switch Ports 4,5 on the Top edge route on Signal 2:5. - The Magnetics to Switch Ports 0:3 on the Botton edge route on Signal 2:5 and Signal 6:9. - Switch Port 6 on the Top edge routes to the front panel RJ45 Magnetics on some combination of Signal 7,8,9,(10). Note that Signal 6 is not used. Signal 7,8,9 are used to run West to the RJ45 connectors as they are also the layers that are block the escape from the P10 backplane connector pins 5:16. The intent is that this enables P10 pins 5:16 and a lot of the Switch chip LED drive signals to route up to the IPMC and front panel LEDs on Signal 1,2,3,4 (but note not 5) in one one continuous run as this path is not blocked by the Switch chip to front panel RJ45 etherent traces. - Switch Port 7 on the Top edge routes to the coupling capacitors to Switch "B" on Signal 2,3,4 and maybe 1 (but not not on Signal 5). This allows the Switch "A" RJ45 traces to cross over the Switch "C" Capacitor Coupling to "B" traces with no layer changes and still this use of the upper signal layers does not block the routes from P10 or the Switch LED pins. Summary of Signal Layers used in the vicinity of the Switch Chips: - Switches to Rear Magnetics Signal 2:5 and Signal 6:9 - Rear Magnetics to Backplane Signal 2:5 and Signal 6:9 within Zone 1 P10 only Signal 6:9 - Zone 1 (P10) to IPMC Signal 1:4 (and 5 in places) - Switch "A" and "C" to RJ45 Mag Signal 6:9 - Magnetics to Front Panel RJ45s Signal 7:9 - FP Magnetics to its RCs Signal 10 - "A" to the A-B Coupling Caps Signal 7:9 - "C" to the C-B Coupling Caps Signal 2:5 - "B" to the Swch Coupling Caps Signal 7:9 - "B" to the FP RJ45 Magnetics Signal 6:9 - Routes North through the FP Signal 2:4 (maybe 1 in places) RJ45s and their Magnetics Signal 7:9 are blocked e.g. Zone 1 and Swch LEDs maybe Signal 6 in places - Switch to FPGA Signal - Clock to Backplane Signal 1 - Combined Data to Backplane Signal 10 FEX Data Fanout to Hub FPGA MGT Receiver Inputs: ------------------------------------------------ All of this GHz routing must be on three layers Signal 2:4. - Signal 6:9 can not be used as they carry the FEX Data into the Fanout and carry the FEX data to the ROD and these signals must cross over the FEX Data runs to the Hub's FPGA. - Signal 1 and 10 can not be used as they carry the Clock and Combined Data to the Backplane and these signals must cross over the FEX Data runs to the Hub's FPGA. - Signal 5 can not be used as it is needed for the FPGA's BULK_1V8 power feed. This is not "flow through" routing in the FEX Data Fanout. I gave the flow through path to the feed to the ROD so that I could meet the mapping requirements of Ed and Ian. The feed to the Hub's FPGA will be in blocks of 8 channels. Within a block the FEX Data Fanout Channel Numbers will run backwards, e.g. start at 8 and run down to 1. As planned this requires 3 runs between Rows of FEX Data Fanout Chips. This matches the FEX Fanout Backplane Input and the FEX Fanout feed to the ROD. And yes, this works for the Top Row with its special 10 FEX Data Fanout Chips. The FEX Data feeds to the Hub's FPGA Routing Groups are: North South most Route most Route Special in Group in Group Top Most -------- -------- Group Fanout Ch Num 65 66 67 68 69 70 71 72 73 74 Routes on Signal 3 2 4 3 2 4 3 2 4 3 North South most Route most Route in Group in Group -------- -------- Fanout Ch Num 57 58 59 60 61 62 63 64 Routes on Signal 2 4 3 2 4 3 2 4 Fanout Ch Num 49 50 51 52 53 54 55 56 Routes on Signal 3 2 4 3 2 4 3 2 Fanout Ch Num 41 42 43 44 45 46 47 48 Routes on Signal 4 3 2 4 3 2 4 3 Fanout Ch Num 33 34 35 36 37 38 39 40 Routes on Signal 2 4 3 2 4 3 2 4 Fanout Ch Num 25 26 27 28 29 30 31 32 Routes on Signal 3 2 4 3 2 4 3 2 Fanout Ch Num 17 18 19 20 21 22 23 24 Routes on Signal 4 3 2 4 3 2 4 3 Fanout Ch Num 9 10 11 12 13 14 15 16 Routes on Signal 2 4 3 2 4 3 2 4 Fanout Ch Num 1 2 3 4 5 6 7 8 Routes on Signal 3 2 4 3 2 4 3 2 Normal Bottom Most Group Routing Notes: Within a Group, the Southern most Differential Pair routes to the MGT Receiver with its Input pins the furthest to the West of all of the MGT Receivers that are used by that Group. Within a Group, the Northern most Differential Pair routes to the MGT Receiver with its Input pins the furthest to the East of all of the MGT Receivers that are used by that Group. Vertical Trace Mat to the West of the Phys Chips: ------------------------------------------------- There is a serious routing problem to the West of the 2 Phys chips. There are about 133 signals that must route vertically through this area area. These signals everything from low current power rails and LED signals to clocks and 1000 Base-T ethernet. These signals are listed near the end of this section. There are a number of complicating factors in routing these vertical traces through this area: 1. There is a pinch in the horizontal width available for these 133 traces because of the required notch for the front panel RJ45 connectors. 2. All of these 133 signals must run to the West of the Phys Chips and the Flash configuration Memory. The Flash Configuration Mentory is expected to require all routing layers to reach in to the 14th ring of BGA pads. 3. All of these traces must route under the front panel RJ45 connectors and their ethernet magnetics transformers. 4. The press-fit through hole pins for the front panel RJ45 connectors will need lots of relief to not result in broken traces during the press-fit operation. 5. This same area needs East-West traces between the front panel RJ45 connectors and their magnetics. These traces are run on Signal: 7, 8, and 9. 6. In this area Signal 10 is blocked under the ethernet magnetics by the connections to the 18 RC components that are associated with each dual transformer. Signal 10 is blocked under the RJ45s by LED resistors 7. Just to the North of this area high speed layers Signal 2 and 3 (and maybe 4) are needed for the differential runs to the Rec and Trans MiniPODs. 8. Some of these signal like the LED signals do not require special routing considerations but many of these signals have special requirements, e.g. the moderate current IPMC_3V3 and CNST_5V9 have width requirements the 25 MHz clocks must have clean low noise routes the ethernet differential pairs have controlled impedance and cross-talk requirements. 9. As currently laid out Signal 5 and 6 are not available because in this area they are used for the Isolated +12V distribution. One way or another the rather high current Isolated_12V rail must route North through this same narrow constricted section. Clearly points 5, 6, 7 are currently in conflict and the layers used for East-West routes in this area must me minimized. Once this vertical mat of traces reaches the North side of the MiniPODs then many of these traces must branch out to the East or West. This will require a lot of cross overs with their vias which will further constrict the vertical mat. A way to make use of Signal 1 needs to be found even though I would like to stay away from Signal 1 because of the metal case around the RJ45 connectors. In this area there are about 30 vertical routing channels for narrow width traces in addition to the vertical ethernet differentail pair area to the East of the magnetics. There are about 95 non-ethernet vertical traces so this will require about 4 vertical routing layers to have any chance of fitting this all in. List of vertical signals to the West of the 2 Phys Chips: - JTAG and 2 Config DONE about 7 - I2C Sensor Bus to Front Panel 2 to Switch DCDC_5 2 - I2C Management Bus to the Power Entry 2 - Power Entry Module Alert Signal 1 - Enable signal to the Isolated_12V supply 1 - Always On 5 Volt supply aka CNST_5V0 1 wide - IPMC_3V3 supply from Power Entry 1 wide - Switch DCDC_5 supply, On/Off, PG, Alert, Mon. 4 - Zone 1 8x HW Adrs, 4x IPMBUS 12 - ATCA Switch and required LED 2 - 25 MHz Clk: 2x Phys, 1x FPGA 3 clean - Switch Chips: LEDs A 16 B 12 C 16 44 MDIO/MDC A 2 B 2 C 2 6 Loop Det/En A 2 B 2 C 2 6 - Ethernet: ROD, IPMC, total 16 pairs Phy U21, Swch "B" Port 5 - Phys LEDs 4 - ROD Front Panel RJ45 LEDs 2 - Shelf Ground 1 + ------------ Estimated Number of Number of Vertical Traces: 133 Plan for the Vertical Trace Mat as of 5-May-2016: - A main concern is, will the Phys chips and Config Flash need to move East to make space for the VTM ? Even the FPGA may need to move East. - All of the East-West traces in the area of the, e.g. Magnetics to RJ45 and MiniPOD to FPGA, run on Signal 1, 2, 3. - The Vertical Trace Mat runs on Signal 7, 8, 9 with some use of 5 and 6 were that can be accomidated. - Try to save Signal 11 and 12 for the Isolated_+12V but if needed give that up and use discrete wires for that power net. - Start at the West edge of the VTM with the 44 Switch LED traces. Pack these tight with 0.16 width and 0.40 mm spacing center to center or where needed 0.15 mm width on 0.30 mm center to center. 0.16 width is about 65 mOhm per cm which is not a problem considering the LED series resistors of about 220 Ohm. - Come down from the LEDs with the Switch LED traces is whatever order allows the easyiest escape from the area of the LEDs and IPMC connector. Breadout the individual Switch LED traces from this bundle in the area South of the Switch chips. The area under the ATCA Power Modules can be used for this. - For the 44 Switch LEDs, swap the initial setup of the LED resistors from resistor between LED and Vcc to resistor between LED and Switch LED Control Pin. Move these LED series resistors to the area South of the Switch chips, i.e. make better use of the area under the ATCA power modules. The intent is to give more space for IPMC Socket routing and to make these long traces slightly quieter as they run under the RJ45s, Ethernet Magnetics, and MiniPODs. - The 44 traces for these Switch LEDs will start at the West edge on Signal 9 and work East. The intent is to come down through the pinch and then make the bend to the East under the Switch chips. The intent is to keep these Switch LED traces on 2 layers max and thus other layers can be used for traces that must go East above the pinch without needing any via cross overs. Routing to the Input Fuses F1 through F6 Rev. 24-Jan-2017 ------------------------------------------------------------- The Power Input and Power Return fuses will typically need to carry about 5.2 Amps during normal Hub Card operation. 5.2 Amps times 48 Volts is a nominal 250 Watts. They will probably be fused for 8 or 10 Amps so these traces really need to be able to support 10 Amp operation. The current drain of the Enable pins is only a few mA and they will probably be fused at 500 mA or something like that. F1, F2 Enable F3, F4 Power Return F5, F6 Input Power Negative Recall the Current setup of the Input Fuses: ------- F1 Conn: Sig_6 total 1 oz F1 Modl: Sig_6 total 1 oz F2 Conn: Sig_6 total 1 oz F2 Modl: Sig_6 total 1 oz F3 Conn: Sig_4, Sig_5, Sig_9, ---, Sig_12 total 3 oz F3 Modl: Sig_4, Sig_5, Sig_9, ---, --- total 2 oz F4 Conn: Sig_4, Sig_5, Sig_9, Sig_11, --- total 3 oz F4 Modl: Sig_4, Sig_5, Sig_9, ---, --- total 2 oz F5 Conn: Sig_1, Sig_2, Sig_3, Sig_7, Sig_8, Sig_11, --- total 3 1/2 oz F5 Modl: ---, Sig_2, Sig_3, ---, ---, ---, Sig_12 total 2 oz F6 Conn: Sig_1, Sig_2, Sig_3, Sig_7, Sig_8, Sig_11, --- total 3 1/2 oz F6 Modl: ---, Sig_2, Sig_3, Sig_7, Sig_8, ---, --- total 2 oz Signal_10 is used for the Chassis Ground and for connecting the pre-charge resistors to the Zone 1 Connector. There are no options to use Signal_10 to carry any of the Fuse traces. Options for what could be added or changed: Sig_1 could also carry: F3 to Zone 1 Connector and F1 and/or F2 to Module Sig_2 could also carry: --- Sig_3 could also carry: --- Sig_4 could also carry: F6 to Zone 1 Connector Sig_5 could also carry: F6 to Zone 1 Connector Sig_6 could also carry: F5 to Zone 1 Connector and F6 to Zone 1 Connector Sig_7 instead could carry: F4 or F5 to Module Sig_8 instead could carry: F5 to Module Sig_9 could also carry: F6 to Zone 1 Connector Sig_10 could also carry: F6 to Zone 1 Connector Sig_11 could also carry: F3 and F4 to Module NO becaue of Fills Sig_12 could also carry: F6 to Zone 1 Connector, F3 to Module NO because of Fills Would like to get the Signal_6 1 oz layer out of the business of carrying the Enable signals and into the high current business of the power input or power return. - Can move F1 Conn and Modl to Signal_1. - Can move F2 Modl to Signal_1. - Need home for F2 Conn - could be as simple as Signal_2 Then the high current stuff that can fit onto Signal_6 is: - F5 or F6 to Module - F3 to Module (requires reroute of DCDC5 control signals) - F3, F5, F6 to Zone 1 Connector This gives the NEW setup of the Input Fuses: Rev. 24-Jan-2017 ----- F1 Conn: Sig_1 total 1/2 oz F1 Modl: Sig_1 total 1/2 oz F2 Conn: Sig_9 total 1/2 oz F2 Modl: Sig_1 total 1/2 oz F3 Conn: Sig_4, Sig_5, Sig_6, Sig_9, ---, ---, Sig_12 total 4 oz F3 Modl: Sig_4, Sig_5, Sig_6, Sig_9, ---, ---, --- total 3 oz F4 Conn: Sig_4, Sig_5, ---, Sig_9, ---, Sig_11, --- total 3 oz F4 Modl: Sig_4, Sig_5, ---, Sig_9, Sig_10, ---, --- total 2 1/2 oz F5 Conn: Sig_1, Sig_2, Sig_3, Sig_6, Sig_7, Sig_8, Sig_11, --- total 4 1/2 oz F5 Modl: ---, Sig_2, Sig_3, ---, ---, Sig_8, ---, Sig_12 total 2 1/2 oz F6 Conn: Sig_1, Sig_2, Sig_3, Sig_6, Sig_7, Sig_8, Sig_11, --- total 4 1/2 oz F6 Modl: ---, Sig_2, Sig_3, Sig_6, Sig_7, ---, ---, --- total 2 1/2 oz High-Current Routing ATCA Power Entry to ISO_12V Rev. 25-Jan-2017 --------------------------------------------------------------------- This is just to document which PCB layers are used to carry the high current from the output of the ATCA Power Entry Module to the input of the ATCA ISO_12V Module. ISO_12V Module PCB Signal Layers Input Pin Carrying this Connection --------- -------------------------- 3 Signal: 3, 4, 5, 12 3.0 oz 1 Signal: 2, 6, 7, 9, 11 3.5 oz