Hub-Module Virtex FPGA --------------------------- Original Rev. 12-Mar-2015 Current Rev. 17-Feb-2016 The UltraScale Virtex device on the Hub Module is a: XCVU125-1FLVC2104I This is speed grade "1", i.e. the normal common slowest speed grade and it is the "Industrial" temperature range which is the common temp range for most of these UltraScale parts. This part has: 40 GTH Transceivers and 40 GTY Transceivers. These are spread across 2 SLRs with 20 of each kind of transceiver in each SLR. This part has 7 HP Select I/O Banks with 52 I/O signals in each. 4 of the HP banks are in SLR #0 and 3 of the HP banks are in SLR #1. This part also has 2 HR Select I/O Banks with 26 I/O signals in each. Both of the HR banks are in SLR #0. The Hub Module uses both of the HR Banks for 3V3 I/O and it uses most of the signals in these Banks. The FLVC2104 package has 2104 pins in a 1mm by 1mm square array with 46 pins on each side and 3 pins missing at each corner. This is a No-Lead package. FPGA Configuration: ------------------- The Hub's UltraScale Virtex FPGA is configured in Master BPI mode from a Micron MT28GU01GAAA1EGC-OSIT NOR Flash memory. This method of configuration requires pins in both the special Bank #0 and most of the pins in Select I/O Bank #65. Drawing #36 shows the details of this configuration setup. The MT28GU01GAAA1EGC-OSIT Flash memory holds 1 Gb of data. The XCVU125 FPGA requires 401,441,280 bits to configure so the Hub Module can hold 2 versions of FPGA Firmware. FPGA JTAG Connection: --------------------- The Hub Module provides a front panel JTAG connection via its J2 "Access Connector". A 1V8 version of this JTAG string is routed to the Hub's FPGA as shown in drawing #33. FPGA System Monitor Reference and Connections: ------------------------------------ The hub provides an external precision reference and filtered power for the FPGA System Monitor. This is shown in drawing #25. The IPMC's Sensor I2C bus is routed to the slave I2C port to the System Monitor as shown in drawing #37. FPGA MGT Transceivers: ---------------------- The Hub design uses all 80 MGT Receivers and 29 of the MGT Transmitters. Note that this FPGA's MGT transceivers are shared across both of its SLRs. The assignment of the MGT transceivers is listed in the file: hub_0_ab_fpga_mgt_transceiver_usage.txt The connections to the GTY and GTH Banks are shown in drawings #22 and #23. FPGA RGMII Ethernet Base Interface Connection: ---------------------------------------------- The Hub Module FPGA is connected to 2 Micrel KSZ9031RNX Phys chips. These Phys chips provide 10/100/1000 speed ethernet connection between the FPGA and the Switch on This Hub and via the backplane to the Switch on the Other Hub. The Phys RGMII to FPGA connections are made to HP Bank #68. Besides the MACs to run these connections the FPGA firmware may want MACs to run the MDC MDIO management links to the 3 Switch chips. FPGA Clock Sources: ------------------- The Hub's FPGA is provided with the following clocks: 25.000 MHz Ethernet Clock single ended 3V3 to Bank 94 40.08 MHz LHC Clock LVDS Logic Clock to Bank 71 320.64 MHz LHC Clock Cap Coupled LVPECL Logic Clk to Bank 71 8x 320.64 MHz LHC Clock Cap Coupled LVPECL MGT Reference Clk more than for every other MGT Quad 2x 125.000 MHz Ethernet Clock single ended 1V8 level Each Phys Chip returns its 5x multiplied Clk to Bank 68 in the FPGA The Select I/O Signals: ----------------------- The Hub design currently uses about 166 Select I/O signals. Both 1V8 and 3V3 levels are used. The 3V3 levels are from HR Select I/O Banks 84 and 94. The Hub's use of FPGA Select I/O signals are listed in the file: hub_0_ab_fpga_select_io_usage.txt FPGA Power Supply Requirements: ------------------------------- The intent here is to list the full details of this FPGA's power supply and bypass capacitor requirements. Then in the Hub Power Supply Design document only a short summary of these FPGA's power requirements will be presented along with a summary of the power supply requirements of the other components on the Hub Module. UltraScale XCVU125-FLVC2104 Recommended Operating Conditions: VCCINT 0.950 V +- 3.0% VCCINT_IO 0.950 V +- 3.0% VCCBRAM 0.950 V +- 3.0% VCCAUX 1.800 V +- 3.0% VCCAUX_IO 1.800 V +- 3.0% VCCO HR 1.140 V to 3.400 V VCCO HP 0.950 V to 1.890 V VBATT MGTAVCC 1.000 V +- 3.0% MGTAVTT 1.200 V +- 2.5% MGTVCCAUX 1.800 V +- 2.8% VCCINT_IO must be connected to VCCINT VCCAUX_IO must be connected to VCCAUX If VBATT is not used then connect VBATT to either ground or to VCCAUX VCCO_0 must be a minimum of 1.425V during configuration. Quiescent Supply Currents: VCCINT 2875 mA VCCINT_IO 178 mA VCCBRAM 162 mA VCCAUX 373 mA VCCAUX_IO 148 mA VCCO 1 mA (assume per Bank) Expected FPGA Power Supply Current Draws: The following is a very brief summary of Philippe's detailed look at the expected current requirements for the XCVU125 in the Hub Module application with a focus on the GTH GTY requirements. For comparison I have also listed Ed's 16-July-2015 Virtex-5 estimates. Summary: Philippe Full 109 Column #2 Ed's Estimates Port Hub UltraScale Virtex 7 UltraScale ---------- -------------- ---------- Core: 18.28 Amps 17 A 15.5 A 20.77 Amps AVCC: 6.39 20 16.2 10.76 AVTT: 7.89 9 3.96 10.01 AVAUX: 0.43 0.232 0.59 The UltraScale numbers have been upped from the Column #2 in Philippe's note by: Core 2.49A, AVCC 4.37A, AVTT 2.12A, AVAUX 0.16A to account for the 12 additional GTH Transmitters sending out Combined Data. This still needs to be checked in the Power Estimator to verify that all of the GTH/GTY connections were divided up correctly. An apparent big difference wrt the all GTH Virtex-7 is that in the UltraScale GTH/GTY: GTH takes more AVCC than GTY GTY takes more AVTT than GTH The biggest change from what was expected based on older parts is the the UltraScale GTY takes a lot of AVTT power. Per transceiver (both rec and trans running) the current requirements are about: AVCC AVTT AVAUX 1.000V 1.200V 1.800V ------ ------ ------ GTH: 0.126A 0.047A 0.0033A GTY: 0.081 0.341 0.0047 Power Supply Sequencing and Common Supplies: At Power ON: VCCINT / VCCINT_IO then VCCBRAM then VCCAUX / VCCAUX_IO then VCCO Power OFF is the reverse. VCCINT / VCCINT_IO and VCCBRAM can all be powered from the same supply and ramped simultaneously. VCCAUX / VCCAUX_IO and VCCO can all be powered from the same supply and ramped simultaneously. VCCINT and MGTAVCC may be ramped simultaneously. MGTAVCC should ramp before MGTAVTT. No recommended sequencing for MGTVCCAUX. Besides the Quiescent currents listed above the supplies must be able to provide the following minimum currents during power up: VCCINT / VCCINT_IO supply 4397 mA minimum additional current VCCBRAM 200 mA VCCAUX / VCCAUX_io supply 533 mA VCCO supply 54 mA All ramp times are 200 usec minimum and 40 msec max. 3.0 msec is about in the middle 16x from either side. From the "ultrascale pcb design guide" ug583 ByPass Capacitor Requirements for the XCVU125-FLVC2104: VCCINT / VCCINT_IO 2x 680 uFd 3x 100 uFd 5x 4.7 uFd VCCBRAM 1x 47 uFd 1x 4.7 uFd VCCAUX / VCCAUX_IO 2x 47 uFd 4x 4.7 uFd VCCO HR or HP 1x 47 uFd MGTAVCC, MGTAVTT, MGTVCCAUX One 4.7 uFd per Power Group The XCVU125-FLVC2104 has a from the GTH & GTY Guides total of 6 Power Groups. 6 Power Groups includes both the GTH and GTY. There is the same one 4.7 uFd capacitor requirement for both the GTH and GTY transceivers. Notes: VCCINT and VCCINT_IO must be tied together on PCB. VCCAUX and VCCAUX_IO must be tied together on PCB. One 47 uFd capacitor is required for up (to) four HP/HR Banks when powered from the same VCCO voltage. 470 uFd can be used for 680 uFd in a 4 to 3 ratio. Recommended Capacitors: 680 uFd 2917/D/7343 Tant 2.1 nH <40 mOhm T530X687M006ATE018 470 uFd 2917/D/7343 Poly Al 1.5 nH <40 mOhm EEF-GXOD471R 100 uFd 1210 X7R/X5R 1.5 nH <40 mOhm GRM32EE70G107ME19 C3216X6SOG107M160AC 47 uFd 1210 X7R/X5R 1.5 nH <40 mOhm GRM32ER70J476ME20L C3225X6SOJ476M250AC 4.7 uFd 0805 X7R/X5R 1.0 nH <20 mOhm GRM21BR71A475KA73 C1005X5ROJ475M Look at the VCU110 Demo Board for the XCVU190 This is an example of how Xilinx set up a multi SLR FPGA in what I assume is best practices. This demo board uses an XCVU190 FPGA with 3 SLRs. Hub Module FPGA has 2 SLRs. The XCVU190 FPGA has 104 MGT transceivers (52 GTH and 52 GTY) vs the 80 on the Hub's FPGA, i.e. 1.3 times as many. Decoupling Capacitors on the VCU110: CORE: Xilinx: 2x 470 uFd 2V Tant_D, 4x 100 uFd 4V X6S, 8x 4.7 uFd 6.3V X5R Maxim: 12x 100 uFd 4V X6S, 17x 4.7 uFd 6.3V X5R, 26x 47 uFd 6.3V X6S AVCC: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 3x 470 uFd 2V Tant_D, 8x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R, 14x 0.22 uFd 6.3V X6S, 14x 4.7 uFd 10V X5R AVTT: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 3x 470 uFd 2V Tant_D, 10x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R, 14x 0.22 uFd 6.3V X6S AVAUX: Xilinx: 6x 4.7 uFd 6.3V X5R Maxim: 8x 100 uFd 4V X6S, 5x 10 uFd 6.3V X5R 8x 4.7 uFd 6.3V X5R