Hub-0 Next Time List ----------------------- Rev. 17-May-2017 The purpose of this file is to collect in one place all of the things that I wish I had done differently in the Hub Module design. As usual, most of these things that I now wish I had done differently were not recognized until I had cards back from the assembly house and had worked with them for a while. 1. I should have put tick marks on all of the high pin count components every 5 or 10 pins. 2. I need to change the thickness milling from the back side of the card to include milling the area where the Front Panel Handles mount so that the area around where the Handle screw goes through the card meets the maximum card thickness specification for the handle, which is 2.40 mm with an absolute maximum of 2.60 mm. The actual space available in the handle itself appears to be about 2.7 mm. 3. If the IPMC is not installed then there are no pull-up resistors on the Sensor I2C Bus, e.g. to run this bus from the Front Panel Access Connector (unless the I2C "pod" that you are using includes pull-ups). 4. Just north and south of the U1 FPGA I could have mounted more large bypass capacitors on just the top surface of the card. These could not have been "high frequency" bypass because its is not possible to put vias close to these locations - but there is space for the component bodies to fit. Some of this space has the height restriction of the FPGA heat sink fill block but other areas could have accommodated components up to 8 mm high of so. The electrical connections to any additional bypass capacitors in this area would need to be from vias perhaps 20 mm away but that would have been more or less OK for some bulk tantalum or aluminum polymer capacitors. All space in this area should have been used. No space is available on the bottom surface because of the Combined Data differential trace pairs in this area.