Design Rule Checks on the Hub Module -------------------------------------- Initial Rev. 6-Jan-2017 Current Rev. 17-Feb-2017 This file contains notes about runs of the Design Rule Checker on the Hub Module. In general the Design Rule Check is run from Layout on the Traces part of the Hub Design. Check --> Traces --> Check_Traces A typical setup is: Entire Board Remove Trace Violations -- NOT Check Net Agains Itself -- NOT Check Trace Widths Less Than Net Rule -- NOT Check All Thermal Ties on Pins and Vias -- NOT Check Same Net Pad to Pad Clearances -- NOT Remove Deplicate Routing -- NOT Check Pas connectivity with fill hatch - NOT Report Off Grid Vias as -- No Checking Report Uncovered Plated Drill Holes as -- Warning Runs on Traces File 658 on 6-Jan-2017: ---------------------------------------- These DRC runs were made with the Design Rules: Default Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.10 0.30 Trace 0.13 0.20 0.17 Fill 0.25 0.21 0.30 0.50 Quad_LED Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.10 0.30 Trace 0.07 0.20 0.17 Fill 0.25 0.21 0.30 0.50 Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.10 0.30 Trace 0.13 0.20 0.17 Fill 0.35 0.35 0.35 0.50 ---------------------------- Check Traces Options ---------------------------- Note: Same Net Checking: OFF (from: Idea/Util/Lay Template 13) Note: Off Grid Via Checking: OFF (from: Idea/Util/Lay Template AA) Note: Same Net Pad to Pad Clearance Checking: OFF (from: Idea/Util/Lay Template B7) Note: Trace/Via/Routing Keepout Clearances: ON (from: Idea/Util/Lay Template B8) ---------------------------- Check Traces Messages --------------------------- Warning: Two vertices are coincident from ( 241.6,8 ) to ( 241.6,6.75 ) on layer (PHYSICAL_11). (from: Idea/Util/Trace Check 13) Warning: Two vertices are coincident from ( 32.5,182.85 ) to ( 32.5,182.8 ) on layer (PHYSICAL_13). (from: Idea/Util/Trace Check 13) Warning: Two vertices are coincident from ( 231.7,179.5 ) to ( 231.7,178.6 ) on layer (PHYSICAL_4). (from: Idea/Util/Trace Check 13) ---------------------------- Check Traces Summary ---------------------------- Note: Checked: 84437 Segments, 2927 Vias and 0 Fill_Areas (from: Idea/LAYOUT/ROUTE E6) Note: Routing violations = 0 (from: Idea/LAYOUT/ROUTE 21) Note: Odd Angle Segments = 48010 (from: Idea/LAYOUT/ROUTE F1) Note: Unroutes = 1147 (from: Idea/LAYOUT/ROUTE E2) Note: Unfinished Connections = 352 (from: Idea/LAYOUT/ROUTE EB) Note: Unplaced components = 0 (from: Idea/LAYOUT/PLACEMENT2 67) Note: Off-board components = 0 (from: Idea/LAYOUT/PLACEMENT2 68) Runs on Traces File 685 on 16-Jan-2017: ----------------------------------------- Made a run today, before putting the Fills back into the design, with the same design rules as shown for the runs on 6-Jan-2017. I have the same 3 coincident vertex warnings which are really un-needed duplicate routing that I forgot to take out. Summary of the results: ---------------------------- Check Traces Summary ---------------------------- Note: Checked: 84451 Segments, 2932 Vias and 0 Fill_Areas (from: Idea/LAYOUT/ROUTE E6) Note: Clearance Errors = 0 (from: Idea/LAYOUT/ROUTE E9) Note: Via Off Grid Warnings = 504 (from: Idea/LAYOUT/ROUTE A8) Note: Odd Angle Segments = 48010 (from: Idea/LAYOUT/ROUTE F1) Note: Unroutes = 1147 (from: Idea/LAYOUT/ROUTE E2) Note: Unfinished Connections = 355 (from: Idea/LAYOUT/ROUTE EB) Note: Unplaced components = 0 (from: Idea/LAYOUT/PLACEMENT2 67) Note: Off-board components = 0 (from: Idea/LAYOUT/PLACEMENT2 68) Runs on Traces File 691 Durand on 21,22-Jan-2017: --------------------------------------------------- Start a sequence of multiple runs to explore where the clearance violations start. This traces file is 685, incremented to 690, and then with un-official fixes to the 3 coincedent via warnings and the added high current input trace on Signal_12. Make an initial run with the DRs shown at the top of this file. This gives zero errors. Explore the High-Speed Diff_Pair Design Rules: In the Diff_Pair DRs, set trace-trace to 0.18. This should blow up the MegArray dual-track routing. Now 525 clearance errors - all within the MegArray dual-track routing. Recall that all "segments" that are in violation get counted so although there are only about 37 trace pairs per MegArray that are in violation this flufs up to 525 segments. Recall the expected Diff_Pair clearances: 0.40 mm ctc spacing - 0.14 mm width = 0.26 mm clearance 0.30 mm ctc spacing - 0.13 mm width = 0.17 mm clearance Now set Diff_Pair DRs to trace-trace of 0.25 mm. The expectation is that this should only pickup additional segments within the MegArray dual-tracks - but that there should be no new traces that are in violation. Find 988 errors as now all of the escapes from the 2nd ring of MGT pins on the FPGA are in violation. Study this layout and see that I should expect a clearance of about 0.226 mm in this area. So setup for 0.22 Now set Diff_Pair DRs to trace-trace of 0.22 mm. As expected we are back down to the 525 violations all dual-track within MegArrays. Now set Diff_Pair DRs to trace-trace of 0.27 mm. This should blow up all of the high-speed differential pair routing. Yes, see 8922 violations in what looks like all vert and horz high speed diff pairs. Recall that for the standard high-speed diff pairs that the air gap in the vert and horz pairs is 0.260 mm and in the 45 degree sections the air gap is 0.283 mm. High-Speed Diff Pair Trace to Trace Summary: MegArray dual-track air gap should be 0.17 mm. It is OK with DR of 0.17 and falls apart at 0.18 mm. Escape from FPGA 2nd ring MGT pins includes a section with an air gap section of 0.226 mm. It is OK with DR of 0.220 but has fallen apart with DR of 0.25 mm The normal vert and horz high-speed diff pair sections should all have an air gap of 0.26 mm. It's all OK with 0.25 mm DR and all falls apart with 0.27 mm DR. Now study the High-Speed Diff Pair to Via Clearance. Increase this DR to 0.25 mm and all is OK. Increase to 0.30 mm all see 476 violations. All appear to be at the Fanout Chip Input to the center termination Via. Calculate this clearance to be about 0.254 mm. Try with a to Via DR of 0.27 mm. Still see all of the Fanout Chip Input Terminator Center Vias - just fewer segments this time. Try with a Trace to Via DR of 0.26 mm and it runs without error. Now stufy the High-Speed Diff Pair Via to Via Clearance. I do not expect this to ever be an issue in the design. So right away increase this DR to 1.00 mm and see zero errors. So leave High- Speed Via to Via DR at 1.00 mm. Now study the High-Speed Diff Pair trace to Pin Clearance. I expect this to fall apart very soon - both under the FPGA and under the MegArraies. Increase the High-Speed Diff Pair Trc to Pin DR to 0.14 mm and see Zero errors. Set trace to pin DR to 0.15 and see 655 errors. These are all under the MegArrays and the FPGA and I think they include all of the High-Speed Diff Pairs under these devices. Everything else still looks clean. Somewhat randomly increase this DR to 0.20 mm and see both more segments under the FPGA and MegArrays in error and also see the Fanout Chip pin 16 Gnd to pin 1 Input in violation. Note that the Gnd trace that runs from pin 16 Gnd to the center pad is 0.01 mm closer to pin 1 (input signal) than the center pad is. This clearance is 0.18 mm. So try a trace to pin DR of 0.17 mm and see only 685 in violation and none of these are in the MGT Fanout cells themselves. So this makes sense and we can do normal DRC runs testing for 0.14 mm clearance. High-Speed Diff Pair Via to Pin increase to 0.50 mm and see 278 violations all between the input common the the pins close to it on the Fanout chip part. Try 0.20 Via to Pin and see zero violations. Try 0.30 Via to Pin and see zero violations. Try 0.40 Via to Pin and see 148 violations to FO Chip center input via. Try 0.35 Via to Pin and see zero violations. Try 0.37 Via to Pin and see zero violations. Try 0.39 Via to Pin and see 148 violations to FO Chip center input via. Try 0.38 Via to Pin and see zero violations. High-Speed Diff Pair Pin to Pin increase to 0.50 mm and see Runs on Traces File 693 on 24-Jan-2017 night: ------------------------------------------------- Working on a combination of High-Speed Diff Pair and Default 0.5 Diff Pair 0.38 1.0 Violations 1 contains 7 trace to trace 0.11 0.26 0.21 default type 0.5 Default This was the setup for above 0.1 0.3 0.11 0.2 0.2 Changing the default net type trc to trace form 2.0 to 0.18 gets rid of these 7 violations. Note that a 0.50 mm trace into a FPGA pin and then a 0.13 mm trace running next to it has a clearance of only 0.185 mm. but not all of the above are this. The other violation is really on Phys_10 at 41.0 36.5 <-- NEED TO FIX net ipmbus_b_sda this get reported 3 times. Crank HS Diff Pir trace to pin to 0.12 zero error to 0.13 404 errors all in the dual-track routing under the MegArray and these are not really real as this is trace to pad violation for pads that do not exist. crank this to 0.14 mm trace to pin clearance still 404 error crank this to 0.15 mm trace to pin 655 error the ones mentioned above and now also the ones expected under the FPGA. Again these under FPGA errors are trace to non-existant pads. Runs on Traces File 693 on 25-Jan-2017: ------------------------------------------ To see Zero errors from the High-Speed Diff Pair: Pin 0.50 Diff Pair Via 0.38 1.00 Trc 0.12 0.26 0.21 at Trc-Pin of 0.121 turn on just the 0.13 Sig_10 dual-track into MegArray at Trc-Pin of 0.122 turn on all dural-track routing into MegArray at Trc-Pin of 0.15 turn on MGT to pads under FPGA Note that these 3 violations types are to pads that do not exist and that all of them are as expected. at Trc-Trc of 0.22 turn on all of the dual-tracks as expected To see Zero errors from the Default Nets: Pin 1.00 Default Nets Via 0.20 0.35 Trc 0.12 0.20 0.185 at Via-Via of 0.36 turn on about 51 via under Switches and Phys Chips that are 0.65 mm land vias spaces 1.00 mm. at via-via 0.40 mm this is 53 violations I believe still all Switch and Phys Chips. at Trc-Via of 0.21 turn on all of the Switch Chip Signal_1 route outs that use 0.20 mm wide traces and are packed in between 0.60 land Vias, i.e. all of the Ethernet Line Circuit pins on the Switches. 0.21 --> 183 Violations 0.22 --> 188 V 0.23 --> 221V 0.25 --> 402 V I think as you go up, e.g. at 0.23 mm, that most of these violations remain in the area of the Switch and vias outside of the NW corner of of FPGA, a few with Phys Chips, some in the IPMC escape, some in the horizontal mat of traces (LED and such) south of the Switch chips, and one by each Clock Fanout. at Trc-Pin of 0.13 turn on 332 Violations Gnd to Dual-Track in MegArray at 0.14 turn on 408 Viol: MegArray, Config PROM, and one under FPGA 92.5, 151.5 to 101.3, 151.5 maybe Sig_9 <-- NEED TO FIX Note that the rest of FPGA is clear and that the Config PROM is 0.60 land pads with 0.13 mm trace, i.e 0.135 DR at 0.15 turn on 3234 Violations: I think it is all FPGA, Config PROM and MegArray - the Switches, Phys, MGT Fanout, IPMC, Backplane, Clocks, PowerSupplies all look clear. at 0.125 238 Violations all dual-track except Sig_6 MegArray at 0.123 238 V the same at 0.121 6 Violations Just the Sig_10 dual-track into MegArray at Via-Pin of 0.21 turn 148 Violations all in MGT Fanout I think at 0.23 have 222 Violations all in MGT Fanout I think at 0.25 have 264 Violations all in MGT Fanout I think at Trc-Trc of 0.19 turn on 7 Violations, 4 under FPGA on Sig_10 consisting of 0.50 and 0.13 spaced 0.50 as noted last night of and the stupid one at 41.0 36.5 Phys_10 as noted last night once this is fixed it should be clear at 0.185 mm Trc-Trc at 0.20 still 7 Violation at 0.21 554 Violation - the Switches light up and just one new one under the FPGA it is the wide SysMon Pow and Ref on Sig_2 which could each be moved by 0.05 mm. at 0.22 566 Violation - no new obvious classes at 0.23 705 Violation - turn on some of the dense buses e.g. LED south of Swithces and vertical mat e.g. overall adrs to ROD, IPMBUS_B_SCL To see Zero errors from the Quad LED Nets: Pin 1.00 Quad LED Net Via 1.00 1.00 Trc 1.00 1.00 1.00 I think that currently there are no nets in the design with the QUAD_LED attribute. At one time this net type was used to allow these nets to get close to the mechanical holes for the LED Light-Pipes. Runs on Traces File 724 on 13-Feb-2017: ----------------------------------------- These DRC runs were made with the Design Rules: These are the defaults left in the design by the Fill Generation Process. Default Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 0.20 0.35 Trace 0.12 0.20 0.185 Fill 0.14 0.20 0.30 0.40 Quad_LED Pin Via Trace Fill ----- ----- ----- ----- Pin 1.00 Via 1.00 1.00 Trace 1.00 1.00 1.00 Fill 0.14 0.20 0.30 0.40 Diff_Pair Pin Via Trace Fill ----- ----- ----- ----- Pin 0.50 Via 0.38 1.00 Trace 0.12 0.26 0.21 Fill 0.15 0.20 0.35 0.40 A typical setup is: Entire Board Remove Trace Violations -- NOT Check Net Agains Itself -- NOT Check Trace Widths Less Than Net Rule -- NOT Check All Thermal Ties on Pins and Vias -- NOT Check Same Net Pad to Pad Clearances -- NOT Remove Deplicate Routing -- NOT Check Pas connectivity with fill hatch - NOT Report Off Grid Vias as -- No Checking Report Uncovered Plated Drill Holes as -- Warning Traces_724 is WithOut Fills DRC result: ---------------------------- Check Traces Messages --------------------------- Warning: Two vertices are coincident from ( 41.1,207.45 ) to ( 41.1,206.5 ) on layer (PHYSICAL_13) Warning: Two vertices are coincident from ( 41.1,211.4 ) to ( 41.1,210.45 ) on layer (PHYSICAL_13) ---------------------------- Check Traces Summary ---------------------------- Note: Checked: 84292 Segments, 2932 Vias and 0 Fill_Areas (from: Idea/LAYOUT/ROUTE E6) Note: Routing violations = 0 (from: Idea/LAYOUT/ROUTE 21) Note: Odd Angle Segments = 48033 (from: Idea/LAYOUT/ROUTE F1) Note: Unroutes = 1147 (from: Idea/LAYOUT/ROUTE E2) Note: Unfinished Connections = 356 (from: Idea/LAYOUT/ROUTE EB) Note: Unplaced components = 0 (from: Idea/LAYOUT/PLACEMENT2 67) Note: Off-board components = 0 (from: Idea/LAYOUT/PLACEMENT2 68) The coincident vertices warning is OK for now. This is from wanted duplicate trace routing on C1012 in the FPGA_Core supply. This is on the bottom of the card. If it is necessary to edit traces again I can probably clean this up - but it is not a problem for now. Runs on Production Traces With and WithOut Fills on 17-Feb-2017: ------------------------------------------------------------------ Today's two runs were done under the same conditions as the run on 13-Feb-2017 that is shown right above this. These runs used the default minimal Design Rules as setup by the last step in the Signal_12 Fill geneeration script which are listed above. The run on Production Traces WithOut Fills gave exactly the same result as on 13-Feb-2017: i.e. two cases of two coincident vertices. The run on Production Traces With Fills gave the following summary: ---------------------------- Check Traces Summary ---------------------------- Note: Number of classic fills checked = 0 (from: Idea/LAYOUT/Thermal Tie 00) Note: Number of areafills checked = 33 (from: Idea/LAYOUT/Thermal Tie 01) Note: Number of actual shapes found = 33 (from: Idea/LAYOUT/Thermal Tie 07) Note: Number of island shapes found = 365 (from: Idea/LAYOUT/Thermal Tie 08) Note: Number of pins with ties checked = 1435 (from: Idea/LAYOUT/Thermal Tie 02) Note: Number of vias with ties checked = 207 (from: Idea/LAYOUT/Thermal Tie 03) Note: Number of flood ties checked = 1642 (from: Idea/LAYOUT/Thermal Tie 04) Note: Number of isolate ties checked = 0 (from: Idea/LAYOUT/Thermal Tie 05) Note: Number of thermal ties checked = 0 (from: Idea/LAYOUT/Thermal Tie 06) Note: Checked: 84292 Segments, 2932 Vias and 33 Fill_Areas (from: Idea/LAYOUT/ROUTE E6) Note: Other Errors/Warnings = 498 (from: Idea/LAYOUT/ROUTE AD) Note: Odd Angle Segments = 48033 (from: Idea/LAYOUT/ROUTE F1) Note: Unroutes = 0 (from: Idea/LAYOUT/ROUTE E2) Note: Unplaced components = 0 (from: Idea/LAYOUT/PLACEMENT2 67) Note: Off-board components = 0 (from: Idea/LAYOUT/PLACEMENT2 68) and shows the two cases of two coincident vertices and many many cases of "poor coverate by Fill_Area". The following is an example of the "poor coverage by Fill_Area". Warning: Pin (23.14,190.13) has poor coverage by Fill_Area (21.05,183.55) (29.45,200.95). This must be the upper MiniPOD pin C6. This must be the Fill on Signal_6. The two X,Y pairs identifying the Fill_Area must be the Lower_Left and Uppoer Righ corners of the rectangle that encloses the Fill in question. Note that the funny abc.x5 dimensions are because its reporting to the center of the 0.10 mm wide trace that is usded to draw the fill shape. I do not know what parameters govern the generation of Poor_Coverage messages. I do not know if they reflect a narrow neck getting to the named pin or reflect a narow section in the fill where the pin itself is located.