Project Log Book for the Hub_0 Board Design ----------------------------------------------- The most recent entries appear first in this log book file. ------------------------------------------------------------------------ DATE: -Feb-2017 Topic(s): ------------------------------------------------------------------------ DATE: 16-Feb-2017 Topic(s): More checks before release, release, archive tars Proof read the Assembly documents last night so this morning I could cleaned up a couple of points in the assembly description and fix one component type in the component description file. In the Bare_Board directory I removed the 4 bla_original" files and renamed the 3 bla_no_therm and the 1 bla_no_r255_r256 into just bla. I readback with a browser from the .../manufacturing/Production/ website the 10 Assembly and 39 Bare_Board files and diffed them with the originals on moto both to verify that the correct version of these files was in the release web site and to check for any errors copying the files to the web release area. All files look OK - but as to their content ? Spent a quality hour studying the gerbers in Fablink. There is an un-needed width change on L3 Sig_2 at about: 63.5, 210.5 and 136.3, 209.5 Sent the released note to George. Full time push on the Hub design started on 18-Feb-2015. Review the status of the design: Status: with all fills OUT Using the full_silk_text components. comps 2932 rev 1335 fst nets 3785 rev 641 connections 8828 finished 7325 rev 739 (724) unfinished 356 guides 1147 Note/Recall: The full_source_text components file and the built from source components file are no longer equal. They differ at least in the geometry that is used for 102 of the DPVs. See the log book entry from Tuesday 14-Feb and the beginning of Wednesday. ---> Currently the full_silk_text components file must not be used to generate Gerber files. Archive tar Files: /home3/edmunds/BackUps/backup_hub_0_wed_1.tar all source wout build /home3/edmunds/BackUps/backup_hub_0_wed_2.tar all source with build /home3/edmunds/BackUps/backup_hub_0_thur_2.tar all source with build and with final version manufacturing documents I will append "_archive" to these three files on moto and force. Edit the trace routing details file to include the two new special use layers from this week for implementing the two circles vs full oval ground plane relief around the DPVs high-speed pins. ------------------------------------------------------------------------ DATE: 15-Feb-2017 Topic(s): Summary of the Hacks yesterday and the incorporation of them. "Final" Build Summary of Ground Stiffen Hacks from Yesterday: - To stiffen the ground structure around the FPGA and around the south edge of each row in the MGT Fanout, I wanted to modify the DVPs that have both their "input" and "output" traces in the same half of the card. The oval ground plane relief around these DVPs could be reduced to just two 0.85 mm diameter circles in the third of the ground plane where the "input" and "output" signals were not located (and remain a full oval in the Middle thrid and either the Top or Bot third where the signals are located). - So creat two new DVP geometries: diff_pair_thru_3p_top_mid_relief and diff_pair_thru_3p_mid_bot_relief that can be used in place of diff_pair_thru_3p for the DVPs that have their "input" and "output" all in Top or Bot half of the card. diff_pair_thru_3p_top_mid_relief uses GLUE_MASK_1 diff_pair_thru_3p_mid_bot_relief uses COMPONENT_METAL_1 to inticate the Oval type Plane Relief that they require. - Edit default_artwork_order_production so that it properly takes into consideration: PROBE_1 and COMPONENT_METAL_1 when it is generating the three types of Ground Plane plots. - Edit sundry_comps so that the 36 or so DVPs around the FPGA are switched as needed from: diff_pair_thru_3p to either diff_pair_thru_3p_top_mid_relief or diff_pair_thru_3p_mid_bot_relief as needed. - In the comps directory creat: dans_special_script.sh and dans_special_script.take which operated on what has been the final output of the components file generation process, i.e. aa_hub_0_comp_file.txt and replaces in it where possible the DVPs in the MGT Fanout with either diff_pair_thru_3p_top_mid_relief or diff_pair_thru_3p_mid_bot_relief as appropriate. Steps for today: Verify that this new DVP ground structure is all OK, then if so Add the dans_special_script.sh stuff to the normal script that builds the components file Then: Build comps, generate Fills, Drills, and Gerbers. Build the Release: - Run the new aaa_hub_0_build_all_comps.sh and give the result to Mentor as comps_1335. This is now the "official_from_source" comps. Verify with diff that comps_1335 is exactly the same as was buuilt by hand in pieces yesterday and verify that comps_1335 differs from the previous official from sources version only in the 102 DPVs that should be changed. 36 around the FPGA and 56 in the Fanout. So the comps files for this build are: comps.comps_1333_official_full_silk or comps.comps_1335_official_from_source with the active one copied to comps.comps_1335 - Run aaa_hub_0_build_all_nets.sh to generate a fresh copy of the netlist from source. Verify that it is equal to the previous version of the Hub netlist. So the netlist file is now: nets.nets_641 - Delete the existing: artwork, drill, and with_fills traces files. - Backup then Status: with all fills OUT with changes for about 102 FPGA DVPs unconnected pin count = 51 comps 2932 rev 1335 src nets 3785 rev 641 connections 8828 finished 7325 rev 724 unfinished 356 guides 1147 - Generate Fills from: comps_1335 from_source traces_724_official_pre_fill Run time 13:28 Look at them with Layout Status: with all fills IN with changes for about 102 FPGA DVPs unconnected pin count = 51 comps 2932 rev 1335 src nets 3785 rev 641 connections 8333 finished 8333 rev 739 unfinished 0 guides 0 33/33 Shapes/Fills concatenated from 60 8333 - 7325 = 1008 connections completed with the Fills - Generate Drills form: comps_1335 from source traces.traces_739_official_with_fills Diff and these new drill files are equal to the previous version. - Generate all Gerbers form: comps_1335 from source traces.traces_739_official_with_fills Run time about 28:33 - Switch Mentor to: comps_1335 full_silk traces.traces_739_official_pre_fill - Generate just Silk Gerbers form: comps_1335 full_silk traces.traces_739_official_pre_fill - Run the back end scripts: remove_most_ground_thermal_relief.sh remove_r255_r256_paste_stencil_openings.sh - Copy to the Web - Leave Mentor with the: comps_full_silk traces_pre_fills - Backup - Start looking and diffing. I have the old versions to compare to. - If today's work holds up as the Production Release then the archive tar files are: /home3/edmunds/BackUps/backup_hub_0_wed_1.tar all source wout build /home3/edmunds/BackUps/backup_hub_0_wed_2.tar all source with build ------------------------------------------------------------------------ DATE: 14-Feb-2017 Topic(s): Diff the Release Files, Weakness in the Ground structure try to stiffen around FPGA and the MGT Fanout, Out of general interest try diffing the release files between the set generated yesterday 13-Feb-2017 (i.e. with the actions taken on Philippe's 50 comments) and the set generate on 8-Feb-2017. Note that the "old" silks are from a middle date. ch artwork_1_trace_fill_L1_top major ch artwork_2_trace_L3 minor half a screen ch artwork_3_trace_L5 minor 1 screen ch artwork_4_trace_L7 minor 1 screen ch artwork_5_trace_fill_L9 minor half a screen ch artwork_6_trace_fill_L11 major ch artwork_7_trace_fill_L12 major ch artwork_8_trace_fill_L14 minor 4 screens ch artwork_9_trace_L16 major ch artwork_10_trace_L18 minor 2 screens ch artwork_11_trace_L20 major ch artwork_12_trace_L22_bot major ch artwork_13_gnd_plane_Ls_2_4_6_no_therm a couple of flashes swap ch artwork_14_gnd_plane_Ls_8_10_13_15_no_therm positions but there is no ch artwork_15_gnd_plane_Ls_17_19_21_no_therm change in overall context ch artwork_16_mechanical_drawing expected change because text changed nc artwork_17_silkscreen_top note this is 13-Feb version vs 10-Feb version nc artwork_18_silkscreen_bot note this is 13-Feb version vs 10-Feb version ch artwork_19_solder_mask_top a couple of flashes swap positions ch artwork_20_solder_mask_bot but there is no change in overall content nc artwork_21_paste_stencil_top nc artwork_22_paste_stencil_bot_no_r255_r256 nc artwork_23_plugs_top nc artwork_24_plugs_bottom nc drill_through_holes_plated ch = changed nc drill_through_holes_unplated nc = no change At some point (today or tomorrow) I willl generate another set of Back-Drill files an verify that nothing has changed. Ground Structure Weakness: - In many locations the ground structure (ten planes of half ounce copper) must be held back away from Differential Via Pairs on the high-speed signals. An example of this is the row of DVPs along the top and bottom edges of the FPGA. Each of these DVPs makes an oval cutout in all ground plane layers that is 1.00 mm wide and 1.00 mm long center to center 2.00 mm long tip to tip. - These oval cutout go through all 10 ground plane layers and Philippe points out that in the case of the FPGA that all of the high speed signals using these DVPs are in the top 5 signal layers of the card, that these DVP vias are back drilled, and thus we could let the ground plane close in on this oval in the bottom "1/3" of the ground plane layers. Note that the bottom "1/3" of the ground plane layers means the "bottom type ground plane" which is used on 3 actual layers in the stackup. Both the top "1/3" and the middle "1/3" of the ground plane layers would need to manitain their full oval releif from the DVP pins. - So how much stiffer would the ground structure be if we let the relief ovals close in in the bottom "1/3" of the card ? How much could they close in ? As the vias that are relieved by these ovals are made from a 0.25 mm drill, I could reduce the Plane Relief from the full oval to two circles of 0.85 mm diameter. This 0.85 mm diameter plane relief is used in other parts of the card and is as small as one would want to go. A concern is keeping the plane metal relieved far enough so that the back-drill never touches it. Doing this would increase the width of the ground path between DVPs from 1.00 mm to 1.15 mm on 3 of the 10 ground plane layers - but it is really more than that, because the cutout on these three layers is no longer a full oval but rather 2 circles of 0.85 mm dia which even have a 0.15 mm bridge of ground between them. - Where this might be most helpfull is along the bottom edge of each row of the MGT Fanout where there is a contiguous string of DVPs all "end-stacked" right against each other. Currently this structure provides only 1.00 mm of ground connectivity out of every 3.00 mm of run. - What do I need to do to implement this ? - Because of the way that PrePreg 1,2,3 were setup I need to find two new spare currently unused layers in the design that plot rationall and that I can define to mean: ground plane cutout in the Top and Mid thirds ground plane cutout in the Mid and Bot thirds It would be crazy to try to change the existing special meaning / use of PrePreg 1,2,3. - I need to add these two new layer definitions to the Artwork_Order geometry. - I need to make two new geometries, that are like the diff_pair_thru_3p geometry, but that use these new special layer definitions to indicate cutout in either: top and mid or in mid and bot. - I need to edit the comps files as required to replace the original diff_pair_thru_3p geometry with the correct one of these two new diff_pair_thru_3p geometries. - The mainline files that were hacked to make a test of Oval Relief on just Top/Mid or Mid/Bot are: sundry_comps_svd_14feb17 default_artwork_order_production_svd_14feb17 diff_pair_thru_3p_top_mid_relief added for this test - Verify that I do not break anything in an obvious way when I switch to using the files that implement DVP Oval cutout on just top/mid or just mid/bot. Status: with all fills OUT before any change comps 2932 rev 1333 src nets 3785 rev 640 connections 8828 finished 7325 rev 724 unfinished 356 guides 1147 Now: add/restore the new diff_pair_thru_3p_top_mid_relief and the modified default_artwork_order_production to the geometry library. build components and pass to Mentor as comps_1334. diff the new comps_1334 with the old offical from source comps file and see that the only difference is the 36 DVPs that surround the FPGA. Status: with all fills OUT with changes in for about 36 FPGA DVPs. comps 2932 rev 1334 src nets 3785 rev 640 connections 8828 finished 7325 rev 724 unfinished 356 guides 1147 - Looking with Layout and the new setup for these 36 or so DVPs around the FPGA looks OK. So hand Mentor the traces file with Fills and generate new gerber for the 3 ground plane plots, and run the thermal aperture removal script, and copy to the web. - Go ahead an make a quick implementation of this for the DVPs that are stacked end to end in each row of the MGT Fanout. To do this make the files: diff_pair_thru_3p_mid_bot_relief to go with diff_pair_thru_3p_top_mid_relief that is used both around the FPGA and in the Fanout dans_temp.txt in Text to hold the Reference Designators of the DVPs in the Fanout that I think can be changed to use Oval Relief on either just Top/Mid or just Mid/Bot. dans_special_script.sh These together edit the comps dans_special_script.take file aa_hub_0_comp_file.txt to change the reference designators listed in dans_temp.txt above from diff_pair_thru_3p to either diff_pair_thru_3p_top_mid_relief or diff_pair_thru_3p_mid_bot_relief as required/appropriate. - Run all of this and make new Ground Plane plots. - Note that special layer GLUE_MASK_1 and COMPONENT_METAL_1 are being used by diff_pair_thru_3p_top_mid_relief diff_pair_thru_3p_mid_bot_relief. - Edited the default_artwork_order_production to use these are required in making the Ground Plane plots - New Gnd Plane plots on the web to be studied. ------------------------------------------------------------------------ DATE: 13-Feb-2017 Topic(s): Monday Meeting, Work on Shapes, Trace Edits, Release Files, Archive Monday morning meeting with all present. Current plan: finish fixing the design today. make new release files Tuesday AM, study the release Tuesday PM and Wednesday AM, release it Wednesday PM. Work on Fill Shapes: - Move the southern border of the ROD Shield Fill north by 0.70 mm - Fix the typo in the Signal_12 Iso_12V Fill that caused a step NE of Fan_1V8 supply - Add extra width on the East edge of the Signal_11 Iso_12V supply where it runs past the Phys Chips south to the converter This required edits to: fill_shapes_on_other_layers.txt fill_shapes_signal_11_nom_core_and_avcc.txt and fill_shapes_signal_12_nom_core_and_avtt.txt that had been relatively stable. Rebuild and restore Hub pcb geometry. The new Fill Shapes look OK but the proof will be in the Fills. More Trace Editing: - Clean up the way that the 2.5 mm Iso_12V traces enter the PVAs for the FPGA_Core supply, i.e. eliminate notch, remove interferrence with ROD Shield, come in from West on Signal 1 and 10. - On the south edge of the MGT Fanout array take advantage of the space to bring in the input differential pairs from the backplane on Signal 7, 8, 9 with one less jog. This keeps these 3 inputs with a 2.0 mm air gap to the wall of vias south of them. This trace edit starts on: traces_723 & comps_1333 from source. The fixes go in OK. Save traces_724, and make a copy. Save a report of trace length. The 3 South edge inputs to the MGT Fan Out that were changes look OK in length match. Status: with all fills OUT un-connected pins = 51 as expected comps 2932 rev 1333 src nets 3785 rev 640 connections 8828 finished 7325 rev 724 unfinished 356 guides 1147 A DRC run with the default clearances looks OK - so try building it. Generate Release Files: - Start generate All Fills from trace_724_official_without_fills comps_1333 from sources Made two runs to completion in about 13 min 28 seconds each. These runs make: traces_729_with_fills_first and traces_734_official_with_fills make a copy of 734 and diff all OK. 729 and 734 are exactly the same size but have differences when you try diffing them. As usual with traces files it hard to tell if they are actually any differeces Go forward with traces_734_official_with_fills dump traces_729. - Look at traces_734 with layout. Status: with all fills IN un-connected pins = 51 as expected comps 2932 rev 1333 src nets 3785 rev 640 connections 8333 finished 8333 rev 734 unfinished 0 guides 0 shapes/fills 33/33 concatenated from 60. The fills completed 8333 - 7325 = 1008 routes. The 3 new shapes look OK. - Start generate all gerbers on traces_734 (official_with_Fills) comps_1333 from source This runs to completion in about 30 minutes with "no missing apertures". - Run the script generate_drill_table_and_drill_files using the same above traces_734 (official_with_Fills) comps_1333 from source - Switch to the traces without fills and the full_silk_text comps file traces_724_official_pre_fill comps_1333_official_full_silk and generate (again) just the two silkscreen gerbers. - Run the scrips to pull out the Thermal Relieves from the ground plane plots and the solder stencil openings for R255/R256: remove_most_ground_thermal_relief.sh remove_r255_r256_paste_stencil_openings.sh - Copy the new artwork and drill files to the Web. Web directory now named: ...../manufacturing/Production/ - I saved all of the previous output files, only a few should have changed, so start looking at the differences. So far I see what I expect to see, e.g. drills have not changed. If by chance this set of release files holds up then the overall archive of this (including two copies each of with and without traces and all the gerber files) is the tar file: 124465664 Feb 13 17:47 /home3/edmunds/BackUps/backup_hub_0_mon_5.tar ------------------------------------------------------------------------ DATE: 12-Feb-2017 Topic(s): Assembly Not_Installed Components, Trace Editing Work, Finished editing the assembly Not_Installed components file so that the 90 or so entries have full X,Y Side location information. Make the version official in/on production release 4. Start to Trace Editing work to fix the various problems and "funny" things that Philippe reported on Friday afternoon in his 50 png comment files. This is more changes/corrections than I can make in one trace editing sesion - so start with the simple easy to do stuff today. Maintain the list: L_dan_scan_gerber_comments.txt with a new column to indicate which items have been worked on in the traces file. Start by pointing Mentor at the official pre-fill traces file and the official comps file from source. Diff to verify: mv traces.traces_722 traces.traces_722_copy_pre_fill mv traces.traces_717_official_pre_fill traces.traces_722 diff traces.traces_722_copy_pre_fill traces.traces_722 cp comps.comps_1331_official_from_source comps.comps_1333 diff comps.comps_1333 /home2/designs/boards/Hub_0/Work/Components/aa_hub_0_comp_file.txt About a 4 hour trace edit session - final write traces_723 and backup Details of corrections are in: L_dan_scan_gerber_comments.txt Status: with all fills OUT comps 2932 rev 1333 src nets 3785 rev 640 connections 8825 finished 7321 rev 723 unfinished 356 guides 1148 ------------------------------------------------------------------------ DATE: 11-Feb-2017 Topic(s): Work on Philippe's 50 comments on the current Gerbers, Work on Not Installed & Comp Descriptions Go through Philippe's 50 comments on the current Gerbers. These comments are in the form of filenames "Lx_y.png" in the ..../drawing/General/ directory. Philippe has very rationally worked to flag anything that looks "funny". There will be rational engineering reasons for some of these funny looking things and others will be mistakes / oversights. Start by going through all of them, study each one from the Mentor layout, and write down what action will be taken in each case. This "actions to take on Philippe's comments" will be in the ..../drawings/General/ directory along with his comment png files. L_dan_scan_gerber_comments.txt Return to working on the assembly files: Not_Installed and Component_Descriptions. No Mentor counts or versions should have changed today. ------------------------------------------------------------------------ DATE: 10-Feb-2017 Topic(s): Assembly Files, Philippe scanning gerbers, release plans discussed with Wade All day working on the 9 or 10 files for the Assembly house. All are checked except that I need to finish verifying the component_description file is complete with all of the component types that the assembly house will be working with and no other old junk from early versions of the design. I also want to add side information to the Not_Installed component list file. Philippe has dug out 20 or so areas from the gerber files that should be reviewed from Layout to see is the apparently extra jogs and such are really needed or just left overs from routing that cleanup has not removed so far. He is putting a set of in close view with the funny patches circled on the web. The plan is to make one more pass with Layout to clean up the issues the he found yesterday and today, then diff the resulting trace file, generate the Fills, generate the gerbers, and run the scripts to pull out thermal apertures from the ground planes and such. Monday make the final decision to release and use the bulk of the day making a final study of the release files. This plane was discussed with Wade and Philippe. The full silk text comps file version had increment today because of more silk cleanup work. There should be no other changes to Mentor counts. ------------------------------------------------------------------------ DATE: 9-Feb-2017 Topic(s): Bare PCB Manufacturing files, More silkscreen work, Philippe digging into gerbers Finished editing the description file for manufacturing the bare pcb. I rechecked all of the hole diameters, counts and descriptions - plated and un-plated. There are 8 cases where I have concatenated hole sizes. Recall that the same nominal diameter hole size, if used both plated and un-plated, requires two different tool codes. Duh - they are separate operations for the bare pcb house. Made another set of rounds cleaning up silkscreen both the pcb geometry based and the comps file based silkscreen text. We now finally have general card name text on the back and serial number white space on the front. Philippe is digging deep into the gerbers. So far we have a clearance issue to the ROD Shield Fill and notches where the 2.5 mm input traces tie up to the FPGA_CORE converter on Sig_1 and Sig_10. The full silk text comps file version had increment today. There should be no other changes to Mentor counts. ------------------------------------------------------------------------ DATE: 8-Feb-2017 Topic(s): Hub trace work and generate Fills, Drill, and Gerbers - From layout work on the C146, C116, C1962 points in Philippe's note and then save Full Silk Text Comps comps_1330. Diff this with the previous to verify no other changes. Comps_1330 is now the official Full Silk Text Comps. - Expunge all artwork and drill files from .../pcb/mfg/ - Expunge the current official with-fills traces. - Move the official per-fill traces file into traces_715 and diff with copy to verify. Recall that this is actually the file traces_700. - Hand Mentor a copy of the source built comps file. This is comps_1331. Diff it with the source directory to verify. - Make a backup and then start editing with: nets.nets_639, comps.comps_1331, traces.traces_715, geoms.geoms_842 This is the trace edit to add the Sensor I2C bus EEPROM and make about 20 other trace cleanup - one of which is semi serious. This makes traces_716. - Give Mentor the latest nets - now for the first time Mentor sees the fix to the Pos Iso_12V Remote Sense. This is nets_640. Diff nets_640 with the source directory and it is all OK. - Start trace editing with: nets.nets_640, comps.comps_1331, traces.traces_716, geoms.geoms_842. This trace editing is just to put in the new Iso_12V remote sense. This make traces_717. Make a copy of traces_717 and name the real traces_717 --> traces.traces_717_official_pre_fill - Restart layout on: nets.nets_640, comps.comps_1331, traces.traces_717 (copy), geoms.geoms_842 just to get Mentor Counts and see that it looks OK. No Edit No Save. Status: with all fills OUT Routing all in for EEPROM and Remote Sense Fix. Source Comps comps 2932 rev 1331 nets 3785 rev 640 connections 8825 finished 7321 rev 717 unfinished 356 guides 1148 - Generate all Fills. Save traces as official with-fills. Run time 13:26 This is: traces_722 - Restart layout on: nets.nets_640, comps.comps_1331, traces.traces_722 (copy), geoms.geoms_842 just to get Mentor Counts and see that it looks OK. No Edit No Save. Status: with all fills IN Comps is from Source comps 2932 rev 1331 nets 3785 rev 640 connections 8329 finished 8329 rev 722 unfinished 0 guides 0 33 Shapes 33 Fills concatinated from 60 The design completed OK, i.e. the fills finished all connections. The obvious things looks OK. Trans MiniPOD 2V5 is OK. Sensor I2C EEPROM look OK. ISO_12V Remote Sense looks OK. - Continue using: nets.nets_640, comps.comps_1331 (from source), traces.traces_722 (copy of with-fills), geoms.geoms_842 - Generate the Drills. - Generate all 24 gerbers running from the with-fills traces and the Source file version of Comps. Ran to completion with no missing apertures. - Switch Mentor soth that: comps_1131 is now a copy of comps_official_full_silk and traces_722 is the copy of traces_official_pre_fills. Diff both to verify. - Run the script to generate just the two Silk Gerber files. - Run the scrips from the .../Tools directory to pull the required Thermal Apertures out of the Ground Plane plots and to pull R255 R256 out of the bottom side Paste Stencil plot. - Copy the new Gerbers and Dills to release 4 on the web. - Leave Mentor with: pre-fills traces and to the comps file with the Full Silk Text Ref Designators. - Note that there was no need to re-generate the Back-Drill files today because no changes have been made in the High-Speed traces since they were generated last. The current set of Back-Drill files was fully checked see the log book entry for: 1-Feb-2017 - Verify that the drills only changed as expected, for the trace editing that was done today. OK - Start work to study the Gerbers. See a clearance problem between the PVAs for the ISO_12V input to the MGT_AVCC and MGT_AVTT converters and the ROD shield. Looks at little over 0.20 mm and should be 0.70 mm. How can this be ? ------------------------------------------------------------------------ DATE: 7-Feb-2017 Topic(s): Touch the Generate Sig_5 Fills and Generate Through Hole Drill scripts, Layer by layer scan from Layout, Capture the current through hole counts and usage, Make a Full Silk Text version of Comps that includes the 7 new components from yesterday, Philippe finds a problem with FPGA Paste Stencil, Edit the Assembly House Not Installed Comps, edit Aperture Table to thinken spokes on the Iso_12V pin #4 D-Code 265, Order of work Wednesday morning. Most of the comps file and nets file work was done yesterday to fix the remote sense problem on the positive side of Iso_12V and to add the Sensor I2C EEPROM - but I have not done any of the trace work for either of these yet. I'm waiting to see of any one else has suggestions for trace cleanup and then I want to do all fixes, repairs, additions at once. To fixing the remote sense problem and to add the new I2C EEPROM will require: generating new Fills and Drills. Because I must generate new Fills and Drill I made two small changes to the scripts that do this: generate_all_fills_on_signal__5.sh now has both the 2V5 and 3V3 Trans MiniPOD fills generated with the special set of design rules that was first put together to fix the lack of closure around the Trans MiniPOD 3V3 Fill on 30-Jan-2017. generate_drill_table_and_drill_files.sh now does the renaming of these files into something that both Mentor and the board house can use. I made a layer by layer scan through the card from Layout, i.e. looking at the design - not at the gerbers and I've spotted about 19 or 20 things to fix/cleanup when I go into the design to work on traces Wednesday morning. Most items are 50/50 cosmetic/functional but one was semi-serious. While looking at Gerbers Philippe sees that a Long-Dog_Bone pin/pad stacks on the FPGA has a funny looking Paste Stencil. I dug into it and it is just the long dog-bone to the NNE pin/pad stack that is screwed up. There are 17 types of pin/pad stacks used in the FPGA and all the rest had a the correct 0.52 mm Paste Stencil opening. Edit BGA_2104_PAD_LONG_VIA_NNE pin/pad stack to fix this. Build and Restore the FPGA geometry. Verify with grep that the other paste stencil openings are correct. Diff the before and after FPGA geom files to verify there are no other changes: flvc2104_rev__2__geometry_tailored.txt The python code that manages the Reference Designator locations can not really add the known good reference designator locations to a comps file that is generated from the source files. Thus, by hand add the 7 components that were added to the design yesterday (to fix Iso_12V remote sense and add I2C EEPROM) to the current Full Silk Text version of the comps file, i.e. add them to comps_1325. This makes comps_1328. Then adjust the reference designators on 6 of these 7 new components and save as comps_1329. For now keep comps_1325 and comps_1329. comps_1329 is now the official full text silk comps file. Edit the file: hub_not_installed_components.txt add to it 6 of the 7 new components from the work yesterday to fix the Iso_12V remote sense and add the I2C EEPROM. These are the 6 "real" components with reference designators in silk. Edit the Aperture Table source file to make the spokes on the Thermal Aperture for pin #4 of the Iso_12V supply, D-Code 265, slightly wider, 1.00 mm to 1.20 mm. This is now 6x the air gap. Order of battle for the work Wednesday morning: - Give Mentor the current official pre-fills traces file and verify that it is good. Give Mentor the source files version of components. - Make all of the trace clean up edits, the add the EEPROM trace edits, and remove the current !so_12V remote sense trace edits. Save traces. - Pass to Mentor the newest net list that now includes the new positive Iso_12V remote sense. This net list is all ready built and just needs to be passed to Mentor - after the existing positive Iso_12V Remote Sense traces have been pulled out in the step above. This should increase the net count by 1. Recall Note that Mentor already has the new Sensor I2C EEPROM nets. - Back into layout just to do the trace work to route the new correct Iso_12V remote sense. Save traces and label as official pre-fill. - Generate all Fills. Save traces as official with-fills. - Stop here an with Layout look at the traces with-fills to make certain that things looks OK, that the fills completed all connections in the design, and to get the counts for the record / later verification. - Generate the Drills. - Generate all 24 gerbers running from the with-fills traces file. - Switch Mentor to the official pre-fills traces and to the components file with the Full Silk Text Ref Designators. - Generate just the two Silk Gerber files. - Run the scrips to pull the required Thermal Apertures out of the Ground Plane plots and to pull R255 R256 out of the bottom side Paste Stencil plot. - Copy the new Gerbers and Dills to release 4 on the web. - Verify that the drill only incremented as expected, i.e. two more 0.30 holes all else the same. - Start work to study the Gerbers. - Leave Mentor with: pre-fills traces and to the comps file with the Full Silk Text Ref Designators. Status: with all fills OUT with nets and comps for new EEPROM with comp for Iso_12V remote sense fix with full silk text comps file comps 2932 rev 1329 nets 3784 rev 639 connections 8821 finished 7305 rev 715 unfinished 355 guides 1161 ------------------------------------------------------------------------ DATE: 6-Feb-2017 Topic(s): ESD Resistor Values, Remove L1953, Checking Assembly docs Meeting with Wade, Start work Fix Remote Sense, Add EEPROM Move all three EDS resistors to being 1 Meg Ohm instead of 10 Meg Ohm. --> Edit: BOM, Bottom XY Place, Bot Comp Counts, Comps Descriptions. RES_10MEG_OHM_1206 becomes RES_1_MEG_OHM_1206 Remove L1953 from being installed by the assembly house to being installed during MSU Final Assembly. --> Edit: BOM, counts in assembly description, add to Not Installed, remove from SMD Comps Bottom, remove from XY Place Bottom. Verified the Not Installed doc. Verified that Comps Description OK for Cap and Res. Touch all 9 of the assembly documents to bring them up to date but still need to add the section, "look out for this" to the assembly description. Monday morning meeting with Wade, Pawel, Brian, Philippe, Yuri was at the dentist. Yes, add the EEPROM onto the Sensor I2C bus, meet again Wednesday afternoon, plan to release Thursday morning. Start the work to Fix the Remote Sense problem on the Positive side of the ISO_12V output: - Add AKA2 to file atca_comps at X 20.00 Y 22.00 side 1 rotate 0 - In atca_isolated_12v_nets: AKA2-1 to ISO_12V AKA2-2 to Remote_sense_Pos_Iso_12V Power_12V-7 to Remote_Sense_Pos_Iso_12V Start the work to Add the EEPROM to the Hub's Sensor I2C bus: - Add EEPROM M24256 U1541 at X 241.0 Y 305.5 side 2 rotate 180 - Add 220 nFd 0603 C1541 at X 234.0 Y 303.0 side 2 rotate 0 - Add JMP 0603 JMP1541 at X 249.0 Y 310.0 side 2 rotate 0 - Add JMP 0603 JMP1542 at X 249.0 Y 307.0 side 2 rotate 0 - Add JMP 0603 JMP1543 at X 249.0 Y 304.0 side 2 rotate 0 - Add JMP 0603 JMP1544 at X 249.0 Y 301.0 side 2 rotate 0 Add these comps to file: i2c_sensor_bus_comps Add these nets to: i2c_sensor_bus_nets BULK_3V3 U1541-8 C1541-1 GROUND U1541-4 C1541-2 HUB_PMBUS_SDA U1541-5 HUB_PMBUS_SCL U1541-6 SENSOR_PROM_E0 U1541-1 JMP1541-1 SENSOR_PROM_E1 U1542-1 JMP1542-1 SENSOR_PROM_E2 U1543-1 JMP1543-1 SENSOR_PROM_WC U1544-1 JMP1544-1 BULK_3V3 JMP1541-2 JMP1542-2 JMP1543-2 JMP1544-2 The components are now in the design for both the remote secse fix and to add the EEPROM. The comps file was diffed before after these additions an nothing else changed. Two Issues: - These 7 new comps were added to the comps source file for the Hub so they only exist in the "built from source" version of the Hub's comps file. How to get them into the full Silk Reference Designator version of the comps file ? And yes, the Ref Desig on 6 of these new comps needs to be adjusted to make a usable silkscreen. If necessary here is the text to add these 7 components to the Full Silk Reference Designator version of the comps file by hand: AKA2 Not_a_Part SY_JUNK AKA_1MM20 2000000 2200000 1 0 U1541 IC_M24256 SY_JUNK soic_8_no_bom 24100000 30550000 2 180 C1541 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805_1sb 23500000 30250000 2 0 JMP1541 Res_Zero_Ohm_0603 Not_Installed res_0603_1sb 24900000 31000000 2 180 JMP1542 Res_Zero_Ohm_0603 Not_Installed res_0603_1sb 24900000 30700000 2 180 JMP1543 Res_Zero_Ohm_0603 Not_Installed res_0603_1sb 24900000 30400000 2 180 JMP1544 Res_Zero_Ohm_0603 Not_Installed res_0603_1sb 24900000 30100000 2 180 - Which if any of these comps should be installed by the assembly company ? C1541 is the only obvious one. All of these new comps that are not installed at the assembly house need to go into the Not Installed document. The nets are now in the design for the new Sensor I2C EEPROM. I can not put in the net changes to fix the remote sense problem until working on it as those net changes will blow up some existing traces. Status: with all fills OUT with new nets and comps as above comps 2932 rev 1327 nets 3784 rev 639 connections 8821 finished 7305 rev 715 unfinished 355 guides 1161 ------------------------------------------------------------------------ DATE: 5-Feb-2017 Topic(s): Finish bottom fiducials, Stop removing the Thermal Flash on two ATCA Module Pins Finish the Fiducial Marks. Much adjustment to get a rational distribution of fiducials, that are located at nice whole number coordinates and are not too close to other copper or silk. I want to have Thermal Relief on Pin #13 of the ATCA Power Entry Module and on Pin #4 of the ATCA Iso_12V module. Edit the following files to get this: remove_most_ground_thermal_relief.sh remove_ground_thermal_relief_sed.2_take aperture_table.apertt_hub_minimum_wagon_wheel Full details are in the 5-Feb-2017 comments section of the remove_most_ground_thermal_relief.sh file. Thus as of this date, I'm removing only 15 of the 18 Thermal Relief Apertures that currently actually appear in the three Ground Plane plots as generated by Mentor. The Thermal Relief Aperture that now remain in the Ground Plane plots after the removal script are: - D265 pin #4 on the ATCA Iso_12V Module and - D276 pin #13 on the ATCA Power Entry Module - D405 which is used for the Ground Loops aka Scope Loops. Note that as written by Mentor all three Ground Plane plots each uses all 18 of the Thermal Relief Apertures. Build a new set of the three Ground Plane gerber files, run the remove_most_thremals script, check them, copy to web. Note the moving of Mentor versions to make the new Ground Plane gerber plots: "data path" the source generated comps from 22-Jan-2016 mv traces.traces_715 traces.traces_715_copy_no_fills mv traces.traces_715_official_with_fills traces.traces_715 make the plots, i.e. run the generate ground plane plots script mv traces.traces_715 traces.traces_715_official_with_fills mv traces.traces_715_copy_no_fills traces.traces_715 mv comps.comps_1324 comps.comps_1325 Each of the 3 ground plane plots, with most thermals removed, is now 61 bytes longer than before: 145106 Feb 2 10:21 artwork_13_gnd_plane_Ls_2_4_6_no_therm 116602 Feb 2 10:21 artwork_14_gnd_plane_Ls_8_10_13_15_no_therm 150216 Feb 2 10:21 artwork_15_gnd_plane_Ls_17_19_21_no_therm 145167 Feb 5 17:58 artwork_13_gnd_plane_Ls_2_4_6_no_therm 116663 Feb 5 17:58 artwork_14_gnd_plane_Ls_8_10_13_15_no_therm 150277 Feb 5 17:58 artwork_15_gnd_plane_Ls_17_19_21_no_therm I checked that each entry of a new aperture select followed by one flash takes exactly 30 bytes and I assume that there is one more carriage return to make 61 bytes. ------------------------------------------------------------------------ DATE: 4-Feb-2017 Topic(s): Work on the fiducials Most of the fiducial marks are fixed or now put in on the top side of the Hub. ------------------------------------------------------------------------ DATE: 3-Feb-2017 Topic(s): Tentatively finish with the Silkscreen Text, New problems in the design Tentatively finished the pcb geom additions to the Hub's silkscreen text. There are now about 150 additional text strings on the Hub pcb coming out of its pcb geometry file. I can think of a few more useful ones, e.g. trim pots and power supply FB jumpers, and I will keep a list what all else could be added, but this text is "finished" for now. New design problems / considerations / to-do items: - Pin 13 of the ATCA Power Entry module (SynQor pin name Logic Ground) makes a connection to the Hub's Ground Planes. It may be a good idea to put back in the Thermal Relief on this pin - just in case we ever need to replace this module. This pin is at x = 107.100 y = 13.475. I think that it is the only use of D-Code 276 in the three Ground Plane plots and thus it is easy to put it back into the design. If this is done I need to "un-minimize" this thermal aperuter in the aperture table. - Pin 4 of the Iso 12V module is the negative side of its 12V output and thus makes a heavy 25 Amp connection into the Hub Ground Planes. Is it rational to try to Thermal Relieve this pin ? This pin is going to be very hard to solder and impossible to un-solder. It ties to: 5 oz of Ground Planes and another 4 1/2 oz of spreader traces. This pin is located at x = 31.354 y = 30.747 and is I believe the only use use of D-Code 265 in the ground plane plots. I will check the SynQor Pin Thermal Relief application note again. Basically I think that they recommend a 2:3 or 1:1 Length/Width thermal relief but give no guidance about inner and outer diameters. Should the hot positive output pin, Pin #4, receive the same treatment ? This output pin sees 2 oz of planes and another 4 1/2 oz of spreader traces. The hot output pin is located at x = 31.354 y = 15.507 - If I need to edit traces again there are some unneeded jogs in a few LED traces near 12 227 and north of there to pull out. - Need to add the R959 the Ground Link Jumper to the "as built" jumpers description document, hub_0_ab_jumpers.txt - If I need to edit the traces again I could probably fatten by 20% the first long section of the Shelf Ground trace that comes output the Zone 1 connector. - I want to move L1953 to the Not Installed at Assembly House class of components, either by making it really Not Installed in the design, or else just by hand editing the documentation files to the assembly house: Comp Counts, BOM, Not_Installed, X_Y_Placement. I want to see under this part at the big via for the 3V3 feed to the South before this part is put on. I need to get some of the L1953 comps for use here during the Final MSU Assembly work. - There are problems with the fiducial marks. I need to fix and or add them for: 3x Switches, 2x Phys Chips, top and bottom FanOut array, sc70 comps on the backside of the card and the clock fanout East of the FPGA. - The Remote Sense pin on the hot side of the Iso 12V supply, pin #7, makes a dirrect connection to the +12V Fills on layers Signal_5 and Signal_6. To fix this I need to fix the design. Because this is an un-wanted connection to Fills, I can not just by hand add some emergency keep out flashes to gerber plots to remove this direct connection. The problem with this direct connection is that it by passes the remote feedback on the positive output from this supply. The remote sence for the return side of this supply is handled correctly in the design and pcb. I assume that this screw up in the remote sense for the hot side of this supply is due to a change in the shape of the Iso +12V Fills that was probably made many months ago. There should be no change in Mentor Counts today. The only changes should be to the gome library version as the various batches of pcb goem based silk text were added. ------------------------------------------------------------------------ DATE: 2-Feb-2017 Topic(s): Made new Gerbers, Meeting with Wade, Silk Text non Ref Desig, clean up the Hub Release document Generated a new set of Gerbers to verify that the problem with the painted narrow traces in the neck-down and dual-track region was fixed and to get a "gerber view" of Philippe's work on the Reference Designators. This involved incrementing Comps from Philippe's 1322 to 1323 with the full silk text version left in place as 1323 after the gerber generation process. I ran the scripts in .../Tools to bury most of the connections to the Ground Plane and to remove Paste from R255 R256. Copied new Gerbers to the web. Short meeting with Wade and Philippe about including an EEPROM on the Hub's Sensor IC2 Bus. There is no final decision until the Monday meeting. I got started adding the silkscreen text to the card that is held in the pcb geometry part of the design, e.g. labelling Jumpers and Power Supplies and such. Most of this on Side 1 is now in. This involved moving some Reference Designators and thus comps was saved again to capture these changes. Now at comps_1324. I verified that the previous comps was written by Mentor and that one can diff them to verify what changes have been made. Major work in cleaning up the instructions for how to make a release of the Hub manufactoring data, hub_release_instructions.txt Much has changed since the initial version of this was written. Only the comps version should have changed. No change to Mentor counts. ------------------------------------------------------------------------ DATE: 1-Feb-2017 Topic(s): Full check of the Back-Drills, Problem with R255, R256, Problem with painted traces in the neck-down and dual-track, Update the Release Instructions, Wade, Philippe, Dan status meeting Full Check of the Back-Drills: Turn on just just one Signal layer and one layer of back-drill indicator circles at a time. Look for matches and lack of matches. Start with the Zone_2 set of back-drills: View Signal_10 with PrePreg_12 --> all Bk-Drills none match good View Signal_9 with PrePreg_9 --> Keep L20 thru L1 all match View Signal_8 with PrePreg_9 --> Keep L20 thru L1 all match View Signal_7 with PrePreg_10 --> Keep L16 thru L1 all match View Signal_6 with PrePreg_10 --> Keep L16 thru L1 all match View Signal_5 none used View Signal_4 with PrePreg_11 --> Keep L10 thru L1 1 used 1 match View Signal_3 with PrePreg_11 --> Keep L10 thru L1 1 used 1 match View Signal_2 with PrePreg_11 --> Keep L10 thru L1 2 used 2 match Yes, there is now back-drill on the "Combined_Data_From_Other_Hub" Check the two MegArray Connectors: View Signal_10 with Sheet_Die_12 --> all Bk-Drills none match good View Signal_9 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_8 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_7 with Sheet_Die_9 --> Keep L16 thru L1 all match View Signal_6 with Sheet_Die_9 --> Keep L16 thru L1 all match View Signal_5 with Sheet_Die_10 -> Keep L9 thru L1 1 match View Signals 4,3,2,1 no connections to MegArray Check the two isolated DPV: View Signal_10 & Signal_2 with Sheet Die 4 --> Keep L3 thru L22 1 match View Signal_10 & Signal_6 with Sheet Die 6 --> Keep L14 thru L22 1 match Check the Transmitter MiniPOD: View Signal_9 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_8 with Sheet_Die_8 --> Keep L20 thru L1 all match Check the FPGA: View Signal_10 with Sheet_Die_12 --> all Bk-Drills none match good View Signal_9 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_8 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_7 and 6 no connections to high-speed FPGA pins View Signal_5 with Sheet_Die_10 --> Keep 9 thru L1 all match View Signal_4 with Sheet_Die_10 --> Keep 9 thru L1 all match View Signal_3 with Sheet_Die_11 --> Keep 5 thru L1 all match View Signal_2 with Sheet_Die_11 --> Keep 5 thru L1 all match View Signal_1 connections to surface pads only Check the Fanout - Note more complicated here because the signal may need to go Up or Down: View Signal_10 with Sheet_Die_8,9,10,11 all Bk-Drill from bottom none match View Signal_9 with Sheet_Die_8 --> Keep L20 thru L1 all match View Signal_9 with Sheet_Die_7 --> Keep L18 thru L22 no cases View Signal_8 with Sheet_Die_8 --> Keep L20 thru L1 no cases View Signal_8 with Sheet_Die_7 --> Keep L18 thru L22 all View Signal_7 with Sheet_Die_9 --> Keep L16 thru L1 all match View Signal_7 with Sheet_Die_6 --> Keep L14 thru L22 no cases View Signal_6 with Sheet_Die_9 --> Keep L16 thru L1 no cases View Signal_6 with Sheet_Die_6 --> Keep L14 thru L22 all match View Signal_5 with Sheet_Die_10--> Keep L9 thru L1 1 match View Signal_5 with Sheet_Die_5 --> Keep L7 thru L22 all but 1 match View Signal_4 with Sheet_Die_10--> Keep L9 thru L1 all but 1 match View Signal_4 with Sheet_Die_5 --> Keep L7 thru L22 1 match View Signal_3 with Sheet_Die_11--> Keep L5 thru L1 1 match View Signal_3 with Sheet_Die_4 --> Keep L3 thru L22 all but 1 match View Signal_2 with Sheet_Die_11--> Keep L5 thru L1 all match View Signal_2 with Sheet_Die_4 --> Keep L3 thru L22 none match View Signal_1 with Sheet_Die_4,5,6,7 all Bk-Drill from bottom none match Back-Drill Summary - all looks good, what should exist is always there, what should not exist is never there. R255 - R256: Resistors R255 and R256 are 0603 resistors that provide connections to the otherwise unused IPMC RJ45 LEDs. These two resistors are not installed by the assembly house. These two not installed resistors use the "one solder blob" version of the 0603 geometry and thus the problem, i.e. they will leave one solder bump each right under where the RJ45 connectors are pressed into the circuit board. Thus the card will be uneven wher it rests on the platten and could be damaged. Solution - don't make a special geometry for these two special resistors and redo the design to use it - rather just remove from the Side 2 Paste Stencil gerber plot the flash openings for these two resistors. Reading off from the design the centers of these two Paste Stencil openings are at: 15.15, 135.0 and 15.15, 113.0 mm and they are size 1.06 mm X by 1.10 mm Y which is D-Code 166. Dig in the plot file: artwork_22_paste_stencil_bot and yes I can find them. I need to pull out the sequences: X015150Y113000D03* and X015150Y135000D03*. Make a simple script in the .../Tools directory to do this: remove_r255_r256_paste_stencil_openings.sh In the gerber plots made yesterday the 0.125 and 0.120 mm wide traces on some layers in the neck-down and dual-track region under the MegArray connectors have been "painted" using the 0.10 mm aperture or something like that. The problem is that these two apertures were just plan missing from the Aperture Table. I added them by hand to the source file and re-copied the source to version 29 of the Aperture Table. Brought the hub_release_instructions.txt file up to date. There should be no change to the Mentor counts today and only the Comps file version should have incremented. ------------------------------------------------------------------------ DATE: 31-Jan-2017 Topic(s): Edit traces and then generate a new set of Fill, Gerber, Drill, and Back-Drill data comps_1316 is Philippe's latest full text silk version from last night. From production comps build of 22-Jan write comps 1317. When appropriate I would like to purge down the comps files. mv traces.traces_694_original_pre_fill traces.traces_699. Keep the previously made copy of trc_694 as traces_copy_of_694_pre_fill Dump all artwork and drill files from ..../pcb/mfg/ diff nets_638 with source build of 17-Jan and it is good. Edit traces which makes traces_700 Edits: add copper to Gnd and Vout pins on the three 20 Amp converters, add Signal_9 copper to the Iso_12V ouput pins, clean up LED Sig_9 and JTAG Sig_1 routes. Make a copy of traces_700, i.e. traces_copy_of_700_pre_fill With layout Verify counts and that the design is OK. Status: with all fills OUT comps 2925 rev 1317 nets 3780 rev 638 connections 8807 finished 7305 rev 700 unfinished 355 guides 1147 From Layout by hand without saving verify that the new design rules for the 3V3 fill under Trans MiniPOD is going to work OK. Run the generate_all_fills_on_all_layers.sh script. Script completes without showing any errors all Fills in Trc_705 With Layout look at the design with all Fills in: Status: with all fills IN 33 Shapes/Fills concatinated from 60 comps 2925 rev 1317 nets 3780 rev 638 connections 8312 finished 8312 rev 705 unfinished 0 guides 0 Unconnected pin count 51 All of the obvious things look OK so generate drills and gerbers. Run the generate_drill_table_and_drill_files.sh script. Run the generate_gerber_all_24_plots_for_hub.sh script. No errors / missing apertures seen while these scripts ran. Fill generation took 14 minutes Gerber generation took 28 minutes Setup for operation with the current official traces without fills and with Philippe's latest comps with silk text from last night: mv traces.traces_705 traces.traces_705_official_with_fills mv traces.traces_copy_of_700_pre_fill traces.traces_705 diff traces.traces_705 traces.traces_700_official_pre_fill rm comps.comps_1317 mv comps.comps_1316 comps.comps_1317 Verify that this runs OK in Layout and has correct counts, then generate just the SilkScreen Gerber plots with Philippe's latest text, i.e. run the generate_gerber_17_18__silkscreen.sh script. All of the above is correct except that we are now actually running on Traces_715 (with "official" per_fill and with_fills off to the side) and running on Comps 1318 which is actually Philippe's Comps 1316 from last night with his full silk text. Edit the Back-Drill Generator Configuration files to point at the new/current/official traces without fills file and to include the new net from yesterday, "Combined_Data_From_Other_Hub". Generate Back-Drill data. Need to start over with the check of the Back-Drill data. Must rebuild/restore the pcb geometry to pickup the new/current verification circles written by the Back-Drill generator. Done. Run the little scripts to rename the actual back-drill files. Copy them to the web. Note that this new set of back-drill files makes 798 drills in the "Most" region and 154 drills in the "Zone2" region. I'm glad that code and not a human is making these files. Verify what Thermal Relief D-Codes are in the three new Ground Plane gerber files. As expected all three Ground Plane plots are each calling all Thermal Relief D-Codes: 251, 253, 254, 256, 259, 261, 262, 265, 267, 268, 269, 271, 272, 273, 276, 277, 404, 405 and none of the three Ground Plane gerbers are any longer calling aperture 266 the 0.80 mm Thermal Relief that was used only by TI QFN-16 and DCDC-9 thermal/ground via/pins. Both of those geometries have been moved to the standard 0.85 mm Thermal Relief. Because Thermal Relief aperture 266 is no longer in the Ground Plane plots - I removed the line that removes D266 from the script that removes most of the Thermal apertures from the Ground Plane plots - all but D405 which is for the Ground Loops aka Scope Loops. After making this edit to the remove script run the remove_most_ground_thermal_relief.sh script. The new problem found so far in todays gerbers is that the 0.12 mm and 0.125 mm wide traces in the neck-down and dual-track routing under the MegArrays is being "painted" instead of being drawn. I must still have something screwed up in the Aperture Table. At least fixing this should not require touching Traces again - I should only need to tough the Aperture Table and regenerate some Gerbers. ------------------------------------------------------------------------ DATE: 30-Jan-2017 Topic(s): Monday Hub Meeting, Fixing 3 Hub PCB layout problems, Murged in the first new Silk Text the the PCB Geom, Fix Geom problem, Back-Drill Check. Monday meeting with Wade, Pawel, Yuri, Philippe, and Dan. Reviewed current status of Hub layout. Philippe has pushed through the "bulk" reference designator silkscreen and it now working on individual components. Pawel is purchasing a cable to allow more MGT Tests. Yuri is working on register layout. Decide to go forward and try to fix the three currently known issues with the bare pcb: the poor connectivity of the 3V3 Fill on Signal_5 under the Transmitter MiniPOD, the non-standard too small Power Relief on the Thermal/Ground via/pins of the TI flavor of QFN-16 and on the DCDC-9 linear regulator, and the missing piece of copper that makes narrower than expected connections from the output of the 20 Amp supplies to the input inductors of their LC filters. To fix these problems the following files were edited: lt1764_dd_pak_dcdc9.txt qfn_16_ti fill_shapes_signal__5_nom_3v3.txt generate_all_fills_on_signal__5.sh The fill shapes file for Sig_5 was edited to add three new shapes to help carry the current from the 20 Amp DCDC Converters to thrir LC inductor inut 'filters. The fill generation file was edited to put the 3V3 fill under the Transmitter MiniPOD into a design rule clase by itself and to add the generation of the 3 new 20 Amp fills. Note that with the build of the release files tomorrow morning that I expect that all calls for the 0.80 mm Thermal Relief aparture will disappear from the three Ground Plan plots and thus I sould pull the 0.80 mm Thermal Relief removal from the script to bury/ flood the via/pin ground connections into the ground planes, i.e. file: remove_most_ground_thermal_relief.sh Worked on the part of the silkscreen text that is held in the pcb Geometries file - so edited hub_0_pcb_silkscreen.txt and removed some old text from: atca_esd_strip_front_only Philippe found a silkscreen_1 vs silkscreen problem with geometry file: so_package_4_pin. This simple 4 pin part has collected its share of problems. Back-Drill - Start the Careful Check Start with the Zone_2 set of back-drills. Turn on just two Layers at a time: View Signal_10 with PrePreg_12 none match good no signal cuts View Signal_9 with PrePreg_9 all match --> Keep L20 thru L1 View Signal_8 with PrePreg_9 all match --> Keep L20 thru L1 View Signal_7 with PrePreg_10 all match --> Keep L16 thru L1 View Signal_6 with PrePreg_10 all match --> Keep L16 thru L1 View Signal_5 none used View Signal_4 with PrePreg_11 1 used 1 match --> Keep L10 thru L1 View Signal_3 with PrePreg_11 1 used 1 match --> Keep L10 thru L1 View Signal_2 with PrePreg_11 2 used 1 match --> Keep L10 thru L1 --> The "Combined_Data_From_Other_Hub" which routes to Zone_2 on signal_2 is not Back-Drilled. The cause of this problem is that the "Combined_Data_From_Other_Hub" net is not in the official list of nets to be considerted for back-drilling, i.e file: hub_back_drill_nets_and_xy_regions.txt Continue check with the "Most Zone": ------------------------------------------------------------------------ DATE: 29-Jan-2017 Topic(s): Check All Fills In Traces Again, Work on Silk that is part of the PCB Geom itself, check /pcb/ directory structure, Check the "All Fills In" traces file again and this time look at the Un-Connected Pin Count. It is 51 and that does not sound right. It is also 51 when I look at the current official "No-Fills" traces file. See the other checks of the All Fills In traces file in the 27-Jan log book entry. The previous serious look at the un-connected pin count was on 16-Jan (see that log book entry) when, "Unconnected Pin Count = 16 all from J3 Voltage Monitor Connector". How did it get from 16 to 51 and is the same with and without Fills ? 35 new un-connected pins. Duh it must be the emergency pad patterns on the backside of the card that I added on 21-Jan. 1x14 + 1x12 + 1x6 + 1x5 = 37 minus the 2 fixed possition Gnd pins that I connected makes 35. So un-connected pin count is OK with and without Fills. From an over abundange of paranoia I check the current directory structure of Rm2150 .../Hub_0_pcb/pcb/ vs the Durand structure which I captures from the tar from last Thursday. - The same number and names of ces_asci_bla files but the ces_ascii_board did update and is one byte longer than the older one. The previous one was from 17-Jan, i.e. not too long ago so this must be update rather frequently. This appears to be just a Mentor generated ascii geometry of the Hub PCB. It will/should have changed between 17 and 26 Jan. I do not know what the ces_ascii_bla files actually do. - There are no Spares or Gates files or attribute files on either the current Rm2150 machine or on Durand from last Thursday. - Both have ces_hispeed_in.ascii of zero length which seem to update regulary. - All other differences are expected and understood. Work on Silk that is part of the PCB Geometry itself, e.g. labels for the Jumpers. I can start this graphically from Layer with Text --> abc_Prompt_Text then adjust it with Text --> Move and Text --> abc_Change_Text and then File --> Save --> ASCI_Geometry to a temporary junk filename and then grep out the new test lines from the temporary junk file and put them into the appropriate rational organized source file in the Hub PCB Geometry sub-directory. ------------------------------------------------------------------------ DATE: 28-Jan-2017 Topic(s): Removing Ground Thermals, Silk Script to remove the Thermal Relief Flashes for all instances of 18 out of the 19 Thermal Relief Apertures is ready. Still an issue about filenames and to check its output on a fancy diff program. There should be no change in Mentor Counts today. Philippe is pushing on Silk so there are Comps version changes. He has finished the bulk silk work and is today pushing on the one of a kind reference designators. There should be no change in Mentor Counts today and changes only in the Comps Version from Philippe's work. ------------------------------------------------------------------------ DATE: 27-Jan-2017 Topic(s): Check design with Fills In, Meeting with Wade, Concerns so far, Back-Drill check, Removing Gnd Thermals, Silk Hand the traces file with all the Fills In back to Mentor and check that it is OK. I should have done this yesterday before generating the Gerber plots. The design does setart up in Layout OK without errors. Status: with all Fills IN comps 2925 rev 1311 nets 3780 rev 637 connections 8265 finished 8265 rev 699 unfinished 0 guides 0 Shapes/Fills 30 / 30 concatinated from 57 Ran DRC with all Fills In and that looks OK. It does report and there is some not very good coverage in a couple of the Fills. See below. Wade, Philippe, Dan meeting in Rm 2150 to discuss where things are. Review again on Monday with everyone. Problems that I see so far: - The 3V3 fill on Signal_5 under the East half of the Transmitter MiniPOD did not close in around most of its pins. That left only 3 narrow links to get 3V3 to this MiniPOD's 3V3 pins which are near the center of the device. It needs 185 mA of 3V3 and these 3 narrow ties are probably OK but could be made a lot better. The MiniPOD monitoring would let us see its 3V3 value. If redoing then could set up a private Design Rules or pad land size for just this fill. New land dia will require yet another change to the Aperture Table. - The TI QFN-16 geom which is only used for the first stage Fanout of the 40.08 MHz clock has a 0.80 mm Power Relief. So does the heat-sink for DCDC-9. These should be 0.82 mm or more correctly 0.85 mm. This should be a simple geom edit/restore with no other changes to the deesign. Verified that testing the Back-Drills can be done from Mentor display but I have not seriously started this yet. Need to write tests and results as this inspection is made. Worked on removing the Thermal Relief Flashes from the 3 Ground Planes. There are 19 D-Codes of Thermal Relieves and I think that 18 should be removed. I have checked what all of these D-Coldes actually plot. All details are in the top of the file: .../Tools/remove_most_ground_thermal_relief.sh There should be no change in Mentor Counts today. Philippe is pushing on Silk so there are Comps version changes. ------------------------------------------------------------------------ DATE: 26-Jan-2017 Topic(s): Fills, Drill, & Plots Generated Work on Assembly Instructions Generate Back-Drill Data Generate the Fills, Drills, and Gerber plots in that order using the source files: nets_637 from 17-Jan, comps_1309 which is aa_hub_0_comp_file.txt from 22-Jan traces_694_original_pre_fill from 25 Jan geoms_818 from 22-Jan with OnSemi and SO-4 modifications in it apertt_29 which is a copy of apertt_hub_minimum_wagon_wheel with the modifications from this morning in it. Assembly Data Notes: - I need to verify that the Not_Installed_Components file is up to date. - I need to verify that the Component_Descriptions file matches the components that are currently in the design. - Everywhere in the assembly data change 49R9 Ohms to 49.9 Ohms as all of the other resistance values that need a decimal point have switched from R to .. - I needed to edit the Tools make_special_smd_installed_comps.sh script to get rid of: PLLs U502, U506, rivets and scope loops, SC70_5_NO_PASTE_NO_BOM, SC70_6_NO_PASTE_NO_BOM, SOIC_14_NO_PASTE_NO_BOM, TSSOP_12_NO_PASTE_NO_BOM as these are all "component types" that are new since that script was written and these parts are not in the assembly houses work. - I need to add a note to the assembly instructions about things to watch out for: 2 types of caps same uFd value, need the PLLs back, We finish with 1637 capacitors on the card, i.e. 69.5% of the components by count. There are 20 types of capacitors or 19.6% of the component types. Generated the Back_Drill data as per instructions. I did not make a copy of the traces file - rather I just pointed the Back-Drill configuration files to the current official production traces file with out Fills, i.e. traces.traces_694_original_pre_fill Then I edited, as required, the script to build the Hub PCB Geom so that it pointed to the new production Back-Drill data and rebuild the pcb geom and restored it in geoms.geoms_819. Later in the afternoon ran the script to build the SilkScreen plots again with Philippe's Comps file that has all of the Reference Designator edits to date. This ran OK, i.e. there were no aperture problems. The silkscreen gerbers are starting to look much better. The traces files that are available are: traces_694_original_pre_fill and traces_699_all_fills. Which ever one you want to use needs to be coppied to traces_699. There should be no change to counts today. Status: with all fills OUT comps 2925 rev 1310 nets 3780 rev 637 connections 8760 finished 8258 rev 694 unfinished 355 guides 1147 I need to put the "Filled" trace file in a verify <--- that all nets completed in it, i.e. did the fills <--- complete all of the connections ? This had been <--- OK on the previous full fill generation but needs to be checked. ------------------------------------------------------------------------ DATE: 25-Jan-2017 Topic(s): 10**9 runs of DRC, Final ? Trace Work, generate Assembly Data Last night and today made many passes wtih the DRC adjusting the design rules with each step to see when and where things are falling apart. The details from these runs are in the DRC notes file along with the tightest constraints that will still pass the clearance tests with zero errors. Most things are as expected, e.g. the dual-track under the MegArrays is both the tightest routing and the thinest traces. I also re-learned that DRC runs build up a large log file in ../Hub_0_pcb/pcb/check/. During these DRC runs I found two proplems that needed to be corrected: - On Signal_9 under FPGA a 0.13 mm wide horizontal trace that spans about 92.5, 151.5 to 101.3, 151.5 was off the grid, i.e. not centered between FPGA pins. The shift (downward) was small but DRC had no trouble findind it. It's not clear to me how I could have generated such a trace. - On Signal_7 there is a 45 degree run of the net IPMBUS_B_SDA that is centered on about 41.0 36.5 that has tighter clearance that any other out in the open Default net type traces. This is in a mixed bus of 0.16 and 0.18mm traces and has the normal probem of having broken into the 45 deg run 0.1mm too early. Because of the need to fix the above two problems I edited the traces file yet again and used this chance to take care of some other points that had built up in the past 24 hrs, e.g. two power input traces that could expand from 2.0 to 2.5 at their fuse connection, more space available on Signal 7 and 8 to relax their Hardware_Adress and IPMBUS above the input fuses. Ran DRC with default rules after these edit to verify that these two problems had been cleaned up and that things looked OK. I ran the script to generate the basic Hub BOM file and the script to generate the Component Counts and SMD X,Y Placement data. These were run on: comps_1307 which comes from a 22-Jan build of comps but has been handed to Mentor a number of times during silk work, nets_637 from 17-Jan, geoms_818 from 22-Jan, and trc_694 from today. I have started editing the 9 Assembly Files to get them into final shape. Recall that the Aperture Table still needs: 3 new rectangular flashes required by the new/modified geometries (OnSemi QFN-16 and so_package_4_pin) and the new thinner pens for the Silk that Philippe is working on. Except for verson numbers there should be no changes to Mentor Counts today. ------------------------------------------------------------------------ DATE: 24-Jan-2017 Topic(s): Work on the Dual-Track routing in the MegArray and other Zo issues, Clean up the 3 coincident vertices, Major work in traces to the 6 Input Fuses, Ready to Go Widen the center-to-center spacing of the Dual-Track traces to 0.34 mm. Copy the official stalbe traces file to the work area and then diff it to verify that the copy is OK: traces.traces_685_stable_pre_fill --> /Work/Traces_Work/Wide_Dual_Track/traces_original Run the script: aa_widen_dual_track_script.sh Then move the result back to the Mentor side of the design. Generate the widened version again and diff to double check the result and move are OK. /Work/Traces_Work/Wide_Dual_Track/traces_post_move --> traces.traces_690 In the design change all of the dual-track trace widths from o.13 mm to 0.125 mm. This should set us up at about 1/2 Ohm above what the 0.14 mm width on 0.40 mm centers will be after the board house adjusts this to 0.13mm on 0.40 mm centers. The tues_2 backup is the first one with the dual-track space widened to 0.34 mm and the width narrowed to 0.125 mm (this is traces 691) and still has the traces.traces_685_stable_pre_fill file. Then as the 2nd part of the Zo clean up to match the expected Hub Stackup do the following: - Only within the dual-track under the MegArrays, and only on layers: Signal_7, Signal_8, and Signal_9 reduce the trace width from 0.13 mm to 0.125 mm. Note that the neck-down segment and and the segment adjacent to the MegArray pin remain at width 0.13 mm. The 0.34 mm center to center and the 0.125 mm width should match the standard high-speed diff pair routing of 0.14 mm width and 0.40 center-to-center spacing. - Only within the dual-track under the MegArrays, and only on layer Signal_6 reduce the trace width from 0.13 mm to 0.12 mm. Note that the neck-down segment is set to 0.125 mm width and and the segment next to next to the MegArray pin is also set to 0.125 mm width and that the segment adjacent to the MegArray pin remains at width 0.13 mm. This special treatment of Signal_6 is required because the the special dielectric thickness used between L13 and L14 Stackup layers. - Only "under" the FPGA, i.e. only the 0.13 mm MGT routing on layer Signal_5, change the 0.13 mm width to 0.125 mm width to match the expected Hub Stackup. This special handling of the nominal 0.13 mm MGT highspeed traces under the FPGA only on layer Signal_5 is required because of the special dielectric thickness used between L9 and L10 Stackup layers. - Note that the standard reduction from 0.14 mm to 0.13 mm "under" the FPGA and "under" the MegArrays for just layers: Signal_1 and Signal_10 should work OK as is with the Hub Stackup because these are MicroStrip routes not internal StripLine routes and because of the special dielectric thickness is used in the Hub Stackup between L1 and L2 and between L21 and L22. - Note that design rule changes are needed, i.e. the smallest air gap between high-speed diff pairs is now 0.21 mm and they get closer to MegArray pins by 0.015 mm. Complete the modifications to the traces that connect the Input Fuses F1 : F6. These modifications are described at the end of the file: hub_0_ab_trace_routing_strategy.txt with some additional changes to this routing strategy added today. In general there was a 25% increase in the amount of copper connecting to these fuses. I think that the best uses of all layers has now been made in these high current connections. Status: with all fills OUT comps 2925 rev 1303 nets 3780 rev 637 connections 8760 finished 8258 rev 693 unfinished 355 guides 1147 The good traces file before the work today is: traces.traces_685_stable_pre_fill Close at trc_693. ------------------------------------------------------------------------ DATE: 23-Jan-2017 Topic(s): Meeting with 4x MSU Yuri and Pawel Additional/Modified Routes to Input Fueses Monday Hub Meeting. We will not have a Tuesday Ian Hub Schedule meeting. The advertized current hope is to have files ready on Wednesday. Work on getting more copper into the routing of the Input Fuse traces. See the end of the file: hub_0_ab_trace_routing_strategy.txt for current information about the routing to the Input Fuses F1 through F6 and for the new setup. Can bump many/most of these traces out to 2.5 mm and they will all have at least 2.5 oz of copper. Worked on moving all of the Dual-Track routing under the MegArrays out by 0.02mm in each direction. This will put the air gap between these differential traces at 0.21 mm. No change in counts or versions. ------------------------------------------------------------------------ DATE: 22-Jan-2017 Topic(s): Restore Geoms, Sundry Comps, Design Rule Checks, Note Resetore the 6 new/modified geometries from yesterday. Now at geoms_818. Moved the sundry comps to pickup the no_paste no_bom version of the spare pad layouts on the backside of the card. Edited the Aperture Table to include the 3 new rectangular flashes required by the new/modified geometries. Continue running DRC. The high-speed diff pair is done and looks OK but has one more step in its clearances than what I was expecting. All details in the DRC notes file. Note to Wade - no release on Monday hope for all but silk on Wednesday. No change in Mentor counts. ------------------------------------------------------------------------ DATE: 21-Jan-2017 Topic(s): Work on Geometries, Philippe working on Silk Worked on the following Geometries: connor_winfield_sfx_524_geom.txt sc70_5_no_paste_no_bom sc70_6_no_paste_no_bom soic_14_no_paste_no_bom so_package_4_pin tssop_12_no_paste_no_bom 5 of these geometries are only used for components that will not be placed on the pcb at the assembly house - thus I want to remove them from the BOM and I do not want Solder Paste on their pads - thus the needed modification / new versions. The 4 pin SO package is for the opto-coupler that turns ON the ATCA Isolated 12V supply. I had an IPC compliant foot print for this component but while checking geometries Brian did not like the way that it looked with its pads running so far under the body of the opto-coupler. I agree with him so I modified the SO 4 geometry to have shorter asymmetric SMD pads. Because of the new pad shapes for the so_package_4_pin and the new Solder Stencil window opening shapes for the Fanout chips I need to append 3 new apertures to the Aperture Table. I will wait to do that until Philippe is not running Layout to work on the Silk. I need to re-build the Components file from sources to pick up the new geometries for the 4 backside spare pad patterns with no_paste and not in bom. I will wait to do that until a time when I will not confuse things with the current work Philippe is doing on Silk. There should be no change in Mentor counts. The correct traces is traces.traces_685_stable_pre_fill which has been coppied to and is running as traces.traces_690. The last build of Comps from sources was comps.comps_1299. Philippe is digging into bulk modification of the Silk in the Fanout section. He may have a nice way to keep the reference designator modification information separate from the actual component placement information in the comps file. I may be able to bulk fix the Silk Ref Designators for the Iso_12V bypass capacitor arrays by modifying the special geometries that are used only for those parts. ------------------------------------------------------------------------ DATE: 20-Jan-2017 Topic(s): Work on MegArray and FO Chip geometries, Wade meeting, Philippe started looking at Silkscreen editing. Finished the MegArray geometries. They look OK and basically have all of the added ground links that look practical - but none were added immediately adjacent to the MGT diff pin pairs. Studied the QFN-16 for the OnSemi Fanout chips. It is small and tight with very little center pad to perimeter pad clearance but on reviewing everything I think that it looks OK. OnSemi recommends very small perimeter pads (compared to other QFN layouts) but maybe that's because this is a very high frequency device. Anyway it's basically exactly what they recommend which requires very accurate Solder Mask work. The only change that I made was to decrease the overall stencil opening from about 75% to about 71%. With the small perimeter pads there will be little paste out on them so I do not want this part floating up in the center. Note that I will need to add another aperture for the new OnSemi QFN-16 Solder Stencil Window. Wade stopped by to ask about schedule for the Monday meeting report. Philippe fired up layout and is looking at the silkscreen. Philippe has checked the RJ45 stuff and it looks OK. Yuri reports that the Configuration stuff looks OK. ------------------------------------------------------------------------ DATE: 19-Jan-2017 Topic(s): Work on the MegArray Geom There has to be two versions of the MegArray geometry, one for S1 and one for S2. There are now 19 types of pin/pad stacks used in this geom. The MGT differential signals have their own set of 4 stacks with the 0.13 mm dog-bones and small pin vias. There is another set of 4 with 0.25 mm bones and small pin vias for use as grounds in the area where all of the MGT traces run through them. There is a 0.25mm bone with normal 0.30 mm drill via for the rest of the signals. There are two versions of the SMD pad that does not have its own private pin via (two bones to the right or left) and there is an SMD pad only for signals that escape on Signal_l. The MGT pin/pad stacks do not have an oval ground relief. Including that broke up the ground under the connector too much. They do have generous circle ground relief. Note that pins for MGT differential pairs are needed in 3 non-standard locations in S2 and that in one of the standard locations in S1 the pins are no-connects and thus use the small pin via with full dog bone version of the stack. Besides needing to make a good ground connection to the SMD Ground Pad that does not have its own private pin via I have also included where possible Ground Links between ground pin vias and or ground pads on the Signal_1 layer. The intent is to both make this ground connection as electrically stiff as possible and also to give the best possible adhesion of the SMD pads to the pcb. No added ground links were placed where they could increase the capacitive loading on the MGT signals. The SMD pads have solder mask and stencil to match the FCI recommendation and now have standard setup of these spacets of their pin vias. Note that I need to change the ConWin PLL geometry to remove its stencil openings as this part will not be assembled onto the card during MSU Final Assembly. It would be nice to have time to do the same for the space pad patterns on the back. No change in Mentor Counts today - Fills are out. ------------------------------------------------------------------------ DATE: 18-Jan-2017 Topic(s): Finish Switch Chip Geom, Clean up ROD silkscreen, Work on MegArray Finished the paste_mask aka solder stencil last night for the Switch chip and that geom now looks OK. It is setup with the pcb thermal ground land that Broadcom recommends but has a normal solder mask with one opening and a solder stencil with 12 openings. This solder stencil gives paste application at 80.4% of the area of the IC's 8.79 mm by 7.62 mm Center Pad and is 59.8% of the area of the PCB's 10.0 mm by 9.0 mm Thermal Pad. This should all be OK. Note that the Switch Chip Geom does use 0.10 mm wide Solder Mask webs between the 0.40 mm pitch pins of the Switch chips. Appended 4 more apertures that are needed to support the new Switch chip Geom. I understand the 2 new rectangular flashes but currently I do not the two new circular flashes of 0.21 mm and 0.46 mm diameter. Cleaned up the silkscreen for the ROD components on the Hub Module. Some of this was at a wide non-standard width and some of it had out of date text. This looks ready for prime time now. Recall that the Hub's MegArray connectors are actually placed via the ROD components on the Hub as a Relatively Positioned Component Set, i.e. one can not just randomly play around with this ROD stuff. Start the attack on the MegArray Geom. Recall that because of the way that it is pinned out on ROD/Hub that the MegArray is actually two separate geometries. Cleaned up the various relieves and mask clearances and such and then made its small pin Via pad/pin stacks in the standard for Hub. Note that the MegArray needs two separate sets of small pin Via pin/pad stacks, one for the High-Speed MGT signals (that have a narrow Dog-Bone) and one (with a thick Dog-Bone) for the forest of Gnd connections that the dual track MGT Diff Pairs have to route through. I think that there are 19 pin/pad stacks used under the MegArray conn. Looked at adding an oval ground relief around the MGT Diff Pairs. This does not look good because pulling the web out of every other Gnd pin pair leaves the center section too isolated. So I gave up on this. In any case it should be happy with 1.05 mm of Gnd relief from the 0.25 mm Drill and 0.52 mm via pads. This leaves a web between every pair of adjacent Gnd pins of 0.22 mm. Looked at adding links to make a better connection to the SMD Gnd Pads that do not have a private pin Via. This looks OK and clean. The result looks symmetric, and all MGT Diff Pair Pins have the same Ground Environment, and there is good isolation between the two MGT columns. The only issue is that it takes a lot of typing to implent this and because it is all hand work it need to be carefully checked. I have these links added to MegArray S1 and will work on S2 tonight. Status the Fills and Plots are all removed for the above work. ------------------------------------------------------------------------ DATE: 17-Jan-2017 Topic(s): Ian Hub Schedule Meeting, Fixed more typos in nets files, work on the Switch Geometry. Hub Schedule Meeting with Ian and 4x MSU. Ian would like us to say the the Hub has been released in next Monday's L1Calo meeting. Fixed the "typos" that Philippe's checking process dug out of the Hub's Net List files. Incorrectly named No_Conn pin pair in: clock_generation_nets Inconsistent and confusing HUB vs Hub in: gth_fanout_nets_template.txt Wrong and dangerous 12C vs I2C in: atca_power_entry_nets and: ipmc_hw_adrs_handle_switch_ipmb_nets Made the edits and rebuilt the design and the Mentor counts are did not change (as expected because none of these typos should have caused an actual design error). I believe that both Brian and Philippe have signed off on the design. Worked on the Switch geometry. I've pulled out all of the Broadcom stuff about Solder Masked defined Thermal Gnd pad and 56 octagonal openings in the Solder Stencil. I've kept the size and hole pattern recommended by Broadcom for the pcb's thermal land but: will go to a standard 0.30 mm Drill, go to a standard non-solder-mask defined pcb land, go to a standard 12 window solder paste stencil, with all window openings within the foot print of the thermal pad on the IC, the sum of the stencil openings is about 78% of the area of the IC's thermal pad, and is about 55% of the area of the pcb's thermal land. Still working to implement this. Note that this will very likely require a new Gerber aperture. ------------------------------------------------------------------------ DATE: 16-Jan-2017 Topic(s): Hub Monday Meeting, work, Status of the To-Do List from a week ago. Hub meeting at new 10AM Monday time, 4x from MSU and Pawel and Yuri. Ask Yuri to look at the Bank #0 Configuration and power up section of the Hub design and the FPGA JTAG connection. He designed this on the VAT card so he should be in a good position to look at it. Decided to make the default to Enable the Equalizers on the MGT Fanout chips as that fits best with the experience that Ed has had. Fixed errors with the PLL Lock Det pin numbers in drawings 40A and 41 and an error with the Transmitter MiniPOD active fiber count in drawing 48 - problems that Yuri had found. Added 4 emergency pad layout patterns to the backside of the card: soic_14, tssop_12, sc70_6, sc70_5. Because the pinout of an likely sc70 components is so fixed I went ahead and made the ground connection to these packages but not the Vcc connection as I don't know which but it might be. Make another DRC run with the same rules. It still looks OK. I still need to take care of the three coincident vertexes that are found by the DRC run. I should have done that today while editing the traces. Run Fills, Drills, and Gerbers and move to the release 3 on the web - almost totally unchecked on Monday. Review of the Status of the items in the Hub To-Do List from one week ago. 1. No changes have been requested. 2. Done 3. Done 4. The first two items are now fully understood. There are multiple ways to accomplish the 3rd item - which one is best to use is still being looked at ? 5. Done 6. FPGA, MiniPOD, and Diff Via Pair are all final. Still working on the MegArray geom. 7. Still working on the MegArray geom. 8. Not started but it straight forward defined work. A couple of hours 9. I need to talked to bare board and assembly house. We have successfully built with this QFN-16 package before but I want to understand the details. 10. Checked and some aspects are OK but not others. Easiest solution is to not install this part at assembly house. They will be installed during MSU Final Assembly with Kapton tape between. 11. DRC ran again OK today with default rules. Still need multiple runs cranking down the rules. 12. Done 13. Done 14. Done all OK on current plots 15. Not started yet - but we have a plan. 16. On hold until other steps are finished. 17. Done - not exactly what was in the original list but the Power Via Arrays are finished and ready for release. 18. Backplane connector Done. Still working on MegArray. 19. Brian and Philippe and mostly Done with this. They should comment who has checked what. Making this design review has generated 3 or 4 points that needed to be looked at. 20. A fresh cut of all this release data was generated late Monday. Just starting to look at it. 21. This is is understood well enough that I'm waiting for the final pass of step 20 before doing it again. 22. Waiting until final pass of step 21. 23. Waiting until final pass of step 20. 24. Waiting until final pass of step 20. 25. This is understood well enough that I'm waiting until final pass of step 20 before doing it again. 26. This is understood well enough that I'm waiting until final pass of step 20 before doing it again. Status: with all fills IN comps 2925 rev 1298 nets 3780 rev 636 connections 8245 finished 8245 rev 690 unfinished 0 guides 0 30 Shapes 30 Fills (count are concatinated from 57) The counts show that the design looks complete. No errors when tool opening. Unconnected Pin Count = 16 all from J3 Voltage Monitor Connector. The good traces file is: traces.traces_685_stable_pre_fill Traces_690 has all Fills in. ------------------------------------------------------------------------ DATE: 14/15-Jan-2017 Topic(s): FPGA Geometry with special MGT pins Moved the FPGA geometry to include special Small Via pin for its MGT high-speed differential pairs. The 212 pin list of active MGT differential pairs comes from the file: hub_0_ab_fpga_mgt_transceiver_usage.txt Removed from this are the 36 MGT pin pairs that make their escape from BGA pads only on layer Signal_1. The overall major revision of the FPGA geometry stays a 2 as this change was implemented as a sed take file edit of the normal tailored version #2 flvc_2104 geometry. All of the details are in the file: rev_2_final_manual_modifications Recall that the Fill Generation design rule for Hi-Res High-Speed traces now must be edited to give 0.03 mm more clearance. ------------------------------------------------------------------------ DATE: 13-Jan-2017 Topic(s): Zone-2 Backplane Conn Ground Relief FPGA BGA Layout Final, Power Via Array Added an Oval of Ground Plane Relief around each pair of pins that make up a differential signal. A 1.30 mm aperture is used to make these ovals to match the ground plane relief in the basic backplane connector geometry. Did this for all three forms of the Zone-2 backplane connectors. Final work on the U1 2104 pin FPGA Geometry. Two things needed to be done: - Final review of all the Power/Ground/Select_I/O pins to make certain that they match: Xilinx suggestions, and what the board house can do, and what IPC Class II requires. The Power/Ground/Select_I/O pins are based on a 0.30 mm Drill and use a thicker dog-bone. - Move all of the MGT pin pairs that are used in the Hub design to have a via based on a 0.25 mm drill with a 0.52 mm pad land and a narrower dog-bone. For background reference recall how the CMX was setup: Surface Pad Padstack: land pad 0.45 mm Solder Mask 0.55 mm Paste Mask 0.45 mm Through Hole Pin Padstack: all Pow,Gnd,Sel_I/O all layers 0.16 dog-bone finished hole diameter 0.30 mm land pad 0.61 mm plane relief 0.85 mm --> ring width 0.155 mm --> plane isolation Air Gap 0.120 mm from the pad Blind Pin Padstack: MGT only Sig 1:3 only 0.14 mm dog-bone finished hole diameter 0.25 mm land pad 0.56 mm plane relief 0.85 mm --> ring width 0.155 mm --> plane isolation Air Gap 0.145 mm from the pad From the Xilinx Gods for Virtex UltraScale: They say make the: UG1099 UG575 --------------------------- ------- ------- BGA Pad Land 0.51 mm 0.53 mm in diameter BGA Pad Solder Mask Opening 0.54 mm 0.63 mm in diameter Dog-Bone Width 0.15 mm --- Via Finished Hole 0.25 mm --- in diameter Via Pad Land 0.48 mm --- in diameter They say that for the best re-flow soldering of the BGA, they want the PCB BGA Land Diameter to match the diameter of the pad on the device package. Note that there are some significant changes compared to the CMX Virtex-6 package. Basically Xilinx went to a larger ball size and larger pad diameter for their UltraScale package. IPC Class II says: 0.25 mm drill --> 0.50 mm pad land dia minimum 0.30 mm drill --> 0.55 mm pad land dia minimum What I have done for the Hub FPGA: Final Irrivocable Decisions For all of the BGA Ball SMD Pads: BGA Pad Land 0.52 mm in diameter BGA Pad Solder Mask Opening 0.62 mm in diameter BGA Pad Solder Paste Mask 0.52 mm in diameter --> edge of Via pad to solder mask 0.050 mm --> clearance to adjacent via pads 0.157 mm --> narrowest point of Solder Mask 0.177 mm For all Power, Ground, Select I/O pin Vias: Via Finished Hole 0.30 mm in diameter Via Pad Land 0.58 mm in diameter Via Solder Mask Opening 0.44 mm in diameter Via Plane Relief 0.82 mm in diameter Dog-Bone Width 0.16 mm --> via donut width around drill hole 0.140 mm --> via drill edge to plane clearance 0.260 mm --> via drill hole edge to solder mask 0.070 mm --> edge of Via pad to solder mask 0.070 mm --> narrowest point in solder mask 0.177 mm --> width of Gnd Web between pins 0.180 mm For MGT signals only pin Vias: Via Finished Hole 0.25 mm in diameter Via Pad Land 0.52 mm in diameter Via Solder Mask Opening 0.44 mm in diameter Via Plane Relief 0.82 mm in diameter Dog-Bone Width 0.14 mm --> via donut width around drill hole 0.135 mm --> via drill edge to plane clearance 0.285 mm --> via drill hole edge to solder mask 0.095 mm --> edge of Via pad to solder mask 0.040 mm --> narrowest point in solder mask 0.177 mm --> width of Gnd Web between pins 0.180 mm The FPGA pins that will use the smaller via pin setup is limited to the MGT signals pairs that are listed in the file: hub_0_ab_fpga_mgt_transceiver_usage.txt. Once the FPGA Geometry with the smaller MGT signal pins is in use then I must crank up the Fill Generation Design Rules for the Hi-Resolution Fills of the High-Speed Net Type. The via pad diameter decreased from 0.58 mm to 0.52 mm which means that I may crank up the design rule for Fill to Via/Pin clearance by 0.03 mm. That is the overall goal and benifit of this work, its small but its a 25% increase in clearance. Returned the Power Via Array to the nominal 0.46 mm size. The actuall Drill will obviously be bigger than 0.46 and should be just about the best match for the PVA for maximum tunnel to plane circumference without cutting too far into the web between pins. ------------------------------------------------------------------------ DATE: 12-Jan-2017 Topic(s): Final Shape adjustment, Silk work, Move to minimum pads on High-Speed signals, Power Via Array to 0.50 mm Yet one more adjustment of the Iso_12V Main and DCDC-7 Shape. Currently all Hi-Res Fills under the FPGA look OK. I think that the final Hub Module Shape / Fill counts are: 57 Fills 48 Shapes 6 Shapes defined on Signal_6 3 Shapes defined on Signal_1 22 Shapes defined on Signal_11 8 Shapes defined on Signal_5 9 Shapes defined on Signal_12 Finally got the "Mill Here" silk on the back side and straightened out some of the obvious stuff in the current front side silk that would not work, e.g. silk over copper that msut be soldered, June 2016 date. Final irrevocable decision about the High-Speed via/pin land diameter. 0.52 mm land diameter with a 0.25 mm drill diameter - the Dill diameter is to be specified as a Finished diameter with a tolerance of +0% -100%. This will just get the Hub class II compliance with its 3.05 mm thickness. Start the work to move all of the following to this size land and drill for just their High-Speed signal pins: FPGA, Differential Via Pair, MiniPODs, and MegArrays. This does not affect the backplane connectors. Note that the Aperture Table will need a new Flash to plot this. May be able to recycle the 0.56 mm but probably best to add by hand a new 0.52 mm. - MiniPODs and Differential_Via_Pairs have been modified - Aperture Number 308 added by hand to the Aperture Table. - MegArray working on it - FPGA working on it Modified the 9 Power_Via_Arrays Geometries to move from their current 0.46 mm Drill to a 0.50 mm Drill. This is pin/pad stack is defined in x3y1_power_via_array. Note that this looks more or less OK as the spacings that I have in these arrays are all between 1.00 and 1.50 mm center to center. Final decision. ------------------------------------------------------------------------ DATE: 11-Jan-2017 Topic(s): regenerate all fills, drills, and gerbers Needed 3 or 4 passes at generating Fills to get everything corect, i.e. the 0.40 mm border in hi-res, restoring rational design rules for all three net types after cranking them around to generate the fills. The Fills on Layer 1 add about 0.849 MByte The Fills on Layer 5 add about 3.174 MByte The Fills on Layer 6 add about 3.097 MByte The Fills on Layer 11 add about 5.668 MByte The Fills on Layer 12 add about 6.232 MByte So just doing them in numeric layer order sould be about the fastest. Status: with all fills IN comps 2921 rev 1296 nets 3780 rev 635 connections 8243 finished 8243 rev 684 unfinished 0 guides 0 30 Shapes 30 Fills (note that fill count is concatinated) The counts show that the design looks complete. No errors when tool opening. Unconnected Pin Count = 16 all from J3 Voltage Monitor Connector. The good traces file is: traces.traces_663_stable_pre_fill Note that as the through hole vias/pins for the high-speed signals are cranked down in diameter that the fill to via and pin for the high-speed net type will need to be cranked up. The point is, that as the via/pin land diameter goes down, one holds the fill web width constant, and thus gains wider spacing between the via/pin land and the closest fill copper. ------------------------------------------------------------------------ DATE: 10-Jan-2017 Topic(s): Video meeting with Ian, Ed, and 4 MSU Add Isolation Shields, New fills and art Video meeting with Ian, Ed, 4x MSU, and one other persion (a L1Calo manager I assume). Ian and the manager say that major explainations will we necessary because the Hub is so late. (Note that in the last 3 days management has more or less cost this project 1.5 days.) Ed has good news: they have separates the ROD and Host many times with no problems and he looked at the fanout on the Host with no input - after it's first stage no osc/noise - after 2nd stage some osc/noise - turn on equalizer and after 2nd stage no osc/noise. All good. Worked on the Shapes of Sig_1 Isolation Shield Fills between Hub and both ATCA Modules and ROD. Added 180 Ohm 0805 resistors between the Isolation Shields and Hub signal ground (picked that value because its rational and already in the design). Wrote the script to generate the Sig_1 Fills. Things should be ready to rock and roll again with this in it. How to re-wind if necessary: - Today there is one new comps file and one new nets file. The only change that should appear in these is the addition of the resistors that connect the isolation shields to Ground. - The "old" stable pre-relase traces file rev 658 was moved to 662. I did this to remove all of the fills generated at the end of last week. So Rev 662 is the stable traces file from Jan 6th. - Traces Rev 663 differs only in that: it contains the connections to the resistors for the isolation shields, one Chassis Gnd trace near R992 was moved, and the Signal_12 traces between the two ATCA modules were fattened to 2mm. Rev 663 is the stable version before the new round of fills. - Geoms increment a number of times today and the PCB geom went throug 5 or 6 revisions to work more on Shapes on Sig_1. Status pre try release: nets_635, comps_1296, traces_663, geoms_773, apertt_27 comps 2921 rev 1296 nets 3780 rev 635 connections 8738 finished 7236 rev 663 unfinished 355 guides 1147 ------------------------------------------------------------------------ DATE: 9-Jan-2017 Topic(s): Ian L1Calo Meeting, Jobs to do Wade, Philippe, Brian Dan meeting, Shapes, Aperture Table Monday morning (MSU time) meeting with L1Calo. Told Ian the state of the Hub design, that the parts kit and PO were in place, and said that I would send him my to-do list. He said that he would setup a meeting on Tuesday to discuss the Hub release. Also I have exchanged notes with Ian and Ed about my continuing concerns about the Fex MGT Data Fanout. Afternoon meeting with Wade, Philippe, and Brian. Reviewed the to-do work list which is now on the details page of the Hub's web site. Job assignments: Brian will continue Geom checking and in parallel start pin_numb-net_name-pin_name checking to be done in coordination with Philippe. Later Brian will do the resistance / voltage drop estimates of the high current sections of the pcb layout. Philippe will generate the pin_numb-net_name-pin_name list from the current design data (which may change by epsilon by the time the design is released) and will look at the possibility of setting up "in bulk" the silkscreen reference designators for the MGT Fanout and the three Switches Chips, and in coordination with Brian we will start proof reading the pin_numb-net_name-pin_name list. Philippe will also look at the Switch Chip date sheets and report back whether or not it is possible to use data in the Switch's PROM to operate the Hub's front panel LEDs, with their current wiring, and display the desired Ethernet Switch information. This is not asking for actual programming data at this time - rather just asking is this possible. Dan will start in on other points on the to-do list. All will work on the final by hand clean up of the Silkscreens (which can only start after Philippe's attempt handle in bulk the Fanout and Switch sections), all will work on checking the final release files, e.g. gerbers, drills, instructions ... Worked on yet another round of clean up of the Shapes. The intent was to fix the rough 45s on Art 5 and 8. Also noticed a good way to fatten up the FPGA_Core fill on Sig_11 at some (I hope) minimal cost to that layers AVCC fill. Figured out some of the problems in the Aperture Table: Duh I added the perimeter rivets and ground loops and thus needed to picked up more apertures for the Gnd plots. Duh I had started mixing up D-Codes and Aperture-Positions. Still question about flooding all Gnd vias into the Gnd planes. No change in Mentor Status should have happened today. ------------------------------------------------------------------------ DATE: 8-Jan-2017 Topic(s): Update web directories and send email, HP Switch LEDs Update the In House Release 3 directory on the web. Sent the pre Monday meeting note to Ian and Ed, the to do list to Wade, and the Switch LEDs as currently implemented on the Hub notes. Saturday night re-probed the HP Switch LEDs - results: The front panel "Speed" LEDs connect to Switch Chip pin names: LEDP 0, 4, 8, 12, 16, 20, 24, 28 The front panel "Activity" LEDs connect to Switch Chip pin names: LEDP 1, 5, 9, 13, 17, 21, 25, 29 These are the first 2 LED pins in each group of 4 LED pins. In all cases the Switch Chip LED pin is connected to the LED Cathode and the LED Anode is connected through a series resistor to the 3V3 supply. I.E. Low Active switch chip output illuminates the LED. ------------------------------------------------------------------------ DATE: 7-Jan-2017 Topic(s): Work on getting files released for the Monday morning meeting. The gerbers from Friday are junk because of the Aperture Table problem with the 3 Ground plane plots. It's not understood what changed to cause these missing Apertures. Details in the Friday logbook entry. - Dump all of the Friday plots because I want to see what all of them look like with the new Aperture Table, i.e. will there be new problems on other plots. - Do NOT dump the Fills, i.e. continue with these fills that have their own known issues, i.e. do NOT back up to traces_658. - Try "appending" to the Aperture Table. Doing this gets us 6 new "Normal" apertures one of which I already knew about and had already put in by hand. Doing this gets us 2 new "Power aka Thermal" apertures both of zero Diameter and I do NOT yet understand this. This is Aperture Table Rev. 27 both Mentor and my minimum wagon wheel versions. - Crank out 24 new Gerbers There were no fatal errors during the generation of this set of Gerbers. They more or less look OK and I have copied them to the web for the Monday meeting. The two things that I spotted during a quick look: Need to fatten the Iso_12V input traces on Sig_12 to match the other layers. The width of the circles on the Silk layers for the ROD and FP Bracket mounting screws is wrong. - The current mentor versions that were used to make these Gerbers are are: nets_634, comps_1295, traces_662, i.e. equal to all filled traces_658, geoms_768, apertt_27 ------------------------------------------------------------------------ DATE: 6-Jan-2017 Topic(s): "Cleanups", Fill & Plot, Switch LEDs Made it through a few more of the required "cleanups": - Gnd Planes now releived along Top and Bottom Edge - ISO_12V converter pad Dia and Plane Releif Dia now more or less OK - RJ45 Condo Gnd SMD pad now OK without Paste Stencil opening. - Art_6 45 deg Hi Res boarders moved 0.5 mm under U1 - Art_7 Zero connectivity of Iso_12V to SWCH_1V2 DCDC is now fixed at the expense of making this are of Art_6 worse. Design Rule Checks: - I started a Hub design rule checks notes file in the Text directory. - A quick run of the design rule checks shows no serious problems with the traces_658 file using the design rules that were in effect during layout. - There are 3 instances of overlapping vias (which look like they may be unintended reduntent trace segments). - Recall that there are separate design rules for the 3 types of Trace Attributes used in the Hub design. - I still need to crank up the design rules and see where things fall apart. Now work on Fills: - Will do all fills first even though this takes longer it eliminates the routing via problem seen in Art_2 (and others ?) near the East Switch. After all fills then start Gerbers. - Hold traces_658 as the stabe good version before fills added. - Need to edit the bio robot instructions with these two changes. - Status with traces_658 all fills out: comps 2918 rev 1295 nets 3777 rev 634 connections 8732 finished 7233 rev 658 unfinished 352 guides 1147 ------- - Status with traces_658 all fills IN: comps 2918 rev 1295 nets 3777 rev 634 connections 8237 finished 8237 rev 662 unfinished none guides none ------- 27 Shapes 27 Fills (note that fill count is concatinated) The counts show that the design looks complete. - A significant problem with all Hi-Res fills under U1 is that the design rule for the fill to fill spacing calls for 0.50 mm but all of the shapes are designed for a 0.40 mm fill to fill spacing. - Note that the 45 deg Hi-Res boarders under U1 on Sig_6 Artwork_8 (12 moves in X of 0.5mm, i.e. 48 coordinates) still need to be changed to get optimum boards. - Note that the 45 deg Hi-Res boards under U1 on Sig_5 Artwork_5 (3 moves in X of various amounts, i.e. 12 coordinates) still need to be changed to get optimum boards. Now work on Gerber Plot generation: - Now run the Gerber generation scrips. These run OK but all 3 ground plane plots fail with missing apertures. Why has this changed since Dec 19th ? - That is gerber plots: artwork_13_gnd_plane_Ls_2_4_6 artwork_14_gnd_plane_Ls_8_10_13_15 artwork_15_gnd_plane_Ls_17_19_21 all fail because they are missing apertures: Shape Type Dia. Power ? ------ ----- ---- ------- Circle Flash 4.00 False Circle Flash 1.50 True Circle Flash 2.10 True - What has broken in the aperture table or changed in the Ground Plane design since this last worked ? - The Hub Module Aperture Table is complicated because it currently has 318 apertures with 17 Power apertures. - Note that the Power apertures are currently known to have NOT correct definitions. Exactly what to do to burry these connections is not known. Switch Chip LEDs: - Late afternoon Philippe showed me his analysis of the Switch Chip LED connections. This is based on the data sheets for the Switch Chips. - If his reading of the data sheets is correc then the PCB layout is screwed up in at least 3 ways: - Different SWCH chip pins must be used to drive the LEDs (i.e. must us 0 & 2 not use 0 & 1 as in the current design). - Some LEDs need to be driven Active HI (vs all 32 driven active Low in current design) this would require: + SWCH Chip routes to the LED Anode (all current routes are to LED Cathode) + LED "power connection of Cathode to Gnd (currently all LED "power connections" are Anode to BULK_3V3). - We agree that over the weekend Dan will re reverse engineer the HP switch that uses the earlier version (but pin compatible) of the Hub's SWCH chip and verify again how its LEDs are connected. - Recall that this HP Switch has the LED indicators that are wanted for the Hub Module, i.e. Speed (100 vs 1G) and Link Activity. ------------------------------------------------------------------------ DATE: 5-Jan-2017 Topic(s): Scope Hooks, Mechanical Holes Finished the perimeter rivets (made them bigger) and added more Scope Hook ground points. Doing that required moving some traces and other components. While editing traces I tried to get more copper in the high current Iso_12V module output and the power feed to it. Worked on the mechanical holes for the front panel mounting brackets and the Top ATCA handle. I think that these are now plotting correctly, i.e. copper on top and bottom and none on any internal layers. I need to verify that the various screw hole component pins are also plotting correctly, i.e. the MiniPOD screw holes, the Hub Heatsink screw holes, the ROD mounting screw holes, and the Bottom ATCA Handle screw hole. All of those are electrical component pins that ties to various grounds. Status: with all fills out comps 2918 rev 1295 nets 3777 rev 634 connections 8732 finished 7233 rev 657 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 4-Jan-2017 Topic(s): Meeting: Wade, Philippe, Brian,Dan Finally finish the HS routing, Global Fiducials, Rivets, Scope Hooks Wednesday meeting - discussed status getting the Hub ready to release. Now estimate another in-house release on Friday of this week which will be advertized to Ed and Ian and a release for manufacturing on the 16th. Also discussed going forward with a MSU build of FTMs. Finished up the re-routing work on all of the high-speed traces. Mostly things looks OK. The cross-over of the backplane input of the readout data from the Other Hub is a problem because the only layers available to route this leaves a significant stub. One of the Transmitter MiniPOD data lines (fiber #1) does not yet look very good and could/should be cleaned up. Started work on some of the other things that need to be finished before the design can be released. Today I put in the Global Fiducials and about 40 rivets around the perimeter and along the high-speed bus up to the ROD. I need to add the locations of the Global Fiducials to the assembly instructions: 290, 312 10, 315 15, 23 274,15. Status: with all fills out comps 2912 rev 1289 nets 3777 rev 633 connections 8667 finished 7168 rev 654 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 3-Jan-2017 Topic(s): Finish Sig_9 MGT Routing Transmitter MiniPOD Routes Finished the Signal_9 MGT routes. Now all MGT Fanout routes (in from backplane, out to ROD, out to Hub) are finished and trimmed with the new style bends. Started work on final clean up of the transmitter MiniPOD MGT routes. In this work I needed to swap 4 of the high-speed trace pairs to get a length match. One pair needed a double swap and in doing that I may have caused a problem. This is almost finished except for the screw up with the Fiber 1 lines right now. May need to back up to traces 649 to recover this. traces.traces_648 <- needs nets 628 traces.traces_649_original <- needs nets 628 traces.traces_650 <- needs nets 629 traces.traces_650_original_aka_649_edited <- needs nets 629 Philippe modified the trace length compare code so that the filename of the log files that it writes has both the string from the configuration file that was used to run the compare and a timestamp in its filename. That is these log files are now good/complete for archiving the length difference aspect of the Hub's high-speed routing. Except for the one run to the Transmitter MiniPOD I think that all of the high-speed routes are now in final form. Status: with all fills out May need to backup to trace_649 comps 2906 rev 1285 nets 3777 rev 629 connections 8667 finished 7168 rev 650 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 2-Jan-2017 Topic(s): Sig_9 MGT Routing Did some cleanup of the 48.08 MHz Clocks to the backplane connectors on the top layer. Still need to round this but it now looks even. Finished the Signal_7 MGT routes from yesterday and almost finished them on Signal_9. All of the Backplane to MGT Fanout Inputs are now finished and look OK. Only a few MiniPOD Transmitter runs left to do at 3mm bends. Status: with all fills out Only Trace Rev change. comps 2906 rev 1285 nets 3777 rev 628 connections 8667 finished 7168 rev 645 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 1-Jan-2017 Topic(s): Sig_7 MGT Routing Finished all by 3 serpentines in the Signal_7 MGT routes from backplane to Fanout and from Fanout to ROD. Looks OK but need to double check Channels: 41, 49, 57 as they have a different topology than the other routes and Channel 61 as it is unique in escaping to the East. Status: all fills are out, at traces 641, other counts same ------------------------------------------------------------------------ DATE: 30-Dec-2016 Topic(s): Sig_8 MGT Routing Finished the Signal_8 MGT routing for both the Backplane into the MGT Fanout and the MGT Fanout to ROD. There are two layers of this left to go. It take a full long day to do a layer of this. All of Signal_8 looks clean and OK. A thing to check on again is the feed for MGT Fanout Channel #38 which runs the Other Hub's readout signal around to the back of the ROD's S2 connector. Where is best for this serpentines in this route ? Is there a better backside escape from the S2 MegArray ? Status: with all fills out comps 2906 rev 1285 nets 3777 rev 628 connections 8667 finished 7168 rev 637 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 29-Dec-2016 Topic(s): MGT Routing Finished the layer Signal_6 MGT routing for both the Backplane into the MGT Fanout and the MGT Fanout to ROD. Many tries at getting this arranged in the best way but it now looks OK. The general flow works best: get all the spacings right with just normal 45 deg runs, then round all the corners, last put in the serpentines. Now that the scheme is understood I hope that Signal_ 7,8,9 go a lot faster. Status: with all fills out comps 2906 rev 1285 nets 3777 rev 628 connections 8667 finished 7168 rev 631 unfinished 352 guides 1147 Note that traces 630 has more serpentines in for MegArray S1. I then backed up to traces 629, did a cleaner layout, and that made traces 631. The "630_original" is a dead end. 629 was renamed 630. ------------------------------------------------------------------------ DATE: 28-Dec-2016 Topic(s): MegArray Geom, All Pow Good, MGT Routing Started work to bring the MegArray Geom to the standard 0.25 mm Drill via for its MGT signals. I have not looked at this Geom in a long time. Questions about why some Gnd pins are setup the way that they are and if I should put a full matrix of Gnd links on the Sig_1 copper in this connector ? Finally tied up the All_Hub_power_Good signal to the FPGA. This is I hope the last Select I/O to get tied up. Worked the documentation (Sel I/O usage, Signal Types, 31 Drw, 31 Blk) so that all is up to date. Working on the MGT rounting from backplane into Fanout and Fanout to ROD. Late today I found a slightly cleaner breakout from the Fanout so now I have about one half of Sig_6 traces to re-do again. Status: with all fills out comps 2906 rev 1285 nets 3777 rev 628 connections 8667 finished 7168 rev 624 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 27-Dec-2016 Topic(s): MiniPOD Geom, MGT Routing Monday I reworked the Transmitter MiniPOD Geom so that the Fiber Data pins are now using the small 0.25 mm Drill and small 0.56 mm Via Pad Lands and so that the 4 unused Fiber have SMD Pad Only for their data pins. This is the start of the final push for all (MiniPOD, FPGA, MegArray, Diff_Pair_Via) MGT pins to use the same small 0.25 mm Drill vias. Only the Transmitter MiniPOD needed rework as the Receiver uses SMD Pads only for its Fiber Data Pins. Note that I dropped the old MiniPOD Geom Blind Vias aka Short vias from the design. This required also removing them from the TECH file. I saved a version of the TECH file with them in it for reference - tech_702_original. Today finished the MGT Fanout to Hub FPGA "new style" rework and spent a lot of time verifying that this is all OK. The smooth bends with equal radius (at large radius) look fine. Their Zo should be within one Ohm of targer. All trace lengths from MGT Fanout to Hub FPGA now look fine. Started the Backplane to MGT Fanout Input final trace cleanup and length matching. Status: Traces now at 620, Geoms now at 760, No other changes. ------------------------------------------------------------------------ DATE: 23-Dec-2016 Topic(s): All work on MGT routing Finished the little bit on MGT cleanup on Signal_10 and started the work on South side MGT connections to the FPGA on Signal_ 2, 3, 4, 5. This now looks OK in the "new style". All is basically in except for the last two bends coming into the FPGA. That is worked out and just needs to be put in. I'f going to move the 320.64 MHz PLL Gnd and CLK_3V3 vias South by 0.2 mm just to improve the clearance to the South most MGT runs, i.e. MGT Fanout Channels 6 and 8. By moving the 45 deg rus South by 0.4 mm (to get larger radius bends going into the BGA) the signal that is closest to the bypass caps to the SW is: MGT Fanout Channels 8. This buys a 1.3 mm radius bends into the BGA. Trace_615 is the first with all Sig_10 fully finished. Status: with all fills out comps 2905 rev 1282 nets 3777 rev 626 connections 8664 finished 7165 rev 618 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 22-Dec-2016 Topic(s): 2nd try to make MAC IO pinout Happy, MGT route rework Implemented the 2nd try to make the MAC IP pinout happy. This try is to not use pin BA32. Yuri reports that things now look OK. All of the rest of the day was spent working on the MGT traces on Signal_10. I think that is now all finished except for moving some trace pairs next to the backplane by 0.3 mm and maybe one more serpentine. Status: with all fills out comps 2905 rev 1282 nets 3777 rev 626 connections 8664 finished 7165 rev 614 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 21-Dec-2016 Topic(s): Meeting with all 6, MAC and MGT trace work, Staff Lunch Meeting with Wade, Pavel, Yuri, Brian, and Philippe. As I understand it Pawel says that all of the FEX receiver stuff, explicitly the: MGT pinout, GTH/GTY Aurora, SLR0/SLR1 Aurora is all OK, that all of the other Hub uses of MGT (e.g. Combined Data, Readout, MiniPOD, ROD Flow Control) look OK to Vivado and its wizards, and that he will start next the minimal/safe design. Yuri said that my trace rework from yesterday, i.e. putting the U21 GTX_Clk into an I/O Block by itself does not fix the problem. I said still aiming to release on Mon Jan 9th. In email with Yuri after the meeting we agreed that I would put the MAC FPGA pinout back the way that it was before yesterday and then move Phys_U21_RXD1_MODE1 from pin BA32 to pin AY32. From his email today, "So, the point is, as I see it, the pin BA32 should be left unused...". Worked on moving the Combined Data MGT traces on Signal_10 to the new high-speed routing "style" with its larger radius bends. I also have the design currently pulled apart to implement the new try at MAC FPGA pinout. Status: with all fills out and MAC FPGA pulled apart comps 2905 rev 1282 nets 3777 rev 625 connections 8664 finished 7163 rev 610 unfinished 354 guides 1147 ------------------------------------------------------------------------ DATE: 20-Dec-2016 Topic(s): Get the U21 Phys Chip GTX_Clk into private I/O Block, 3 page cleanup The GTX_Clk from Phys Chip U21 is now in an I/O Block by itself. This was done by moving the Phys_U21_TX_EN signal from pin BB34 to pin AY32. This was done by moving the trace for this signal from layer Sig_7 up to layer Sig_3. The routing looks OK. Worked on the 3 page list of cleanup, e.g. C2934/5 from 0603 to 0402, bad corners and width changes on Sig_7, LC Filtered DCDC Converter Capacitor SLIs, SLIs in the MegArrays, SLIs in R1405, R1410, R1991, 4x Via SLI at 38.9, 15.5, and more. Status: with all fills out comps 2905 rev 1282 nets 3777 rev 625 connections 8664 finished 7165 rev 608 unfinished 352 guides 1147 ------------------------------------------------------------------------ DATE: 19-Dec-2016 Topic(s): MSU In-House Release All work today was on the MSU In-House Only Release. No change in pcb status. ------------------------------------------------------------------------ DATE: 16-Dec-2016 Topic(s): Fills and Gerbers All day working on the Fills and Gerbers, i.e. working on the files that support the creation of the Fills and Gerbers. Currently using an Aperture Table that makes minimum size normal "wagon wheel" power apertures. That is OK for this test work and good because you can see the pins that connect to the Ground Planes but is not going to be the final method. Gerber generation now checks for missing apertures. From looking at the Gerbers I have two pages of things still to fix. Most of these points are simple and should not take too long. I'm leaving them in the "in house release" as I need to get this out soon. All Gerber and Drill files for the "in house only" release are now on the web. Currently with all Fills in there are: 3 un-finished traces, and 39 guides. Un-Finished: Bulk_1V8 NW corner U553-2 to R1991-2, BULK_3V3 by U21 L1905-1 to R1410-2, SLIs at: 38.9, 15.5 maybe multiple sins at this location; 99.1, 199.7; 133.6, 199.6; 232.6, 201.1; e.g. C75/C76 in each of the 20 Amp converters; 17 in each MegArray; trace_601 is the good per-fill file. Status: with all fills in, i.e. trace_605 comps 2905 rev 1277 nets 3777 rev 624 connections 8165 finished 8123 rev 605 unfinished 3 guides 69 ------------------------------------------------------------------------ DATE: 15-Dec-2016 Topic(s): Worked on the In House Release Worked on the Fill to X design rules for: the 4 types of conflicts, 3 types of Nets, and 4 layers of fill generation, aka tune up 48 parameters. Worked on the Aperture Table. We are locked at version 25 and any changes or additions will need to be modifications to this table, i.e. not starting over again. Main issue is setting up the Power Apatures. I'm fairly certain that this only involves the 10 Ground planes of 3 different kinks. I also want to look a finding a way just to flood some / most of these ground plane connections. The intent is to make both the Aperture Table and Fill to X rules good enough for production release or close to it. Repaired 3 more of the problems found yesterday when all of the fills were in: ECLK_3V3 not filled, BULK_1V8 route to the jumper area East of FPGA, GNDs to the 2nd 40.08 MHz Fanout. Status: with all fills out trace_601 is the good per-fill = 599 comps 2905 rev 1277 nets 3777 rev 624 connections 8660 finished 7121 rev 601 unfinished 353 guides 1186 ------------------------------------------------------------------------ DATE: 14-Dec-2016 Topic(s): Meeting with everyone, Fills work, Release Work Meeting this morning with: Wade. Yuri, Pawel, Brian, Plhiliipe. Discussion of the MAC IP physical pinout issue. Clear agreement that if I put the Phys chip GTx_Clk signals in an I/O Block by themselves then that will get us around the IP's pinout restriction. The order to check things remains: Bank 68, all up MGT, all up "minimal safe" design. The other "IP" in the system will be the IPBus setup on top of the MACs, and the FELIX optical TCC via serial MGT channel. Let folks know that January 9th is the release target. Worked on the Fill generation scripts. Almost all needed their "unique ID point" changed. Still working on the Fill to X design rules. Have tried 4 sets of rules in this first pass. The next pass will start with something like: Fill Via Trace Pin ---- ---- ----- ---- 0.50 0.20 0.35 0.15 HS \ 0.50 0.20 0.30 0.14 Norm | Hi Res 0.50 0.35 0.35 0.35 HS \ 0.50 0.21 0.30 0.25 Norm | Med Res With all 53 fills in there are still 17 unfinished traces and 100 guides. I have found and fixed most of the problems. The whole ECLK_3V3 fill was missing from the script. The mrging of the Hi Res and Med Res fills is not working and that is leaving one SLI per combination, i.e. most by the FPGA. A bunch of the High-Speed Diff Pairs were missing their Net_Type Property. I have dumped the trace files with the fills and saved traces.traces_597_1st_pre_fill and _598 is the current good version. Status: with all fills out comps 2905 rev 1275 nets 3777 rev 624 connections 8657 finished 7114 rev 598 unfinished 353 guides 1190 ------------------------------------------------------------------------ DATE: 13-Dec-2016 Topic(s): Plugs and Fills Gave up with the one sided Via Plug setup in the MGT Fanout area. One sided plugs were working fine for the normal center thermal ground pad usage (and continue to be used for that) but they were not OK in the vias that were very close to bypass capacitor and QFN-16 pads in the Fanout area. These vias and 2 of the 4 QFN_16_On_Semi center pad vias were moved to being plugged from both sides aka IPC type IIIa plugs. This looks OK now but I still do not understand how they manufacture them or how one does assembly with them without a trapped air / water problem. Started the fill generation process. MANY shaps have moved enough that I needed to find new unique points on them. That is mostly done. The fill to fill/via/trace/pin design rules are all working OK but now the issue is picking final values for them. A solution clearly exists but need to find the best one. The fill to pin relief for the Diff_Pair_HS type nets is working but needs adjustment. Saving traces.traces_592 as the golden pre-fill version. <--- Status: with Sig_6 fills in comps 2905 rev 1275 nets 3777 rev 622 connections 8577 finished 7141 rev 594 unfinished 306 guides 1130 5 Shapes and 5 Fills are in. ------------------------------------------------------------------------ DATE: 12-Dec-2016 Topic(s): Weekend work on Geoms, More clean up for parts/place and trace delay matching Over the weekend made the final (I Hope) adjustments to the following Geometries to get the backside center pin metal correctly placed and to get the via plugs all working correctly. Recall that Sheet_Dielectric_1 is being used for the backside metal of components that are placed on the Top side of the card. This is metal on side 2. Sheet_Dielectric_2 is being used for the backside metal of components that are placed on the Bottom side of the card. This is metal on side 1. PrePreg_5 marks the vias that are plugged from the Top PrePreg_6 marks the vias that are plugged from the Bottom. The following Geometries were worked on: switch_328_pin_geom, lt1764_dd_pak_dcdc9.txt, both MiniPOD_Geoms, phys_48_pin_geom, qfn_16_on_semi_bot, qfn_16_on_semi_top, qfn_16_ti, qfn_32, qfn_48, via_0mm60_bot_plug, via_0mm60_top_plug The new comp types (since Sept release) are now worked into the XY placement scripts and that is working OK. Finally realized that we do NOT want to concatinate the Back-Drill files from Most and ZONE_2 duh because they will require different drill diameters. Today worked on parts and placement issues, e.g. just one instance of an other wize common component type on one of the sides of the card. Adjusted other component type valuse and various documentation drawings to match. Reworked the MiniPOD Receiver geom so that I sould un-flip on pair (Fiber #6) and thus fix up a large timing skew (before trying to add length matching serpentines. This now looks OK so I adjusted the required drawing and documentation table. Same thing will be needed in MiniPOD Transmitter on 4 channels. Status: comps 2905 rev 1275 nets 3777 rev 622 connections 8660 finished 7066 rev 590 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 9-Dec-2016 Topic(s): Start work on the MSU internal release, FPGA pin out Many notes today from Pawel and Yuri about understanding the MAC IP FPGA pinout issue and suggestions about pin swaps. Finished some more cleanup North of the FPGA and then at about noon started trying to make the internal MSU only release of the Hub design for checking. Philippe rolled through the Back Drill generation process with no trouble. We have had a quick look at that data in the Mentor display. I got only as far as the Bill of Materials. That took a while because of the recent new components that take special handling (e.g. the two linear regulators now have different geometries and the new not in BOM clock oscillator). That stuff is now all in and the script is working OK. Still the issue of final determination of where to install the specialized values of resistors and capacitors (e.g. in the DCDC Converters). We have started the document with serious instructions for generating the Manufacturing Data. They are in the file: hub_release_instructions.txt Status: comps 2905 rev 1272 nets 3777 rev 620 connections 8658 finished 7064 rev 588 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 8-Dec-2016 Topic(s): MGT Trace Cleanup Basically all work was on the MGT traces on the North side of the FPGA. Moved the bulk of them 0.2 mm South to even up the spacing and increased the bend radius where space was available. This is enough trace cleanup for now. Friday try to make an in house release and start checking. Status: comps 2905 rev 1266 nets 3777 rev 620 connections 8659 finished 7065 rev 587 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 7-Dec-2016 Topic(s): Fix documentation, Meeting with Wade, Trace Routing Cleanup Fix the errors that Philippe spotted in the documentation comments in the mgt_all_other net list file a week or so ago when he made the GTH_FO_Ch to MGT_FO_Ch edit. Doing that pointed me to an error in drawing #22 of the GTY channels. Meeting with Wade, Brian, and Philippe down here after their video meeting. Main issue is the MAC IP restrictions on physical pinout. We are requesting an implementation with Both MACs and all other IO in Bank #68. We need to see all of the raouting issues with the MAC IP not just the routing problems with one MAC in isolation. When that is finished we need a final signoff on the layout of all MGT related connections. At the 3rd level of priority is needing to know that all physical pinout for the minimal safe design is OK. Also mentioned: running into the holidays, first IBERT in the optical connections (that being most likely to work), the mechanical changes (LEMO, ATCA Switch, Elma), and mentioned the mechanical parts to design. All routing work is on cleanup under the FPGA and cleanout of the high-speed traces. Status: comps 2905 rev 1266 nets 3777 rev 620 connections 8659 finished 7065 rev 580 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 6-Dec-2016 Topic(s): Front Panel Support Mechanical Holes, Front Panel Handel Mechanical Hole, Trace Clean Up The mechanical holes are now in the PCB Geometry for Front Panel Mounting Brackets. Two holes (4-40) near the top and two near the bottom. They look OK and are in about the right place and not too tight. Basically all day trying to understand why I could not get the metal setup the way that I want around the Bottom Handle hole in the PCB. Finally found a design constraint from 9-June-2015 that was restricting access to layers for this hole - I *think* in an early attempt to enforce separation of Ground and Shelf Ground. Now this is OK. In the debugging process the ESD Strip Geom was split into two pieces: front and mid-rear. A little time for trace clean up on Signal 9 - mostly within the U1 foot print. 36 revs of geom file to find the problem. Status: comps 2905 rev 1266 nets 3777 rev 619 connections 8659 finished 7065 rev 576 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 5-Dec-2016 Topic(s): Backside Cu and Plugs, Change Handle Switch and Lemo, Front Panel Mechanical Weekend work on the geometries that need either Backside Copper or Via Plugs. This is getting closer to real. Working on making the change to using Elma Front Panels and Handles and ATCA Switch. To facilitate this and to get space for front panel Brackets I have changed the LEMO connector and the ATCA Switch. LEMO also had to change because of the front panel is on a different ground. Now working on adding the mechanical holes to the pcb geometry for the front panel brackets. Looks OK for 2x 4-40 holes top and bottom. Anticipated Elma Part Numbers: Front-Panel 66-536-28 Top Handle 81-300-00 Bottom Handle 81-301-00 Switch 81-088-1 Switch Connector Part Number: Molex 53047-0310 DK# WM1732 Status: comps 2904 rev 1265 nets 3777 rev 617 connections 8654 finished 7060 rev 575e unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 2-Dec-2016 Topic(s): Documentation then PCB Fixed problems in (aka updated) 4 more documents and then finally got back to layout work after a full week of this other stuff. After todays work the current collection of pcb topics (pre internal release) is down: redoing the Lemo connector, redoing the ATCA Switch. Neither are OK the way that they are. Then I can add the Mechanical holes. Status: comps 2900 rev 1256 nets 3777 rev 612 connections 8653 finished 7059 rev 574 unfinished 353 guides 1241 ------------------------------------------------------------------------ DATE: 1-Dec-2016 Topic(s): All work on Documentation All work today was on documentation to make it current with the actual pcb design. Released the first draft of the "signal types" document. I think that all of my documents for the firmware folks are now current. ------------------------------------------------------------------------ DATE: 30-Nov-2016 Topic(s): Working on Docs, Meeting with Philippe and Wade Meeting with Wade and Philippe. So far the FTM looks like it would be a good data source for production Hub Module testing. It also does not look too expensive and perhaps could be built more or less turn-key. Having a 12 data source crate would also make a good platform for ROD and Hub FW development. Talked about were we are in the Hub layout work and that we soon need all hands on deck checking that it will provide the necessary Hub functions and is a correct implementation of those functions. I think that all of my drawings and documents now match what is actually in the design and are on the web. I'm still working on the signal types document but it will be finished either tonight or else in the morning. Then back to pcb after a full week away from it. ------------------------------------------------------------------------ DATE: 29-Nov-2016 Topic(s): Drawing, Text Docs, Netlists Except for the "select i/o usage" document and the explaination of "signal types" document I believe that all of the drawings and documentation have been brought up to date with the actual Hub pcb design. I hope to finish this tomorrow. Worked on the net list both pulling out "commented out" stuff that was left over from the strugle to route the card and also fixing the "polarity flips done by reference designator" that left the .ucf and .xdc files showing stuff that would have been very hard for other to understand. Status: comps 2899 rev 1255 nets 3778 rev 609 connections 8644 finished 7053 rev 573 unfinished 350 guides 1241 ------------------------------------------------------------------------ DATE: 28-Nov-2016 Topic(s): Drawing, Text Docs, Netlists Continue working to bring all Hub drawings and documents up to date with the issued .ucf and .xdc files. Answer notes from Yuri and Pawel about connections to the Hub's FPGA. Start work on fixing parts of the Netlist that "do the right thing" in the Hub design but cause lines in the .ucf or .xdc files to be wrong. This has to do with "flipping" some MGT signals by means of AC Coupling Capacitor Reference Designator manipulations. Still have not started the overall description of the various "types" of signals connected to the FPGA. I'm building up a rather long list of known changes that are needed in the actual pcb layout: - Add the Hub's SMB_Alert_B FPGA connection. - Straighten the traces around the NW Heat-Sink screw. - Add multi ties to the large Tants South of the SW Chips. - Change the Lemo connection from pcb mount to panel mount. - Change the ATCA FP Switch to discrete wire connection. ------------------------------------------------------------------------ DATE: 25-Nov-2016 Topic(s): GTH_FO to MGT_FO, Drawings and Doc Moved the Mentor Design to actually using Philippe's edited netlist files that changed GTH_FO_CH_bla to MGT_FO_CH_bla. The counts look OK and no error messages. The overall netlist file is 371 bytes longer. The rest of the work today was on updating the required drawings and writing the documentation to describe the pins in the .ucf file so that everything fits together. Sent a note to George to answer his note requesting an update on Hub design status. Status: comps 2899 rev 1255 nets 3778 rev 606 connections 8644 finished 7053 rev 573 unfinished 350 guides 1241 ------------------------------------------------------------------------ DATE: 23-Nov-2016 Topic(s): Power Supply DCDC 2, 3, 7 Loc UCF files, GTH_FO to MGT_FO The DCDC Converters 2, 3, 7, i.e. the ones with an LC output filter for the MGT and Fanout loads, now all have selection jumpers to pick their servo feedback from either before or after the "L" separately for their Differantial Amp DC feedback path and for their RC feedback path. They also now have an 0805 capacitor for direct feedback from before the "L" to their "Trim" input pin. Also double riveted the connection to their "Trim" input pin. Finished the list of net names that will not go in the .ucf file. The two biggest issues in this were: same net name connection to both the pins for the slave I2C port to the System Monitor and for the master I2C port (e.g. so that we can manage the DCDC Converters). Solution dump the salve I2C System Monitor port from the .ucf because it is at fixed pin locations anyway. Issue that the FEX data input nets to the FPGA still have the old "GTH_FO_CH_bla" net names. Solution is that Philippe edits all 8 files that still had the old "GTH_FO_CH_bla" net names - they are now called "MGT_FO_CH_bla" Here is a table listing all files from the Net_list area where "gth" was detected and the action or lack of action |-----------------------------------------------+---------------------------------------+-----------+---------| | Name of file found in Work/Net_Lists | | Name | Content | | with "gth" appearing within content | Action | Changed | Changed | |-----------------------------------------------+---------------------------------------+-----------+---------| | aa_list_of_files_with_fpga_connection.txt | updated 2 file names gth->mgt | | Yes | | aaa_hub_0_build_all_nets.sh | updated comments and 2 gth file names | | Yes | | combined_data_distribution_nets | gth in comments, all legitimate | | | | dcdc_7_converter_nets | comment could be changed, but benign | | | | gth_fanout_channel_nets | output of script -> replaced&renamed | by script | N/A | | hub_all_other_gth_nets | updated/corrected header description | Yes | Yes | | | updated comments and GTH_FO_* | | | | | Note: comments for This_Hubs_RO_* | | | | | need more help; don't yet match usage | | | | migt_f.py | "gth" occurence in word "length" | | | | netlistsort.py | "gth" occurence in word "length" | | | | ultra_dci_vref_mgt_calib_resistors_nets | gth in comments, all legitimate | | | | ultra_no_connect_pins_nets | gth in comments, all legitimate | | | | xcvu125_flvc2104_pkgpinout_formatted.txt | all legitimate | | | | xcvu125_flvc2104_pkgpinout_gth_gty.txt | all legitimate | | | | xcvu125_flvc2104_pkgpinout_raw_unix.txt | all legitimate | | | |-----------------------------------------------+---------------------------------------+-----------+---------| | Build_GTH_Readout_Nets/ | | | | | | | | | | aa_build_gth_fanout_nets.sh | updated comments and output name | | Yes | | gth_fanout_dap_pad_gnds | updated comments | | Yes | | gth_fanout_equ_enb_groups | updated comments and GTH_FO_* | | Yes | | gth_fanout_nets_addition.txt | updated comments and GTH_FO_* | | Yes | | gth_fanout_nets_config.txt | updated comments | | Yes | | gth_fanout_nets_template.txt | updated comments and GTH_FO_* | | Yes | | gth_fanout_to_hub_fpga_nets | updated comments and GTH_FO_* | | Yes | | gth_fanout_to_hub_fpga_nets_NO_polarity_flips | updated comments and GTH_FO_* | | Yes | | gth_fanout_to_hub_fpga_nets_straight_order | updated comments and GTH_FO_* | | Yes | | gth_fanout_to_meg_arry_conn_nets | updated comments and GTH_FO_* | | Yes | | gth_fanout_zone_2_input_nets | updated comments and GTH_FO_* | | Yes | | migt_f.py | "gth" occurence in word "length" | | | |-----------------------------------------------+---------------------------------------+-----------+---------| | Not_Currently_In_the_Design/ | | | | | | | | | | virtex_7_fpga_bypass_cap_nets | ignored | | | | virtex_7_fpga_power_ground_nets | ignored | | | | xc7vx550t_ffg1927_pkg_pinout_raw | ignored | | | | xc7vx550t_pinout_gth_by_function_raw | ignored | | | | xc7vx550t_pinout_gth_by_number_raw | ignored | | | |-----------------------------------------------+---------------------------------------+-----------+---------| Status: comps 2899 rev 1255 nets 3778 rev 605 connections 8644 finished 7053 rev 572 unfinished 350 guides 1241 ------------------------------------------------------------------------ DATE: 22-Nov-2016 Topic(s): Back-Drill, Loc UCF, Power Supply Drawings Worked on the Mentor Layers to display the Back-Drills for the Zone 2 Connector Region. Verified the use of the PREPREG layers in the Hub design. Working on adding jumpers to allow control of the feedback source points on the 3 DCDC Converters that use LC output filters i.e. the MGT supplies. Email with Yuri about the .ucf file for the Hub and talk with Philippe about how his ListCompPinNets will pull this out, i.e. what to trim off of the raw net list. As added to today for the Zone_2 Connector back-drills, review the special use of layers in the Hub design: Ground Plane Cuts in Top layers PrePreg_1 Ground Plane Cuts in Bot layres PrePreg_2 Ground Plane Cuts in All layers PrePreg_3 Vias Plugged from the Top PrePreg_5 Vias Plugged from the Bottom PrePreg_6 Backside metal on Bot side e.g. QFN center pad Sheet_Dielectric_1 Backside metal on Top side e.g. QFN center pad Sheet_Dielectric_2 Back-Drills non-Zone_2 from Top Shallowest Sheet_Dielectric_4 Back-Drills non-Zone_2 from Top NT Shallowest Sheet_Dielectric_5 Back-Drills non-Zone_2 from Top NT Deepest Sheet_Dielectric_6 Back-Drills non-Zone_2 from Top Deepest Sheet_Dielectric_7 Back-Drills non-Zone_2 from Bot Shallowest Sheet_Dielectric_8 Back-Drills non-Zone_2 from Bot NT Shallowest Sheet_Dielectric_9 Back-Drills non-Zone_2 from Bot NT Deepest Sheet_Dielectric_10 Back-Drills non-Zone_2 from Bot Deepest Sheet_Dielectric_11 Mark All non-Zone_2 Back-Drills Sheet_Dielectric_12 Back-Drills Only-Zone_2 from Bot Shallowest PrePreg_9 Back-Drills Only-Zone_2 from Bot Mid Depth PrePreg_10 Back-Drills Only-Zone_2 from Bot Deepest PrePreg_11 Mark All Only-Zone_2 Back-Drills PrePreg_12 No status count changes today. ------------------------------------------------------------------------ DATE: 21-Nov-2016 Topic(s): Shapes, Drawings, Routing Weekend work on the AVTT shape to reduce overlap with the AVCC fill and on power supply documentation drawings. Today work on the Bulk_1V8 connection to Translators, on drawings, and getting the 35 Ground connections to DCDC9 and fill in J2. The design now has 16 pins with no associated net. They are all in the J3 Voltage Monitor connector and are OK for now. Status: comps 2884 rev 1247 nets 3772 rev 602 connections 8611 finished 7020 rev 569 unfinished 350 guides 1241 ------------------------------------------------------------------------ DATE: 18-Nov-2016 Topic(s): Clean Routing and Shapes Power Supply FB Options Jumpers Worked on clean up of the shapes and some of the routing. All shapes are now looking OK and are mitered. It needs one more check but I think that it is ready to try generating the fills and gerbers. Shapes have changed enough that I will need to find new unique points on them for the Fill Generation scripts. Cleaned up various routing and moved the Bulk_1V8, Bulk_3V3, and MGT_AVAUX monitor points closer to their loads. There are still some Tants with only single connections at each end and I would like to find a place for one more 3V3 Tant. Working on the jumper options layout for the 3 converters that use and external LC filter. Status: comps 2884 rev 1247 nets 3772 rev 601 connections 8609 finished 7016 rev 568 unfinished 351 guides 1242 ------------------------------------------------------------------------ DATE: 17-Nov-2016 Topic(s): Cleaning Routing and Shapes Worked on routing clean up, e.g. getting the Voltage Monitor points as close to the loads as practical and clean up of the Equalizer Enables vs Fills on same layer, and Chassis Gnds. Now with mitering working made a push on final fill shapes. Moved a lot of things around by 1 mm or less. Pushing the Core fill as tall in N/S direction as possible as the MGT feeds still look OK coming from the perimeter. With mitering on can see many more sins in the shapes as they were. Status: comps 2884 rev 1245 nets 3772 rev 601 connections 8609 finished 7016 rev 567 unfinished 351 guides 1242 ------------------------------------------------------------------------ DATE: 16-Nov-2016 Topic(s): Back-Drill and Mitering Work Tuesday all day was working on dividing up the various layer transitions in the design into what back-drills we will actually ask for in the bar pcb. This is described in detail hub_back_drill_nets_and_xy_regions.txt fill on the web. The intent remains to only back-drill the multi Gb/sec stuff and leave the Ethernet and differential clocks alone. Wednesday work with Brian on testing the miter.py. This is now running and I have been editing the shapes files with the changes that look necessary and the NO_MITERs that are required. In checking the back-drill stuff Philippe found a significant mistake that I made in selecting the nets for back-drilling. That's now fixed and the back-drill description file on the web is up to date. We need a final cross-check on the layer transitions to back-drill depth mapping and what to do under the Zone 2 connectors. All looks rational except for 1 of the Hub Readout pairs to the Other Hub. No trace editing in 2 days - so no status change except that Mentor Graphics was purchased by Siemens on Monday. Working on drawings of the DCDC Converter feedback setups. ------------------------------------------------------------------------ DATE: 14-Nov-2016 Topic(s): Weekend work on Drawings, Rework PS Voltage Monitor Conn J3, Caps in Spare Osc, Brian's miter.py Over the weekend work on bringing some of the drawings up to date and made a drawing 53 of the Access Signals, Spare Oscillator, and Spare Gate List. Monday work on redoing the J3 Voltage Monitor connector to put the series resistors at the source of the monitored voltage rather than all of them up near the J3 connector. Addes some space between the SysMon Ref monitor point and its neighbor monitor points just to help isolate and protect the SysMon Ref voltage. Added series 0603 patterns to the Spare Oscillator just in case we want to AC couple it (like the other clocks) or back terminate it. Brian has the miter.py ready for testing. I will do that tomorrow as it would be good to try a practice run of building all of the design files so that we have an internal "almost final version" to start looking at for problems. Status: comps 2884 rev 1243 nets 3772 rev 601 connections 8607 finished 7014 rev 566 unfinished 351 guides 1242 ------------------------------------------------------------------------ DATE: 11-Nov-2016 Topic(s): Finished routing Spare Osc & Access Outputs, Clean up, Voltage Monitor, Meeting with Wade and Philippe Finished routing the Spare Crystal Oscillator and Access Outputs Buffer. Major clean up of traces in the vertical pinch especially at the top of the RJ45 notch. Worked on the J3 Voltage Monitor connections and added an 11th monitor point for the ISO_12V. Meeting with Wade and Philippe. Wade is pushing on L1Calo for how to have 12 data sources. A goal is to get this sooner rather than when it is too late to do maximum good. eFEX would be best but could the FTM module be used ? Meeting about that next week. Hope to get Ed on board as I assume that he would be interested in an all channels test - after all he make a fanout just to do that. Would be a nice setup to say that this does or does not work. Then would be used for production testing of ROD+Hub. Could be a turn-key build here in the US. Status: comps 2882 rev 1236 nets 3770 rev 599 connections 8596 finished 6987 rev 562 unfinished 353 guides 1256 ------------------------------------------------------------------------ DATE: 10-Nov-2016 Topic(s): Spare Osc. & Access Outputs Got in all of the components and nets for a Spare Crystal Oscillator with differential output connected to a Global Clock input and Buffered Access Output to the Front-Panel J2 Connector. These are all tied up to pins in Bank 67 and are layed out to be routable. Other traces have been already been moved around to make these new nets routable. Additional clean up in the JTAG and Power Control traces between the MegArrays and on Signal_9 in the FEX MGT Fanout. Status: comps 2880 rev 1234 nets 3769 rev 598 connections 8590 finished 6978 rev 557 unfinished 353 guides 1259 ------------------------------------------------------------------------ DATE: 9-Nov-2016 Topic(s): 3V3 Tant, TDI Buf, Access Signal Output, Extra Osc with diff pair Added one more 330 uFd Tant to the BULK_3V3 because it had fewer than some of the other rails and none close to a significant part of the loads and because BULK_3V3 uses 330 uFd vs 470 uFd for the other rails. Added the AND gate Buffer to the JTAG TDI signal going into the ROD. This is U557 with series terminator R593. This now all looks clean and the JTAG drawing #33 is up to date. Still working on buffereing of the front panel access signals and the spare oscillator with a differential signal pair. An issue is getting the FPGA Signals. A point of this is to make FPGA signals available in an emergency. Philippe's Back-Drill is about ready for prime time. Going through checks now. Status: comps 2873 rev 1232 nets 3763 rev 592 connections 8569 finished 6964 rev 556 unfinished 350 guides 1255 ------------------------------------------------------------------------ DATE: 8-Nov-2016 Topic(s): Finished all trace length trimming of high-speed nets that run all or in part on Sig_10, Connected the 74 Under FPGA bypass capacitors Finished the trace length trimming of all nets that run on Signal_10. Added 4 more Under FPGA bypass capacitors and connected all of them. So far this all looks OK. Still need to divide up the Under FPGA caps into not all 100 nFd values. All are 0402 size. "Final" Count of Under FPGA Bypass Caps: FPGA_CORE 12 BULK_1V8 14 MGT_AVCC 18 MGT_AVTT 18 MGT_AVAUX 10 BULK_3V3 2 Status: comps 2869 rev 1226 nets 3761 rev 588 connections 8556 finished 6954 rev 553 unfinished 347 guides 1255 ------------------------------------------------------------------------ DATE: 7-Nov-2016 Topic(s): Weekend work on Under FPGA Caps Over the weekend worked on getting the Under FPGA bypass caps into the design. The current counts are: FPGA_CORE 12 These are all 0402 size and can be BULK_1V8 14 100 nFd, 47 nFd, or 10 nFd as those MGT_AVCC 16 values are already in the design. MGT_AVTT 16 Most cases have good clean short MGT_AVAUX 10 connections to the vias with about BULK_3V3 2 1/4 going to double vias. Clearances to adjacent vias are OK. Worked on replay to Ed's nice note about operation without the ROD powered up. I think that I need to add a buffer to the JTAG circuit. That's OK as the part is in the design. Status: comps 2865 rev 1224 nets 3761 rev 587 connections 8449 finished 6676 rev 548 unfinished 347 guides 1426 ------------------------------------------------------------------------ DATE: 4-Nov-2016 Topic(s): Doing the Trace Length Trimming of all high-speed traces on Sig_10 Working on the Combined Data trace trimming and doing it as separate trims of the FPGA to Coupling Cap traces and then separately trimming Coupling Cap to Load traces. Need to keep in mind which signals can be Flipped, e.g. Combined Data, vs which can not be flipped. Status: comps 2795 rev 1221 nets 3761 rev 584 connections 8309 finished 6676 rev 548 unfinished 347 guides 1286 ------------------------------------------------------------------------ DATE: 3-Nov-2016 Topic(s): Final Routing of Combined Data I gave up on the idea of final length trimming of the 74 FEX Data Input pairs and instead will do the 12 Combined Data pairs first (along with their similar routes e.g. Hub Readout and Combined Data to This ROD). The point is to verify that things look OK with this smaller number of traces first and then finish off the large number of FEX Input traces. So today was final adjustment of the Combined Data (and similar) traces and added 24 segment smoothing to them and trying to understand the best physical and electrical place to put the length match serpentines. Rework 3 of the MGT Fanout distributed bypass capacitors and now wish that I had more of them. Recall the difficult path from the FAN_1V8 supply to the Fanout chip array. Status: comps 2795 rev 1219 nets 3761 rev 582 connections 8309 finished 6676 rev 544 unfinished 347 guides 1286 ------------------------------------------------------------------------ DATE: 2-Nov-2016 Topic(s): Finish Fanout input/output rework Connect Fanout distributed bypass caps, Work on Fanout and MGT fill shapes, Philippe makes runs of finding back-drill locations and these go into the design Rework of the Fanout in/out traces is finished and now needs to be checked and then work on trace length matching. Final placement of the FAN_1V8 distributed bypass capacitors and connect them. This required yet another rework of some fills and still more of this to do. Philippe passed along the output of the initial part of the back-drill generation program. This included the file to allow display of the back-drills in the Mentor design. So far this looks good. You can see all of them or any compination of the various subsets. Status: comps 2795 rev 1217 nets 3761 rev 582 connections 8295 finished 6664 rev 540 unfinished 343 guides 1288 ------------------------------------------------------------------------ DATE: 1-Nov-2016 Topic(s): All work on final MGT FO routing All day on rework of the FEX Data MGT Fanout traces from the backplane to the Fanout Input and from the Fanout Output up to the ROD. I found a slightly better set of rules to route these traces (slightly greater separation between adjacent pairs within the Fanout itself at the cost on one more bend in about every 4th pair) so I'm working to implement this. After this it is length equalization of these 148 pairs. That sould be "easy" as no polarity swapping is allowed by my betters. Status: comps 2793 rev 1215 nets 3761 rev 581 connections 8277 finished 6645 rev 537 unfinished 329 guides 1303 ------------------------------------------------------------------------ DATE: 31-Oct-2016 Topic(s): Weekend work on LT1764 Geoms and fills near the FPGA, Review Special Layer usage, unstacking MGT traces Moved the generic LT1764 Geom into one specific for DCDC4, i.e. large Thermal Pad with zero Thermal Vias and one specific for DCDC9, i.e. small Thermal Pad with 35 Thermal Vias. Now that the close in FPGA bypass caps are in - worked on changes to the fill shapes to get them all connected. Among other things this means notching the CLK_3V3 fill to get a tab for a AVCC Tant. Review the special use of layers in the Hub design: Ground Plane Cuts in Top layers PrePreg_1 Ground Plane Cuts in Bot layres PrePreg_2 Ground Plane Cuts in All layers PrePreg_3 Vias Plugged from the Top PrePreg_5 Vias Plugged from the Bottom PrePreg_6 Backside metal on Bot side e.g. QFN center pad Sheet_Dielectric_1 Backside metal on Top side e.g. QFN center pad Sheet_Dielectric_2 Mark All Back-Drilled vias Sheet_Dielectric_4 Back-Drills from Top Shallowest Sheet_Dielectric_5 Back-Drills from Top NT Shallowest Sheet_Dielectric_6 Back-Drills from Top NT Deepest Sheet_Dielectric_7 Back-Drills from Top Deepest Sheet_Dielectric_8 Back-Drills from Bot Shallowest Sheet_Dielectric_9 Back-Drills from Bot NT Shallowest Sheet_Dielectric_10 Back-Drills from Bot NT Deepest Sheet_Dielectric_11 Back-Drills from Bot Deepest Sheet_Dielectric_12 Review the list of Geometries that require Plugged Vias and other special features, e.g. backside metal: qfn_16_top qfn_16_bot qfn_16_ti qfn_32 qfn_48 phys_48_pin Switch geom dir lt1764_dcdc9 Via from top Via from Bot Monday: start the work to optimize the spacing of the MGT traces that run from the backplane into the FEX MGT Fanout and from the Fanout up to the ROD. Moved the 6 Durand files into the design. Status: comps 2793 rev 1215 nets 3761 rev 581 connections 8277 finished 6645 rev 532 unfinished 329 guides 1303 ------------------------------------------------------------------------ DATE: 28-Oct-2016 Topic(s): Meeting with Wade, North side and SysMon Bypass, MGT with ROD Meeting with Wade and Philippe. Discuss the design status, pcb fabrication, testing options (e.g. many FTMs with only one FPGA and need for 14 slot ATCA) and problem recovery options (e.g. simple DC bias card). Finished the North side close in bypass for AVCC, AVTT, and AVAUX. Was able to fit in one more AVCC and one more AVTT cap. Added some "close in" 0402 caps to the SysMon 1V8 and Ref traces. Reworked the Readout Combined_Data MGT link and the two Hub Readout links with its ROD. Moved these 6 coupling capacitors to locations adjacent to the rest of the Combined_Data coupling caps and not over any Sig_6 ... Sig_10 traces. I believe that all 340 of the 0201 MGT coupling caps are now in safe locations. Status: comps 2793 rev 1214 nets 3761 rev 580 connections 8271 finished 6633 rev 526 unfinished 329 guides 1309 ------------------------------------------------------------------------ DATE: 27-Oct-2016 Topic(s): Write nets & xy regions note for back-drills, MGT RCal Resistors, North side close in bypass caps Status: comps 2789 rev 1205 nets 3761 rev 578 connections 8250 finished 6588 rev 522 unfinished 313 guides 1349 ------------------------------------------------------------------------ DATE: 26-Oct-2016 Topic(s): Finish South Side Caps Move Combined Data Caps Finished the South Side close in FPGA bypass caps for the AVCC, AVTT, and AVAUX rails. Had room to add one more cap to both AVCC and AVTT. Need to verify that I'm plating the FPGA Heat Sink mounting screw holes. Moved the Combined Data and Hub Readout Data AC coupling caps to their final locations. The issue here is that these 0201 caps have a ground plane cut out and thus they must not be over any traces on Signal 6 through 10. Status: comps 2789 rev 1201 nets 3761 rev 578 connections 8251 finished 6587 rev 520 unfinished 315 guides 1349 ------------------------------------------------------------------------ DATE: 25-Oct-2016 Topic(s): Bare pcb meeting with TTM and Debron, 2nd note about Back-Drills, Close in FPGA Bypass Cap Work 3 way meeting this morning about Hub pcb. Small vias, plugs, and back-drills are now understood. Notes on the Hub_PCB web site. For now everything is understood. Another meeting is planned once the "final" design data is released. The decision is to back-drill the Hub is now final. Send 2nd note with core dump of what I understand about this for Hub. I need to move all of the high-speed vias, except for the Zone 2 connector pins to a common size with 0.25 mm drill. The FPGA_CORE, BULK_1V8, and BULK_3V3 close in FPGA bypass capacitors are all in and look OK. Two more FPGA_CORE and one move BULK_3V3 cap was added. Some rework of the power fills is going to be required along the west FPGA edge is required. Now working on AVCC, AVTT, AVAUX on the South side of the FPGA. Status: comps 2787 rev 1191 nets 3761 rev 577 connections 8236 finished 6555 rev 516 unfinished 293 guides 1388 ------------------------------------------------------------------------ DATE: 24-Oct-2016 Topic(s): Placement of close in FPGA bypass capacitors Over the weekend and today worked on placement of the close in FPGA bypass capacitors for the FPGA_CORE BULK_1V8 and BULK_3V3 rails. Wrote detailed note to the bare board house. Phone meeting with them. Used Philippe's reorder_traces.py tool to check a 400 byte traces file discrepancy (but all counts OK) during the routing work today. reorder_traces.py is working fine on Hub. Status: comps 2784 rev 1187 nets 3761 rev 576 connections 8222 finished 6543 rev 515 unfinished 291 guides 1388 ------------------------------------------------------------------------ DATE: 21-Oct-2016 Topic(s): New Mentor Licenses and working on final placement of the close in FPGA bypass caps Status: comps 2779 rev 1176 nets 3761 rev 575 connections 8193 finished 6469 rev 512 unfinished 250 guides 1474 ------------------------------------------------------------------------ DATE: 19-Oct-2016 Topic(s): Finish the High Current Traces, Mitering the Fills, Geom Work Finished the High Current traces. The only thing that could still be added to the High Current traces is more layers for the output of the Iso_12V module. Work on the ATCA power module geometries to get better pin pad stacks for their high current pins and worked to fix the ATCA ESD component geometry. Talked with Brian about python to miter the corners of the Fills. He thinks that it sould not be too hard to write code for this. Status: comps 2779 rev 1171 nets 3761 rev 573 connections 8193 finished 6469 rev 512 unfinished 250 guides 1474 ------------------------------------------------------------------------ DATE: 17-Oct-2016 Topic(s): Work on High Current Traces This is finally almost finished. This also required moving some parts of some traces outside of the 4.5 mm keep out zone. Needed to make a new Routing Via to better fit the width of the high current traces. Details about the cross section and current capacity of these traces is near the end of the ab file: hub_0_ab_power_distribution_strategy.txt Status: comps 2779 rev 1171 nets 3761 rev 573 connections 8148 finished 6424 rev 509 unfinished 250 guides 1474 ------------------------------------------------------------------------ DATE: 17-Oct-2016 Topic(s): Weekend work on Fill Shapes and today work on High Current Traces Details of the High Current traces from Zone 1 connector to and between the ATCA Power Modules have been added to the ab file: hub_0_ab_power_distribution_strategy.txt Status: comps 2779 rev 1169 nets 3761 rev 573 connections 7976 finished 6252 rev 505 unfinished 250 guides 1474 ------------------------------------------------------------------------ DATE: 14-Oct-2016 Topic(s): Working on non high-speed clean up. Also routed the stupid Hold-Up capacitors. This stuff needs to be marked as 100 Volt DC and dangerous. I got as much of it off of the surface layers as I could. Can we not connect the big Hold-Up capacitors and just use a small radial THD cap in the discrete wire holes by the ATCA Input Module ? Started the double up and tripple up of the high current traces for the connections into the ATCA Input Module and between ATCA modules and for the ISO_12V output from the ATCA Module. Status: comps 2777 rev 1168 nets 3761 rev 572 connections 7912 finished 6189 rev 503 unfinished 250 guides 1473 ------------------------------------------------------------------------ DATE: 13-Oct-2016 Topic(s): Finish the last major routing Only the FPGA bypass capacitor remain for final placement and routing connection. This will be done as part of the cleanup of the high-speed traces around the FPGA. The planned open spaces for these bypass capacitors have mostly been retained during the card routing. Status: comps 2777 rev 1164 nets 3761 rev 572 connections 7734 finished 5990 rev 496 unfinished 265 guides 1479 ------------------------------------------------------------------------ DATE: 12-Oct-2016 Topic(s): Routing Overall_HW_Adrs_to_ROD, Meeting with Wade in Rm 2150 Routing the final parts of the HW Adrs setup. Routing lanes look OK to complete this. Putting these nets back into the design as their turn comes up. The Bank 84/94 No_Conn nets are not in the design at this time. Meeting with Wade and Brian and Philippe for part of it. Reviewed work on the Hub layout design, the visit to Debron, and the preliminary stackup and details from the bare board house. Showed Wade my list from the log book about how the Hub MGT Fanout could fail. Wade brought up the problem of testing data links from all slots at once. We want to demand the before Hub production build. Problem of not enough FEX sources and problem of who builds first. Wade suggests that we start discussions of this whole topic and explore the possible solutions to find the best way forward. Status: comps 2777 rev 1162 nets 3746 rev 569 connections 7726 finished 5968 rev 492 unfinished 279 guides 1479 ------------------------------------------------------------------------ DATE: 11-Oct-2016 Topic(s): Hub's FPGA LED control signals and Overall_HW_Adrs_to_ROD Status: comps 2777 rev 1161 nets 3739 rev 567 connections 7717 finished 5957 rev 488 unfinished 281 guides 1479 ------------------------------------------------------------------------ DATE: 10-Oct-2016 Topic(s): Weekend Power Fill work then continue routing the remaining control signals Over the weekend worked on the ECLK_3V3, CNST_5V0, and change cuts in ISO_12V. All fill shapes are getting near final form except for miters. Routing some of the last random control traces. Almost down to only the 24 Hardware Adrs lines left. The I2C Buffer Enables are back in the design. I think that 16 of the Hardware Enables are still out of the design. Status: comps 2777 rev 1160 nets 3739 rev 564 connections 7717 finished 5945 rev 482 unfinished 275 guides 1497 ------------------------------------------------------------------------ DATE: 7-Oct-2016 Topic(s): Routing various control signals Routing: Resets for Flash, Phys, and Swich, Config Done, IPMC LED 4, Handle-Switch, Sensor Bus, Mgt Bus, Entry Alarm, and Power Enable. The expect problem of no paths in the pinch. Status: comps 2777 rev 1160 nets 3740 rev 562 connections 7703 finished 5921 rev 477 unfinished 278 guides 1504 ------------------------------------------------------------------------ DATE: 6-Oct-2016 Topic(s): Power Control to DCDC Converters Continue working on Power Control to the DCDC Converters. All in except to finish the 5 lines to the SWCH_1V2 converter. Status: comps 2777 rev 1160 nets 3740 rev 562 connections 7695 finished 5900 rev 471 unfinished 283 guides 1512 ------------------------------------------------------------------------ DATE: 5-Oct-2016 Topic(s): Finish MDIO/Loop_Det into FPGA Start runs from Power Control to the converters The Switch MDIO and Loop_Det signals are now routed to the FPGA and loop OK and compact so that they do not get in the way of the bypass caps too much. The 19 nets for HW Slot and Shelf and the I2C Buffer Enable that also run to Banks 84 & 94 are still out of the design. Routing the: SMB_Alert_B, First_Enable_1,2,3, POWER_Good 1:7, Converter_Ramp, PMBus_SCL, and PMBus_SDA to the 7 DCDC Converters. Routing paths are more or less open for this. Status: comps 2777 rev 1160 nets 3740 rev 562 connections 7692 finished 5892 rev 466 unfinished 284 guides 1516 ------------------------------------------------------------------------ DATE: 4-Oct-2016 Topic(s): Routing MDIO / Loop Det into FPGA Right now about 19 nets are pulled out of the design to make it easier to work in the almost full Select I/O Banks 84 and 94. Status: comps 2777 rev 1158 nets 3740 rev 560 connections 7653 finished 5799 rev 458 unfinished 325 guides 1529 ------------------------------------------------------------------------ DATE: 3-Oct-2016 Topic(s): Fills and MDIO / Loop Det All fills are back in and stable with all MiniPOD power and BULK_3V3 and BULK_2V5 all on Signal_5. The Switch MDIO and Loop Detect are escaped from the switches and routed upto the FPGA. Status: comps 2777 rev 1158 nets 3761 rev 555 connections 7672 finished 5799 rev 454 unfinished 325 guides 1548 ------------------------------------------------------------------------ DATE: 2-Oct-2016 Topic(s): Work on Fills on Sig_5 Work to move all of the MiniPOD related fills to Signal_5 with the hope of opening up Signal_6 so it can be used to finish the vertical runs through the pinch. This requires arranging the MiniPOD power filters to fit BULK_3V3, BULK_2V5, and the 4 filtered MiniPOD supplies all onto Signal_5. The horizontal runs under the front panel Enet magnetics must also move to Sig_5 as that is the only way to open up Signal_6 for vertical runs. ------------------------------------------------------------------------ DATE: 30-Sept-2016 Topic(s): Routing the FPGA SWCH MDC, MDIO, and Loop_Detect signals Moved around a lot of other stuff to try and make room for the 12 FPGA SWCH MDIO and Loop_Detect signals on Signal_4. The MiniPOD stuff looks OK. Status: comps 2777 rev 1156 nets 3761 rev 555 connections 7667 finished 5794 rev 451 unfinished 319 guides 1554 ------------------------------------------------------------------------ DATE: 29-Sept-2016 Topic(s): Routing MiniPOD Power and Control Signals Status: comps 2777 rev 1156 nets 3761 rev 555 connections 7663 finished 5780 rev 445 unfinished 324 guides 1559 ------------------------------------------------------------------------ DATE: 28-Sept-2016 Topic(s): Routing the MiniPOD Power and Control Signals Status: comps 2777 rev 1152 nets 3761 rev 552 connections 7657 finished 5759 rev 442 unfinished 318 guides 1580 ------------------------------------------------------------------------ DATE: 27-Sept-2016 Topic(s): Routing in Power Supplies The two NE converters and the two linear converters are now all routed and look OK. I need to make separate geometries for the two instances of the linear LDO LT1764A regulator. In the case of the MGT_AVAUX supply the pin #6 can have a quite large thermal pad but no Gnd vias close to it as it is right over the FEX MGT feeds to the ROD. In the case of the BULK_2V5 supply the pin #6 must have a very compact thermal pad but it can have lots of thermal/Gnd vias in this pad to get the heat down to the Ground planes. Must verify these new pin #6 thermal/Gnd pads with Brian's email note about the current geometry for the LT1764A. Now need to go through all 7 DC DC Converters and correectly set the servo loop component values for the 4 converters for which Brian knows their values and update the "ab" power supply description file. Must go through all 9 power supplies and decide / setup which of the specialized component values are assembly house installed (if any) and which are MSU Final Assembly installed and correctly setup the one_solder_blob geoms and verify which of these comps are ending up in which BOM file. I.E. still lots of power supply and their comps work. Status: comps 2777 rev 1145 nets 3761 rev 552 connections 7640 finished 5707 rev 439 unfinished 296 guides 1637 ------------------------------------------------------------------------ DATE: 26-Sept-2016 Topic(s): Mentor design of Via Plugs, back to routing Over the weekend worked out a way to implement the Via Plugs in the Mentor design setup for the Hub Module. The Via Plugs are separate for the ones applied from the top and from the bottom. I've set them up as Gerber plots 23 and 24. So far I have tested them with QFN-32 and QFN-48 geometries. I need to expand this to the 3 types of QFN-16, the Switch, the Phys-48 and for the close in vias used in the MGT Fanout. These close in MGT Fanout vias will need versions for plugging from the Top and plugging from the bottom. Back to pcb routing. Picked this up with Rev 404 of the traces data even though this had moved to Rev 433 during fill generation for the intermediate release. Started with the clean up of some additional things that I spotted while working on the gerbers for the intermediate release. Now working on DCDC 6 and 8. Status: comps 2777 rev 1135 nets 3761 rev 551 connections 7608 finished 5575 rev 435 unfinished 286 guides 1747 ------------------------------------------------------------------------ DATE: 23-Sept-2016 Topic(s): Trip to Debron MSU car trip to Debron. Delivered the Hub Kit of this date. Returned some non-MSU parts from 2011 that had been packed into the left over CMX assembly parts. Meeting with George, Jack, Josh, and another production engineer. Topics; plugging center pad vias, blind via vs back drill, inner corner radius, MSU needs a board pre assembly, the minus FPGA board is also minus the ATCA modules, the 3 types of backplane zone 2 connectors, solder paste percent coverage on the QFN parts both center pad and perimeter signal pads, solder mask on the switch parts, connector press in requirments, parts storage for up to a year. Debron is going to start working with the pare board house next week on the bare pcb topics. It will be the same bare board house as CMX. ------------------------------------------------------------------------ DATE: 21,22-Sept-2016 Topic(s): Package the Hub Kit and write the Kit inventory file which is on the web with the Intermediate Release documents Pulling the chicklets out of the Zone 1 and Zone 2 connecters takes a lot of time. I used a technique so that I never touched the pins on the zone 2 connectors. ------------------------------------------------------------------------ DATE: 20-Sept-2016 Topic(s): Work on the text files for the Intermediate Realease, put it on the web, send note to George, start Kit and its Inventory. ------------------------------------------------------------------------ DATE: 19-Sept-2016 Topic(s): Correct more problems from Gerber and work on the text text documents for the Intermediate Releasse, Comps files for Brian More problems found by looksing at the Gerber plots, e.g. a via in the middle of the FPGA. Get the BOM files and Comps counts and X,Y files ready for the Intermediate Release. It takes about 20 minutes to generate a full set of Gerbers. Currently the 22 Gerber files are about 25 MBytes total. The Traces file with the fills in it is about 15.5 MByte larger than the traces file without fills. Now have Mentor Nets, Comps, and Geometries all on the web so they are easy to get at. When over the comps file layout with Brian and the use of Layout to figure out what comp is what. ------------------------------------------------------------------------ DATE: 18-Sept-2016 Topic(s): All work was in correcting problems with the Gerber plots Worked on the .sh files for generating the Gerber plots. For now I will stay with 3 forms of the Ground Planes although it's not really clear how many we will need. All other work was in fixing gerber plot problems e.g. paste stencil for the Switches is all screwed up, solder mask is wrong for FPGA, MegArray, Switch, and too thin for all QFN-16, Gnd Plane Combined Data Caps have no relief, ... Not clear how good the gerbers need to be for the intermediate release but right now they are a mess. ------------------------------------------------------------------------ DATE: 17-Sept-2016 Topic(s): All work was on Area Fill clean up Worked on clean up of the Area Fill shapes, e.g. getting in enough copper so that FAN_1V8 has a chance of working and removing the Sig_12 copies of the ISO_12V Shapes that are identical to the Sig_11 copies. Do get confused - this is not removing Fills rather it is just having one copy of the Shape where the Shape is identical for the fills on two separate Layers. Worked on another set of both Medium and Hi resolution clearances for the High_Speed traces on Layers 11 and 12. Status: 47 Shapes 47 Fills comps 2777 rev 1125 nets 3761 rev 551 connections 7008 finished 6267 rev 433 unfinished 81 guides 660 Note - traces_404 remains the good/correct version to go back to after this practice Fill work. ------------------------------------------------------------------------ DATE: 16-Sept-2016 Topic(s): All work was on generating the Area Fills and Gerber Files With 45 Shapes and 45 Fills in the design (the 4 MiniPOD fills are not in and 5 others must still be missing ?) the Status is: comps 2777 rev 1125 nets 3761 rev 551 connections 7004 finished 6253 rev 428 unfinished 83 guides 668 Note - traces_404 remains the good/correct version to go back to after this practice Fill work. The worst and currently unusable fill is both of the FAN_1V8 fills. The long horizontal row of in/out connections under each row of Fanout Chips almost cuts the chips off from the FAN_1V8 supply. Must go West but that is of no help on Signal_11 with its Equalizer Enable traces. Not clear what to do. This needs to be a stiff 20 Amp connection. Moving the Diff_Pair_HS Net_Type fill to pin/via/trace out to 0.35 mm looks pretty good (as done on only Sig_12). The only rule that actually makes a difference is Fill-Pin. From looking at the fills, I don't think that the MiniPOD Nets have the High-Speed Property set. Missing from the 54 are: on Sig_5 the BULK_3V3 connector South of the MegArrays (but it is really out of the design) and on Sig_11 the two DVDDL nets for U21 and U22. Other 2 ? ------------------------------------------------------------------------ DATE: 15-Sept-2016 Topic(s): All work was on generating the Area Fills Stuck most of the day with a problem generating one of the Area Fills on layer Signal_6 - message: // Note: Input_Shape cannot merge with 1 other Input_Shape(s), because of different parameters. (from: Idea/Util/Fill 85) Asside from that the scripted generation of Fills is working well. Still need to make final adjustments of the Design Rule fill clearances to other fills, vias, pins, and traces for the three classes of nets in the Hub design. Using different parameters for the general area of the card and for under the BGAs. For now these 24 parameters are just adjusted to something middle of the road/rational. Note that the boarder between the BULK_1V8 & MGT_AVAUX fills under the FPGA is still not correct. There is the question of keeping the BULK_1V8 fill rather wide and connecting the two MGT_AVAUX out layers by trace. Status: comps 2777 rev 1125 nets 3761 rev 551 connections 7603 finished 5529 rev 423 unfinished 286 guides 1788 Note - Holding on to traces_404 as the good/correct version before the Fill work started. ------------------------------------------------------------------------ DATE: 14-Sept-2016 Topic(s): All day on Fill Shapes We currently have 52 Area Fills in the design. The whole day was spent checking them and cleaning them up. Except for the 4 MiniPOD fills most of these should be in about final form. None of them have mittered corners yet. Basically none of the fills look very strong. The East side bulk ISO_12V filter caps and the Hold-Up caps and Wire Terminals were rearranged as part of the fill shape editing. These parts should now be in final positions. Status: comps 2777 rev 1125 nets 3761 rev 551 connections 7603 finished 5529 rev 404 unfinished 286 guides 1788 ------------------------------------------------------------------------ DATE: 13-Sept-2016 Topic(s): Backside Metal setup and working on: QFNs, Switch, and PVAs, Working on Gerbers and Fills, Debron Schedule The backside metal is working and "finalized" on the 6x QFNs, the Switch, and the 8x PVAs. They look OK and the Top and Bottom Gerbers look OK and are generated cleanly by script. Debron is expecting intermediate files on the 19th and we have a meeting scheduled on the 23rd. Working on fill shapes and positioning the East side Iso_12V caps. Status: comps 2777 rev 1122 nets 3761 rev 551 connections 7603 finished 5529 rev 403 unfinished 285 guides 1789 ------------------------------------------------------------------------ DATE: 12-Sept-2016 Topic(s): Routing DCDC 2,3,7 Backside Metal Worked out the scheme that I will use for placing the backside copper for the QFN, Switch, and PVA components. The details are given in the hub_0_ab_trace_routing_details.txt file. So far I have implemented this scheme in the 8 PVA components. This is not a standard Mentor method but I have checked it by making top and bottom side plots. It appears to be working OK but I need to check by implementing it with the 5 or 6 QFN components and with the Switch component. Worked on the Artwork Order file and the script to generate the Gerber plots. Added another output cap a Cap_22_uFd_10_V_1206 component to all three of the 20 Amp converters. These three converters are now routed. Status: comps 2777 rev 1114 nets 3761 rev 551 connections 7594 finished 5510 rev 402 unfinished 286 guides 1798 ------------------------------------------------------------------------ DATE: 11-Sept-2016 Topic(s): DCDC 2,3,7 layout work Added a 21st PVA and brought all 3 of the 20 Amp converters up to the same design. It's starting to look a lot better. Status: comps 2774 rev 1109 nets 3761 rev 550 connections 7557 finished 5344 rev 398 unfinished 274 guides 1939 ------------------------------------------------------------------------ DATE: 10-Sept-2016 Topic(s): Work on DCDC2 (3,7) routing continues Currently added a total of 9 PVAs in DCDC2 for its filter inductor and to stiffen other Ground connections. List: PVA12 Filter Inductor Input 6 pin MGT_AVCC_Pre_L PVA13 Filter Inductor Input 3 pin MGT_AVCC_Pre_L PVA14 Filter Inductor Output 6 pin MGT_AVCC PVA15 Filter Inductor Output 6 pin MGT_AVCC PVA16 Filter Inductor Output 4 pin MGT_AVCC PVA17 Filter Inductor Output 4 pin MGT_AVCC PVA18 Filter Inductor Output 3 pin MGT_AVCC PVA19 Converter Input Caps 3 pin GROUND PVA20 Converter Output Tant 3 pin GROUND These additions and moves of: C1051, R1051, R1052, PVA9, PVA5, PVA11, and PVA7 must be edited into DCDC3 & DCDC7. All three nets files need editing and trc is ready to copy. Major remaining design issues: - Get the silk off of the PVAs. I thought that I had done this but I only pulled it off of the DPV arrays. - The backside metal is missing on all of the PVAs. - The backside metal is missing on all of the QFN parts and on the center thermal pad of the Switch geometry. All of these parts (7 of them or something like that) use the same basic design so it should be easy to fix. - Where is the fill or other connectivity for CNST_5V0 ? Status: comps 2753 rev 1108 nets 3761 rev 549 connections 7490 finished 5344 rev 398 unfinished 274 guides 1872 ------------------------------------------------------------------------ DATE: 9-Sept-2016 Topic(s): Routing of DCDC1 and DCDC2 and some other general routing clean up DCDC1 routed without much trouble. Needed a lot of work on DCDC2 (3, 7) to add rational high current connections for the output filter inductor. This now looks good. Currently 5 additional PVAs in DCDC2 for its filter inductor and to stiffen other connections. Status: comps 2749 rev 1106 nets 3761 rev 548 connections 7456 finished 5331 rev 397 unfinished 274 guides 1851 ------------------------------------------------------------------------ DATE: 8-Sept-2016 Topic(s): ROD: Present, SMB, Power Control routed to Hub FPGA, Meeting with Wade and Philippe Wade stopped by for a meeting with Philippe and me. Most discussion was about what we do once we have Hub cards, e.g. - required and desired tests before the ROD/Hub get together, - required and desired tests at the ROD/Hub get together, - tests after the ROD/Hub get together - full MSU Production testing of the Hub Modules before shipping My strong concern remains about the fanout section and the routing density of the MGT signals: - Oscillation could be OK but it could have so much cross-talk that no communications is possible. - Oscillation could be OK but as FEX cards are plugged in the cross-talk builds up so that only with most of the FEX cards running does the communications fall apart. I.E. at the start everything looks OK. - Oscillation could be a problem but by driving all FEX slots the oscillation problem goes away, i.e. we need dummy driver cards and must use 14 slot crates to run the system. - Oscillation is a fixed inherent problem of the fanout layout and nothing can be done about it. Status: comps 2744 rev 1101 nets 3761 rev 548 connections 7434 finished 5178 rev 392 unfinished 265 guides 1991 ------------------------------------------------------------------------ DATE: 7-Sept-2016 Topic(s): Routing SysMon Ref and JTAG Status: comps 2744 rev 1100 nets 3761 rev 547 connections 7433 finished 5169 rev 387 unfinished 262 guides 2002 ------------------------------------------------------------------------ DATE: 6-Sept-2016 Topic(s): Work over the weekend and Routing work Over the weekend worked on bring some of the drawings up to date with the current design. Email with George and proposed an intermediate release of data on about Monday Sept 18th, i.e. about 2 weeks from now. Finally I have the ROD's SMBAlert_B signal in the design. I'm using an isolation resistor in it like in the other power control signal from the ROD. An issue is that in the July ROD schematics I do not see the signal SMBAlert_B signal connected to is pin S1-B27 as it is specified in the official MegArray pinout. Finally pulled the Sig-5 traces out of the areas of the 3 Switch chips that cut through the Switch's 3V3 fill. From necessity there are still trace cuts in the perimeter of the Switch 3V3 fill. The ab_power_distribution_strategy has been brought up to date with the 7 Wire-Term pairs that are now in the design. Status: comps 2744 rev 1096 nets 3761 rev 546 connections 7427 finished 5132 rev 381 unfinished 263 guides 2032 ------------------------------------------------------------------------ DATE: 2-Sept-2016 Topic(s): Routing: Config Ctrl and Pull-Ups, JTAG, and Power Control Finally have all of the Configuration Control Jumpers and Pull-Up Resistors routed. Started work on the JTAG and Power Control. This required lots of component location changes. There are still many signals to get up through the pinch. To help route these I freed up Sig_4 by moving the Ethernet Magnetics to RJ45 Sig_4 traces to Sig_6 and thus giving up on having the BULK_1V8 fill wide enough to run under this area. Status: comps 2743 rev 1094 nets 3756 rev 542 connections 7430 finished 5119 rev 377 unfinished 263 guides 2048 ------------------------------------------------------------------------ DATE: 1-Sept-2016 Topic(s): All work today on routing the 4 TBD_Spare_Links from the ROD, Meeting with Wade, Assembly PO # Routed the 4 TBD_Spare_Links from the ROD to the Hub. They are routed as 4 differential pairs. They have a complicated route through the main capacitor array for the Isolated +12V supply. This sounds bad but their clearances to the mass of vias in this array is OK. Currently the hard part looks like the 24 lines to carry around the crate/slot hardware address - but they are DC. Next is the JTAG I think and then the 10**9 I2Cs. Meeting with Wade about "what next steps" and first get together of ROD-Hub, and Hub testing and such. They have a meeting about these topics tomorrow. We have an Assembly PO Number: 316358 Status: comps 2742 rev 1087 nets 3755 rev 539 connections 7430 finished 5069 rev 372 unfinished 257 guides 2104 ------------------------------------------------------------------------ DATE: 31-Aug-2016 Topic(s): Routing Ethernet: Top of The Backplane and to ROD, FAN_1V8 Power Supply Move The Top of Backplane and ROD Ethernets are now routed but they still both need a lot of clean up. The show down just South of the MegArrays resulted in deleting the Bulk_3V3 fill that runs just South of these connectors to supplement the long loop over the top. Yet another not nice compromise in this layou but it was that or else vias in the MGT Readout Control circuit from the ROD. I removed the inversion in the ROD's Ethernet Circuits that had been asked for at one time. Hub matches the July ROD schematics. Hub net-names match the ROD schematic net-names and the general layout matches Host-2. Had to move the DCDC_7 FAN_1V8 supply. It is now rotated 90 deg and now more South than East of the ROD. It all looks fine except that its LC Filter's output connection to the FAN_1V8 Fill is way up in the NE corner of the fill. Status: comps 2742 rev 1087 nets 3755 rev 538 connections 7430 finished 5061 rev 367 unfinished 257 guides 2112 ------------------------------------------------------------------------ DATE: 30-Aug-2016 Topic(s): Routing Ethernet to the Top of the Backplane Worked on routing the two Ethernet connections that are at the Top of the Backplane, i.e. This Hub's FPGA to the Other Hub's Switch and the Other Hub's FPGA to This Hub's Switch. As expected there are no open paths. I don't think that the architects of the Hub with its 74 channel Fanout gave much thought to the PCB routing implications. Status: comps 2742 rev 1080 nets 3755 rev 537 connections 7430 finished 5037 rev 364 unfinished 273 guides 2120 ------------------------------------------------------------------------ DATE: 29-Aug-2016 Topic(s): MGT Links to ROD, MGT Links to the Transmitter MiniPOD Weekend work on: 6x DPV components, DCDC converter locations, and area fills. DCDC 1 and 2 were moved West with the air flow spacing now taking into consideration the finter inductors associated with DCDC 2 and 3. Area fills on Sig 11 and 12 were adjusted and generally cleaned up. The Area Fills were added for the 2V5 and 3V3 Clocks. Made 1.1 mm DPV component to clean up MiniPOD Receiver routing. Monday routed the MGT: Combined Data, 2x Readout, and Readout Control to/from the ROD. Routed 8 of 12 MGT links to the MiniPOD Transmitter. The available layers for all of this high-speed routing are very limited. Keep in mind that Sig_5 is not available and the exiting the FPGA on the rest of the upper half is blocked by the MGT inputs to the FPGA. Routing on Sig 8 and 9 is basically the only way to get to the MiniPOD Transmitter. The current Major Issues include: where did the fills under the MiniPODs go ?, Sig_5 routes to the Switches that cut their fills, missing opposite side pad copper in PVA, FQN, major screw up in combining the Med and Hi resolution Fills, i.e. file size no longer matters but different clearance rules still do matter. Need to rework the fills yet again. Status: comps 2742 rev 1076 nets 3747 rev 535 connections 7430 finished 5029 rev 358 unfinished 277 guides 2124 ------------------------------------------------------------------------ DATE: 26-Aug-2016 Topic(s): Configuration PROM and Receive MiniPOD Need another DPV spaced 0.1 mm further apart for MiniPOD routing. The configuration Flash PROM is now routed and has gone through one good round of clean up. It looks OK but - does it need to move West to get further away from the FPGA (for manufacturing) but not too far West to block the vertical routes ? Status: comps 2741 rev 1070 nets 3747 rev 529 connections 7442 finished 5003 rev 353 unfinished 277 guides 2162 ------------------------------------------------------------------------ DATE: 25-Aug-2016 Topic(s): Brought both the FPGA comps and Flash Config comps out of RPCS, Routing Config Jumpers and PROM All of the Flash Config PROM comps file is now just a flat comps file. The FPGA associated comps have been split into the existing RPCS and a flat normal comps file. As I move more of the FPGA associated comps around I'm putting them in the flat file as the FPGA itself has been fixed since the 25-July-2016 meeting. Status: comps 2735 rev 1060 nets 3747 rev 526 connections 7423 finished 4925 rev 348 unfinished 277 guides 2221 ------------------------------------------------------------------------ DATE: 24-Aug-2016 Topic(s): Routing Clock Power and the traces to the two Phys chips Finished the power routing to supply the Clock section. The CLK_3V3 Filter is feed from an area fill and the CLK_2V5 Filter is feed via a discrete wire. Routed all of the traces from the FPGA to the two Phys Chips. With one swap this followed the plan in drawing 45. Status: comps 2735 rev 1053 nets 3747 rev 526 connections 7419 finished 4874 rev 344 unfinished 277 guides 2268 ------------------------------------------------------------------------ DATE: 23-Aug-2016 Topic(s): Clock Generation Routing I fixed the default inputs to the unused section of the TI Fanout Chips so that they are Tied Off. They suggest pulling both unused inputs to Gnd with 1k Ohms. I pulled one to Gnd this way and tied the other to their common mode reference. That should clearly bias to input to a known state. Almost finished routing the Clock Generation sections. Need to update Drawing 40B. Status: comps 2727 rev 1048 nets 3747 rev 524 connections 7394 finished 4815 rev 339 unfinished 293 guides 2286 ------------------------------------------------------------------------ DATE: 22-Aug-2016 Topic(s): Clock and Resistor Routing Weekend work on the TI version of the QFN-16 geometry for the CDCLVD1204 and on the FPGA Heat Sink trying on it to make the pinch mounting screws symmetric on the East and West sides. Today worked on placing and routing some of the MGT Termination Calibration resistors, the pull-down resistors on the VREF pins and the DCI calibration resistors. Also worked on placing and routing in the Clock Generation section. Gave up on sourcing the CLK_2V5 via an Area Fill and started installing the setup for another discrete wire power feed. Status: comps 2725 rev 1034 nets 3749 rev 521 connections 7383 finished 4762 rev 334 unfinished 295 guides 2326 ------------------------------------------------------------------------ DATE: 19-Aug-2016 Topic(s): Scheduled Power Outage, Work on Ethernet to Other Hub and Clock Generators, Note Sent to Select Assembly Vendor Scheduled power outage with computer restart. Previous boot was 459 days ago. Worked on routing the remaining Ethernet traces which are the Hub to Hub connections including finally pulling Rows 1 and 2 out of connector P20. Sent note to request the assembly services PO. Status: comps 2722 rev 1024 nets 3749 rev 518 connections 7370 finished 4693 rev 331 unfinished 291 guides 2386 ------------------------------------------------------------------------ DATE: 18-Aug-2016 Topic(s): Routing Work Finished the Equalizer Enable routes and the Reference Clock from the Other Hub. For the Equalizer Enables I routed part of them on the 1 oz center high current power fill layer Signal 11. I hope this is quiet enough to be OK. The route on Sig 11 is just a very short cut out of the West edge of the FAN_1V8 fill and then splits the Clock_3V3 and Clock_2V5 fills. The intent was to do nothing to harm the high-speed traces and this keeps the Equalizer Enqbles well away from them. All Fanout <--> FPGA and FPGA <--> Backplane routes are now in. Status: comps 2722 rev 1023 nets 3765 rev 517 connections 7370 finished 4677 rev 329 unfinished 291 guides 2402 ------------------------------------------------------------------------ DATE: 17-Aug-2016 Topic(s): Routing Work, Meeting about Assembly Bids The attack on the odd ball connections to the Backplane is under way. The two MGT Readout lanes from This Hub to the Other Hub are routed and look OK. The 40.08 MHz Reference Clock from the Other Hub is routed as far as a Diff Pair Via that is on the West side of the vertical run up to the ROD so a path for it should now be open. 5 of the 13 Equalizer Enables are routed. NOTE that I have changed my mind and will use a couple of Select I/Os in Banks 70 and 72 to handle some of these. I'm using just the very perimeter pins in 70 and 72 with BGA Pad Only and thus I'm sticking with the spirit of the law in that there are no pin associated vias from Banks 70 and 72 to cause problems for the High-Speed signals or the Clock Signals. I'm still looking for paths for the other 8 Equalizer Enables. The main problem is needing to feed the Enable signal to two rows. Bid review meeting with Wade, Philippe, and Brian. Debron is less money and the same delivery schedule. All of the other points look OK. I will let Janice and Debron know our choice. I need to set a trip to visit them and start a review to understand the PCB questions and other assembly problems. Status: comps 2722 rev 1022 nets 3765 rev 513 connections 7363 finished 4651 rev 322 unfinished 305 guides 2407 ------------------------------------------------------------------------ DATE: 16-Aug-2016 Topic(s): Combined Data and Equalizer Enable Routing Pulled out all of the Combined Data routes to the Backplane and did them again so that I could move their AC Coupling Capacitors. I had tried to put these capacitors in a column near the backplane connectors but it does not look right and the required bypass caps on the Fan_1V8 bus do not have good locations. Moved to the Combined Data AC Coupling Caps to about the middle of their traces. The Equalizer Enable traces are routed within the MGT Fanout itself but there is still no path available to route most of them to the FPGA Bank 71. I moved all of the Bank 71 connections around to get the Equalizer Enables, Lock Detects, and Second 40.08 MHz Fanout Clock Select in good order for when route paths become visible. Status: comps 2719 rev 1015 nets 3765 rev 508 connections 7353 finished 4626 rev 316 unfinished 312 guides 2415 ------------------------------------------------------------------------ DATE: 15-Aug-2016 Topic(s): 320.64 MHz Clock Routing The push over the weekend was to find paths for the 320.64 MHz Clock traces from the Fanout and under the FPGA. This is 8x MGT Reference Clock and 1x Logic Clock to HP IO Bank 71. All routed on one layer. These were put in today along with all of the 320.64 MHZ Fanout connections except for its input runs. The Logic Clock feed to Bank 71 was modified to include Back Terminators so tha the LVPECL swing will look more like LVDS swing. The Clock Circuit Drawings were brought up to date. Started working through the Zero Length traces that were flagged by Philippe's Diff Trace Length that are NOT No_COnn_* nets. So far the issue is needing to name all Single Point Nets starting with No_Conn. Status: comps 2719 rev 1013 nets 3765 rev 505 connections 7291 finished 4514 rev 313 unfinished 365 guides 2412 ------------------------------------------------------------------------ DATE: 12-Aug-2016 Topic(s): FEX FO to Hub FPGA Length Clean Up, 320 Clock Routes Finished copying of the FEX FO Unit Cell to all 74 locations. Worked on matching trace length in the FEX FO to Hub FPGA. Philippe's Length Difference tool is the "enabling technology" to get that done. Worked on routing paths for the 9 copies of the 320.64 MHz Clock into the FPGA. That looks OK for now. Need to find routes for: Clock From Other Hub, 2x Readout To Other Hub, 13x Equalizer Enables. Status: comps 2717 rev 1005 nets 3763 rev 501 connections 7264 finished 4402 rev 310 unfinished 365 guides 2497 ------------------------------------------------------------------------ DATE: 11-Aug-2016 Topic(s): Final MGT FO Routing Remove the temporary "test case" routing from the MGT Fanout. This brings us to: comps 2717 rev 992 nets 3763 rev 500 connections 7190 finished 2996 rev 301 unfinished 291 guides 3903 Verify that things look OK and then swap in the final three QFN-16 Geometries. Then start the final routing inside the MGT Fanout. Still need to understand the problem with the opposite side copper on the center pad. Wasted a couple of hours exploring a more symmetric way to place the Vcc bypass capacitors around the fanout chips. It does not work because of the need for surface routing paths. Final choices for the Term Ref and Vcc bypass caps. Moved to follow the OnSemi recommended value for the Term Ref cap --> yet one more component type needed for the build. Routed the full bottom Row: comps 2717 rev 1004 nets 3763 rev 500 connections 7198 finished 3148 rev 306 unfinished 299 guides 3751 Trace file revision summary: 300 Before the Delete 301 Right after the Delete 305 Two Left-Hand Bottom Row sections done 306 Full bottom Row done. Today Janice send us the bids for Hub Assembly. Debron and ADCO both submitted bids. ------------------------------------------------------------------------ DATE: 10-Aug-2016 Topic(s): Combined Data Routing Clean Up QFN-16 Geometry Work Work on clean up of the Combined Data Routing. Use Philippe's Diff Trace Length tool to get a first look at these now clean routes. A lot of swapping is going to be needed. To finish the MGT FO to Hub route trace length work I need to get in the routes to the AC coupling caps and the routes from the coupling caps to the DPV comps. Right now I just have these routes in for a couple of test cases. To make these routes final I need the final version of the QFN-16 comp for the MGT FO NB7VQ14M on both the Top and Bottom of the card. This leads to a ton of work trying to understand the differences in the TI and On_Semi reccomendataions for the QFN-16. This leads to splitting into different QFN-16 geometries for TI and On_Semi. Status: comps 2717 rev 992 nets 3763 rev 500 connections 7197 finished 3073 rev 300 unfinished 292 guides 3832 ------------------------------------------------------------------------ DATE: 9-Aug-2016 Topic(s): Start Combined Data Routing Started work on the Combined_Data routes. All are in but some are just place holders. Moved the Combined_Data AC Coupling Caps to the area by the Backplane Connector. Many posibilities for match trace length. Many issues with routes due to bypass capacitor placements. Next need to finalize the QFN-16 top/bot geometry for the Mot Fanout chips so that I can route Fanout chip to DVP. Philippe returns with his Differential Trace Length comparision program. This makes checking the routing options a lot faster and with a lot fewer errors. One can now check the routing options without going crasy. Status: comps 2717 rev 989 nets 3763 rev 500 connections 7197 finished 3073 rev 296 unfinished 292 guides 3832 ------------------------------------------------------------------------ DATE: 8-Aug-2016 Topic(s): East edge MGT Routing, Fill Areas Worked over the weekend and today on: Area Fill Shapes in the area under the FPGA (recall FPGA was moved North after the FEX-MGT and MGT power decision two weeks ago), FPGA geometry along its (as placed) East edge, the 12 MGT Receiver connections on the FPGA East edge. All 74 FEX MGT Receiver connections are now routed. The North & South edges are pretty final. Still lots of optimization work on the East edge. Status: comps 2717 rev 983 nets 3763 rev 496 connections 7197 finished 3021 rev 291 unfinished 292 guides 3884 ------------------------------------------------------------------------ DATE: 6-Aug-2016 Topic(s): FEX MGT Receiver Routing All of the Upper East side is in and looks more or less OK. Working on clean up. Lots of FPGA Geom changes needed. For now pulled out DPV625 and 626 for the inputs from the Other Hub. It will be very nice if these are not needed. Status: comps 2683 rev 971 nets 3763 rev 487 connections 7131 finished 2943 rev 283 unfinished 304 guides 3884 ------------------------------------------------------------------------ DATE: 5-Aug-2016 Topic(s): MGT Receiver Routing The North and South MGT FEX Receiver routes are in and look as expected and look OK. An issue is that I *think* that I want to change from using just a via-pair to handle the BGA Pad Only routes that come out on the L1 copper to using the Differential Via Pair Component with its Gnd Rivet and its automatic taking care of the Plane Relief around the high-speed differential pair. This will be a lot of work to pull out the via and swap in these Diff Via Pair Components now that the routes are in. Currently working on FEX MGT Receivers at the top of the East side of the FPGA. 4 of 6 look like they have clean routes but I have not studied their diff trance length match yet. So far it looks like there is space for Heat Sink mounting screws along the East edge. I have turned back on the FPGA Heat Sink with so far just 2 screw holes. I need to and I think can move the 320.64 MHz Clock Distribution fanout and its RC networks closer to the FPGA. Doing so will give space for some the the Lower East side FEX MGT traces to route between the 40.08 MHz and the 320.64 MHz Clock Distributors. That route is their shortest path. Status Main Path: comps 2685 rev 970 nets 3763 rev 486 connections 7135 finished 2943 rev 282 unfinished 292 guides 3900 ------------------------------------------------------------------------ DATE: 4-Aug-2016 Topic(s): MGT Receiver Polarity vs Trace Length South side now work on North The South side Fanout data connections to their MGT Receivers are all routed. On the South side with two serpentines we have the following trace length match: Ch 6 CMP Ch 6 DIR Ch 7 CMP Ch 7 DIR -------- -------- -------- -------- OCP_Hub: 2.33 2.71 2.71 2.33 OUT_Hub: 147.81 147.54 153.05 153.30 SUM: 150.14 150.25 155.76 155.63 -------------------- -------------------- Delta: 0.11 0.13 Shorter Is: CMP DIR Serpen Is In: CMP DIR Note: that the last line is to check that I have not over compensated for the length match. Now start checking the 16 possible arrangements for matching trace length on the North side. First test for length match of Flipped and Not-Flipped in the NW Quadrant. Ch 66 "red" Not-Flipped to Rows 3,4 Driver on Bot Ch 67 "blue" Not-Flipped to Rows 1,2 Driver on Top Ch 68 "tan" Flipped to Rows 3,4 Driver on Bot Ch 69 "green" Flipped to Rows 1,2 Driver on Top Ch 66 CMP Ch 66 DIR Ch 68 CMP Ch 68 DIR --------- --------- --------- --------- OCP_Hub: 2.33 2.71 2.33 2.71 OUT_Hub: 108.21 109.82 117.38 116.66 SUM: 110.54 112.53 119.71 119.37 --------------------- --------------------- Delta: 1.99 0.34 Shorter Is: CMP DIR So for the Rows 3,4 (i.e. Receivers 1 and 3) use Flipped polarity with one serpentine in DIR. Ch 67 CMP Ch 67 DIR Ch 69 CMP Ch 69 DIR --------- --------- --------- --------- OCP_Hub: 2.71 2.33 2.71 2.33 OUT_Hub: 112.82 113.52 125.97 124.37 SUM: 115.53 115.85 128.68 126.70 --------------------- --------------------- Delta: 0.32 1.98 Shorter Is: CMP DIR So for the Rows 1,2 (i.e. Receivers 0 and 2) use Not-Flipped polarity with one serpentine in CMP. Final check with the seerpentines now in place Ch 67 CMP Ch 67 DIR Ch 68 CMP Ch 68 DIR --------- --------- --------- --------- OCP_Hub: 2.71 2.33 2.33 2.71 OUT_Hub: 113.05 113.52 117.38 116.88 SUM: 115.76 115.85 119.71 119.59 --------------------- --------------------- Delta: 0.09 0.12 Shorter Is: CMP DIR Serpen Is In: CMP DIR So Flip the North side feeds to Rec 1 and 3 pins in Rows 3,4 one serpentine delay in DIR. No-Flip the North side feeds to Rec 0 and 2 pins in Rows 1,2 one serpentine delay in CMP. Well that was interesting by now redo the routing topology to take into consideration the Heat Sink mounting screw holes and check again: Ch 67 CMP Ch 67 DIR Ch 68 CMP Ch 68 DIR --------- --------- --------- --------- OCP_Hub: 2.71 2.33 2.33 2.71 OUT_Hub: 121.82 122.31 125.99 125.50 SUM: 124.53 124.64 128.32 128.21 --------------------- --------------------- Delta: 0.11 0.11 Shorter Is: CMP DIR Serpen Is In: CMP DIR Status Main Path: comps 2685 rev 970 nets 3763 rev 485 connections 7135 finished 2895 rev 275_real unfinished 310 guides 3930 ------------------------------------------------------------------------ DATE: 3-Aug-2016 Topic(s): Video Meeting with the Normal Suspects, Setup an account for Brian to look at Geometries Wade setup a video meeting with Yuri, Philippe, Pawel, and Brian to help figure out: How to finish the design and have it ready for release in 3 1/2 weeks, How to start MSU Testing of the card once we have a Hub. Brian will try to finish P.S. loop component study by sometime next week. He can then start on verifying the Geometries - probably starting with the P.S. components. Initial MSU Testing will probably be: first are the power supplies and clocks all OK, then branch into three somewhat separate activities: Switch, MGT, and the complete IPBus chain, i.e. Phys, MAC, FPGA. Most/All of this stuff will require some FPGA FW and figuring out what tests we are going to do will drive what FW we need. Philippe is going to work on an overall description of Initial MSU Testing. At some point we need a FEX like object to generate data as we have no other way to drive most of the inputs on the Hub card. At some point we need to get together with a ROD. There should be lots of overlap between the ROD and Hub FW for testing their FEX inputs. Yuri has/is pushing on the IPBus chain and will pass to Philippe notes about what SW and FW is available. Setup an account for Brian to look at Mentor Geometries and we went through the basics of the 12 Amp DCDC Converter Geometry. He will start Geometry checking next week. While doing this I noticed that both ATCA Module Geometries are currently broken in some way that I do not understand. ------------------------------------------------------------------------ DATE: 1-Aug-2016 Topic(s): MGT Receiver Polarity vs Trace Length, FPGA Geometry The end of last week and over the weekend I have made a push to understand the best way to escape/route the differential traces from the MGT receivers along the South edge of the FPGA, i.e. rows 43/44 and 45/46. There are 16 possible ways to route these traces and the point is to find the ones that have the best trace length match within a differential pair. The only way to do this is to actually route them with all of the corners smoothed an such and measure / compare their internal length differences. The Mentor files for this study have been branched off of the Main path into a Durand path. Recall: that MGT Fanout Drivers on the oposite side of the card have their output swapped wrt which polarity of the signals is on top on the long horizontal runs over to the FPGA. Thus for example, if to get the best differential length trace match with a Bottom side driver when you Flip the Polarity then with a Top side driver you do NOT need to Flip the Polarity to get the best trace length match, i.e. the same trace topology. Recall: that these net names are of the form: GTH_FO_CH_*_OCP_HUB_CMP # from the Fanout Chip GTH_FO_CH_*_OCP_HUB_DIR # to the DC Blocking Cap GTH_FO_CH_*_OUT_HUB_CMP # from the DC Blocking Cap GTH_FO_CH_*_OUT_HUB_DIR # to the FPGA MGT Receiver Input Recall: that the outputs that exit the West edge of the MGT Fanout will be special cases because there is a different set of bends in these traces. These are MGT FO Ch 1, 9, ... SE Quadrant: ROW: 43,44 43,44 45,46 45,46 Polarity: Straight Flipped Straigth Flipped MGT FO Ch: 11 19 12 20 Driver Side: Top Top Bot Bot wrt SE Corner: Away Towards Towards Away DIR OCP Length: 2.33 2.33 2.71 2.71 DIR OUT Length: 111.90 95.51 115.32 102.96 DIR Total Length: 114.23 97.84 118.03 105.67 CMP OCP Length: 2.71 2.71 2.33 2.33 CMP OUT Length: 109.84 95.79 115.07 104.99 CMP Total Length: 112.55 98.50 117.40 107.32 DIR - CMP Delta: + 1.68 - 0.66 + 0.63 - 1.65 The Shorter Is: CMP DIR CMP DIR Final Choice: - This This - SW Quadrant: ROW: 43,44 43,44 45,46 45,46 Polarity: Straight Flipped Straigth Flipped MGT FO Ch: 3 7 4 8 Driver Side: Top Top Bot Bot wrt SW Corner: Towards Away Away Towards DIR OCP Length: 2.33 2.33 2.71 2.71 DIR OUT Length: 126.29 153.77 131.54 162.22 DIR Total Length: 128.62 156.10 134.25 164.93 CMP OCP Length: 2.71 2.71 2.33 2.33 CMP OUT Length: 124.24 154.05 131.29 164.25 CMP Total Length: 126.95 156.76 133.62 166.58 DIR - CMP Delta: + 1.67 - 0.66 + 0.63 - 1.65 The Shorter Is: CMP DIR CMP DIR Final Choice: - This This - So the South Side Design will be: For SE Quadrant (for Quads: 127, 128, 129, 130, part of 131, and 132): Rows 43/44 Top Side Driver: Flip the Polarity Lengthen DIR Side Rows 43/44 Bot Side Driver: does not exist in the current mapping Rows 45/46 Top Side Driver: does not exist in the current mapping Rows 45/46 Bot Side Driver: Straight Polarity Lengthen CMP side For SW Quadrant (for Quads: 124, 125, and 126): Rows 43/44 Top Side Driver: Flip the Polarity Lengthen DIR Side Rows 43/44 Bot Side Driver: does not exist in the current mapping Rows 45/46 Top Side Driver: does not exist in the current mapping Rows 45/46 Bot Side Driver: Straight Polarity Lengthen CMP side Recall: that the standard serpentine for horizontal or vertical trace pairs adds 0.234 mm of trace length per increment. Thus in the cases above with a match error of about 0.65 mm we want to add two serpentine increments to the shorter trace.. FPGA Geometry Work on Rev. 2 of the FPGA Geometry so that it now builds BGA SMD Pads only for the MGT Receiver pins in Rows: 1/2 and 45/46. These pin numbers are held in a file so that Pad only pin/pad stacks are automatically placed at these locations when the geometry is built. Status MGT Routing Study Path: comps 2651 rev 967 nets 3763 rev 475_Dur connections 7133 finished 2845 rev 255_Dur unfinished 306 guides 3982 Status Main Path: comps 2651 rev 967 nets 3763 rev 474 connections 7133 finished 2805 rev 251_real unfinished 314 guides 4014 ------------------------------------------------------------------------ DATE: 26-July-2016 Topic(s): MGT Receiver Connections, 40.08 MHz Clock to Backplane My current setup of MGT Receiver connections has been stable since about mid April - over 3 months. The documents that describe the Hub's MGT Receiver mapping are: Drawings #22 and #23 hub_0_ab_FEX_MGT_fanout_map.txt hub_0_ab_fpga_mgt_transceiver_usage.txt gth_fanout_to_hub_fpga_nets gth_fanout_to_hub_fpga_nets_straight_order Today the decision was taken to shift the whole set of 80 connections CCW by one receiver. The possibly big advantage of this is that it removes the issue of splitting FEX_9 between Bank 133 GTY Receiver and Bank 233 GTH Receivers. With the new mapping all data lanes from a given source (typically a FEX card) will all be received by either all GTY or all GTH Receivers. No data source will be split across GTY and GTH Receives. The significant disadvantage is that we almost certainly loose one of the 4 MiniPOD Receiver channels becacuse of the now almost impossible route that this 4th MiniPOD Receiver will take to reach its new MGT Receiver. In the new mapping 3 of the MiniPOD Receivers will still connect to Bank 224 GTH Receivers and the 4th MiniPOD Receiver with the impossible route will connect to a Bank 124 GTY Receiver. I'm also looking for a way to move the "Combined Data from the Other Hub" MGT Receiver connection but this requires some kind of cross over or route through the MGT Fanout. I also need to redo the FPGA Geometry to dump the extended perimeter dog-bones on the perimeter MGT pins. The 40.08 MHz LHC Clock Fanout to the Backplane is routed with a pure top side L1 route. Status: comps 2648 rev 964 nets 3763 rev 468 connections 7135 finished 2793 rev 242 unfinished 292 guides 4050 ------------------------------------------------------------------------ DATE: 25-July-2016 Topic(s): Meeting about Amps and Links, Uniform QFN Geometries, Un-Connected Pins Meeting with Pawel, Wade, Yuri, and Brian. Pawel reports that Xilinx now agrees that there is a problem with the current monitor readout values that come from their VCU-108 board through the path: 4 term resistors, FPGA SysMon, "system controller thing" blob of software, JTAG connected PC, blob of software. Pawel reports that Xilinx says we should use the numbers from their Power Estimator in Vivado. Pawel will work up Vivado Power Estimator numbers for the actual running Hub configuration by mid week and we may compare these numbers to Philippe's. Asked for definitive final summary write up. So for now the decision is to use 20 Amps for MGT AVCC and AVTT. Implementation of this will start immediately. QTH, QTY, Aurora, ... has been passed to Ian. Looking at using same setup as front-end to L1Calo. This weekend's work was to start "harmonizing" all of the QFN geometries and other Thermal Pad geometries in the design. They are all being moved to the new rational one file format with the Thermal Pad in the body of the geometry and not associated with a Thermal Via pin/pad stack definition. A point of this work is to make a uniform set of geometries that will then need to be uniformly modified once the bare board house tells us what they want for plugging the Thermal Vias. This set of Geometries includes: NB7VQ14M QFN-16 top and QFN-16 bot CDCLVD1204 QFN-16 MC100LVEP111 QFN-32 CDCLVD1216 QFN-48 KSZ9031RNX QFN-48 BCM53128 Switch_256 For a given QFN package there appears to be a lot of variability in what the various manufacturers and IPC recommend. Worked on the un-connected pin list in the Mentor design. It started at 39 or something like that. Using Philippe's tool it is now down to 25 and they are all understood/expected, i.e. J2 has 4, J3 has 20, MegArray S1 has 1. ------------------------------------------------------------------------ DATE: 22-July-2016 Topic(s): Meeting on Thursday, Clock Generation & Distribution ReWork Wade, Pawel, Brian, Philippe and I had a long meeting on Thursday morning to discuss MGT Vcc and Vtt supply current and the arrangement of FEX Aurora Lanes to Hub MGT Receivers. No decisions yet. Another meeting next week. I remain concerned that we not proven that GTH and GTY can be used interchangeably in a multi-Lane Aurora setup. Reworked the Clock Generation and Distribution so that the Hub can turn off the 40.08 MHz Clock to the 12 FEX cards and to the Other Hub. The intent is that only the Hub that receives the FELIX TTC Optical signal will drive the Backplane Clock signal and that the Other hub will not drive the backplane clock lines that it is connected to. There is a new set of Clock Drawings. Status: comps 2648 rev 951 nets 3752 rev 461 connections 7134 finished 2759 rev 239 unfinished 293 guides 4082 ------------------------------------------------------------------------ DATE: 15-July-2016 Topic(s): Power distribution rework with a new set of Area Fills, Release the RFP for the Hub, Wed Philippe, Brian, Dan Switch & IPMC EEPROM meeting, Swap BULK_3V3 20A to 12A With the power outage on July 8th and 9th I made a lot of work on the Area Fills for power distribution. This is now all basically new and back in the design. See the hub_0_ab_power_distribution_strategy.txt file. The basic changes are: The power distribution use of Signal_5 and Signal_6 have been flipped for a better fit. The BULK_1V8 fill under the FPGA comes in only as a finger. It comes in from the West. This gets us back to 4 layers to run FEX traces from the MGT Fanout into the East side of the FPGA. The RFP for the Hub Assembly was on the street by 13:30 Tuesday afternoon July 12th. Wednesday meeting with Philippe and Brian. Reviewed Philippe's study of the Switch Chips. Took the decision to add the EN_EEE jumper on pin 38 to the design. This jumper has now been added and the plan is to install it by default at the assembly house, i.e. to by default disable the EEE feature. Philippe also reported about looking at the Broadcom program for generating the Switch EEPROM contents. This is starting to look rational. Still un-known what if any we need to put into the Switch EEPROM. The hoped for Switch operation is: wake up from the EEPROM and then use MDIO to access the 8x Phys in the Switch and hope that that gives all of the monitoring we require to understand any operational problems. Talked more about the IPMC EEPROM and what I *think* it does. Brian is going to look at it. A little trace work to clean up some obvious things that are required to fit with the new Area Fills, e.g. moving what layer traces are on and connecting the West most RJ Connector LED Anodes with trace and not with fill. Kind of as part of the power distribution Area Fill rework I have swapped the BULK_3V3 DCDC Converter, removing the 20 Amp module that had been in the design and putting in a 12 Amp module. The expected draw is in the range of 4 or 5 Amps on BULK_3V3. Status: comps 2635 rev 937 nets 3736 rev 453 connections 7107 finished 2724 rev 237 unfinished 293 guides 4090 ------------------------------------------------------------------------ DATE: 8-July-2016 Topic(s): Working on Fills, Video Meeting with Ed to Review the ROD-Hub The Area Fills for the various power buses on the Hub Module are not well layed out. I'm working on trying to make a rational set of assignments of power bus fills to PCB layers. There are a lot of requirements and constrains in this and so far I do not have a clean layout for the area fills. I do have Mentor making un-painted fills from a script. I think it will be possible to script the whole fill generation process. I did some clean up of traces in the area of the front panel LEDs. Part ordering continues without problems. Note that traces rev 236 is really a copy of traces 233 from the 5th. On Friday the 8th we had a video meeting with Ed, Wade, Brian, and Philippe to review the ROD-Hub compatibility. I have edited the following file to indicate the action items from this meeting for me: hub_0_ab_non-MGT_ROD-Hub_connections.txt Sensor I2C Bus section - add notes about: - The Sensor I2C bus may not work at all when some section of it is not powered up. - This may not be a problem during normal power up just so long as once both ROD and Hub are fully powered that the IPMC then starts to provide good monitoring data to DCS. - If there is a problem on the ROD-Hub Sensor I2C bus (e.g. lines clamped low) it would be good if the IPMC could report that to DCS vs just sending junk data or no data to DCS. - The Linear Technology I2C bus translators/buffers may automatically allow most of the ROD-Hub Sensor I2C bus to keep operating when just one section of it is clamped low. - It may be useful to run the Ready signals from the I2C bus translators/buffers back to the Hub FPGA. ROD Ethernet Connection section - added: The Hub design must confirm that it correctly implements the polarity of the Ethernet signals coming from the ROD. Jub should match Host Rev 2. Spare Unused ROD-Hub HP IO Signals - changed/added: We have a convention for who will drive and who will receive these spare signals when they are not used. When not used they will be setup as LVDS signals and the Hub will drive and the ROD will receive. I forgot to ask in this meeting about pin B27 in the S1 MegArray connector from ROD labeled "SMBA". I do not know what I can do with this Alert signal. I have forgotten to ask about this pin in the past and I need to find out about it. Status: comps 2628 rev 928 nets 3735 rev 449 connections 7099 finished 2711 rev 236 unfinished 296 guides 4092 ------------------------------------------------------------------------ DATE: 1-July-2016 Topic(s): RFQ technical documents on web The technical documents for the Hub RFQ are finally on the web. Parts purchasing continues and is looking OK so far. comps 2628 rev 927 nets 3735 rev 448 connections 7087 finished 2700 rev 231 unfinished 297 guides 4090 ------------------------------------------------------------------------ DATE: 24-June-2016 Topic(s): RFQ Technical Data Generation Work on the RFQ documents included generation of the X,Y placement data and splitting SMD parts into Top and Bot lists and counts. I want to do this in some more or less automatic way as Hub is still at the point where things are changing, i.e. it's clear that these are not final lists and tables. Scrubbed some more on the drill files. Parts ordering is back fully underway. Lots of other clean up and making things real, e.g. ROD mount drill holes/pins. As with CMX the bulk of the Hub components are SMD, 99.5%. Hub has about 24% more SMD components than CMX and about 43% more SMD component types. Status: comps 2628 rev 915 nets 3735 rev 446 connections 7087 finished 2700 rev 231 unfinished 297 guides 4090 ------------------------------------------------------------------------ DATE: 22-June-2016 Topic(s): Some real numbers for the Hub Assembly work The following draft files for getting bids are about ready: bill_of_materials_cleaned_22jun16.txt bill_of_materials_inventory_22jun16.txt hub_0_component_descriptions.txt There is a total of about 2227 components that the Assembly House will mount on the cards. All of them are SMD except for: a total of 3 solder-in THD components a total of 9 press-in THD components In total there are 103 component types that the Assembly House will need to work with. 97 of these component types are SMD 3 component types are solder-in THD 3 component types are press-in THD MSU Final Assembly will need to install about 45 electrical components. These are mostly: EEPROMS, RCs for Loop Tune, Rs for output voltage set, and Rs for I2C Address set. MSU Final Assembly will need to install about 9 major mechanical components: front panel, 2x fp brackets, fpga heatsink, 2x minipod heatsink, cover plate, and 2x mid-board optical connectors. There will be a lot of small hardware items used to mount these major mechanical components and some additional hardware for the ROD, e.g. standoffs. ------------------------------------------------------------------------ DATE: 17-June-2016 Topic(s): RFQ Technical Data Generation The bulk of the work this week had to do with generating the technical data for the Hub Module Assembly RFQ. Worked on the Hub fabrication drawing including internal corners, generation of drill data (now done with a script), generation of Gerber data (now done with script), generation of BOM files (now done with a script). A lot of work done sorting out components into: not-a-part, not installed at assembly house, and normal assembly house component. Status at end of week: comps 2628 rev 909 nets 3735 rev 445 connections 7087 finished 2700 rev 231 unfinished 297 guides 4090 ------------------------------------------------------------------------ DATE: 14:16-June-2016 Topic(s): Components that are Not in the BOM file. There are at least two classes of components that will not appear in the BOM file for the Hub Module: - Geometries for which all instances of components that use that Geometry are excluded from the BOM, e.g. differential via "component". - Individual instances of a component that are excluded from the BOM file, e.g. a jumper that is not installed. The other way to think abou this is that in the design there are some components that are not real parts that need to be assembled, e.g. Diff_Via_Pair and EDS_Strip and in the design there are some components that are real electrical components but that we choose not to have installed at the assembly house, e.g. not installed option jumpers and one of a kind single placement components. The following Geometries have had the attribute "Component_Not_in_BOM" added to them so that no instances of components that use these Geometries will ever appear in the BOM file: diff_pair_through diff_pair_thru_1g diff_pair_thru_1mm diff_pair_thru_3p ESD_Strip Rod_Silk Silk_Only_MiniPOD Silk_Only_FFG1927 AKA_1MM20 x1y1_power_via_array x3y1_power_via_array x3y3_power_via_array x4y2_power_via_array x2y2_power_via_array x3y2_power_via_array x4y1_power_via_array x4y3_power_via_array MPO_OPTICAL_CONN res_0603_1sb res_0805_1sb res_1206_1sb cap_0805_1sb soic_8_no_bom ATCA_Guide_Pin_Receptacle wrap_1mm1 wrap_3mm0 LEMO_Conn A big point of pulling all instances of these out of the BOM is that doing so provides a continuous index in BOM file of "Company Part Numbers" that actually exist on the card. Thus we can have a BOM file were both we and the assembly house need to take action on every listed item. Many individual components also need to be removed from the BOM. Examples of these components are jumpers that we do not want installed by the assembly house, and one of a kind components that we do not want the assembly house to worry about yet another spool of parts for just one placement. - Not Installed JTAG Jumper: JMP2 - Not Installed ROD Power Control Jumper: JMP4 - Not Installed IPMC Payload Enable Jumper: JMP6 - Not Installed LED Series Resistors: R255 R256 - Not Installed Configuration Jumpers: R1811 R1814 R1815 R1821 R1823 R1825 - Not Installed Phys Chip Jumpers: Adrs: R1901 R1903 R1905 (R1951 R1953 R1955) Mode: R1910 R1912 (R1960 R1962) - Not Installed Switch Chip Jumpers: Switch A: R2004 R2005 R2008 R2010 Switch B: R2104 R2105 R2108 R2110 Switch C: R2204 R2205 R2208 R2210 Note that all of these Not Installed (but real components) are setup with a "one solder blob" geometry and that this one-solder-blob geometry includes the attribute Component_Not_in_BOM. In this way the individual instances of Not Installed components are removed from the BOM file. We also do not want the Assembly House to install the 3x Switch EEPROMS or the IPMC FRU&SDR EEPROM. Note also that in the comps files, these individual instances of Not Installed components are given the acutal Company Part Number that should be used if this component ever needs to be installed and they are given a Symbol Name of "Not_Installed" which indicates to the reader that this component is normally Not Installed. There is an additional problem in generating the Bill of Materials - the BOM generator sorts on both the Company Part Number AND on the Geometry (even if the Geometry is not being displayed in the BOM Report). This is only a problem because in a number of places I'm using the same electrical part with different Geometries. The following table lists the Company Part Numbers that are used with multiple Geometries in the Hub design: Company Part No. Geometries -------------------- ---------------------------------------- Cap_100_nFd_0201 cap_0201 cap_0201_top cap_0201_bot Cap_10_uFd_25_V_1206 cap_1206 Cap_1206_THD Cap_22_uFd_Tant_V tant_d_plus_left Tant_D_THD_Plus_Bars Cap_47_nFd_0402 cap_0402 cap_0402_gth Conn_FCI_55714 minipod_receiver minipod_transmitter FCI_Conn_74221 MegArray_S1 MegArray_S2 IC_NB7VQ14M QFN_16 QFN_16_Side_2 LED_HSMR_C170_BLU led_quad_up_right led_quad_low_left LED_LGR971_GRN led_quad_plain led_quad_low_left LED_LYR976_YEL led_quad_plain led_quad_up_right TE_2065657-1 ATCA_Zone_2_Conn ATCA_Zone_2_Conn_no_9_10 The method for removing multiple instances of a given Company Part Number from the BOM, is that during BOM generation, have only one Geometry in the Components file for each Company Part Number. This special temporary Components file is make by a script that replaces Geometries as needed, i.e. as indicated by the table above. ------------------------------------------------------------------------ DATE: 10-June-2016 Topic(s): Monday and Tuesday Meetings, Routing work on Hub Monday meeting with Wade, Philippe, and Brian. Review some of the Hub power supply "features" and talk about inputs to Wade's talk, e.g. monitoring vs management of the power supplies. Notes to Wade: Brian about Hub power, Philippe about MGT power, Dan about IPMC. Brians first day. Tuesday meeting with Janice Croswhite from MSU Purchasing. Talk about best way to setup the assembly services purchase for the Hub build. Janice thinks there is no problem to start this early and is helpful in getting this order going. Some more work on the power supervision circuits and the ROD power control. Moved to 5 caps in the ramp circuit to get caps with the correct voltage range. Finally added the J3 Voltage Monitoring RC filter components for 10 supplies, i.e. including the SysMon Ref supply. Made a practice path "smoothing" high-speed traces in the Fanout cell itself. Made enough drawings and notes that this is now a canned process. A remaining issue in the Fanout is the tight cap to thermal via spacing and no place else to put this cap except on the back side with one foot in the thermal pad. As the goal now is to release an RFQ within the next week or two - all work switched to getting the technical data ready for that. While working on gerber plots, drill files, and the processes to generate then I've noticed things that needed to be fixed in various geom files - so a bunch of work has gone into them while these problems are fresh and obvious. There are two clear bare board issues: back drill vs blind via and how to handle the vias that are very near SMD pads or even in the thermal SMD pads for the various exposed pad components, e.g. Switch, Phys, Fanout. We need to pass this to the bare board house and talk about options for plugging vias to prevent solder flow into these vias. Note with Ed and David about IPMC and Monitoring. It sounds like our two level model of monitoring is correct. comps 2628 rev 875 nets 3735 rev 444 connections 7088 finished 2700 rev 228 unfinished 296 guides 4092 ------------------------------------------------------------------------ DATE: 3-June-2016 Topic(s): Routing Work on Hub, Friday Meeting Friday meeting with Wade and Philippe in Rm 2150. Brian will be here Monday so I need to think of more jobs for the pool of work for him. I'm working to setup a meeting with Jan at MSU Purchasing about the Hub Build. I have had email with Marc and Matt and he says that Jan will handle this order. The No_Conns were finally added to the IPMC mezzanine socket along with the check for 244 connections in the net list builder. Cleaned up and routed the power supply startup controller and supervision and the ROD Power Control all along the top edge of the card. Except for the long runs between sections I think that the front edge and top edge are now basically finished. The Switches and ATCA modules and such (everything below the FPGA) are all finished. More work on the issue of solder mask tenting. Now working to pull the tents off both sides of all via/pin holes. The current Goal is a minimum relief gap between the edge of the drill hole and the edge of the Solder Mask of 0.10 mm with 0.12 or 0.15 mm being better. It is prefered not to use too much relief as letting the Solder Mask come up and cover the outer part of the pad land is good. New thoughts and additions still to get into the design: RC filters and Voltage Monitor connections up to J3. Route Power Good signal to a FPGA Select I/O input. Add another crystal oscillator (non-LHC) locked. comps 2605 rev 869 nets 3725 rev 440 connections 7033 finished 2676 rev 226 unfinished 280 guides 4077 ------------------------------------------------------------------------ DATE: 31-May-2016 Topic(s): Un-Tenting SMD Comps and Vias Worked over the long weekend to un-tent the SMD (BGA) comps with vias and the routing vias. This got complicated as there are a lot of Geometries that need work and just about all of them need special consideration. Lots of reading to try to understand the issues. My understanding to date: - Tenting vs non-tenting changed when the world changed from the old dry film solder mask to the current LPI solder mask (Liquid Photo Imagible). - There are probably two separate entrapment problems: entraping a drop of liquid that blows apart the PCB during assembly when it is hot and entraping a small amount of some chemical that over time damages the electrical connection to the via (a long term reliability problem). - The typical entrapment problem today comes from the chemicals used to apply the surface finish which is done after the solder mask has been applied. - Beacuse it is a thin liquid, LPI solder mask does not guarantee that it will cover (tent) a given via. - The problem is not just tenting both sides of the via which risks trapping a drop of liquid within the via. - Tenting just one side also causes entrapment that can cause long term reliability problems. - If you need the vias covered then use "plugging" or "button printing" that is a separate processing step that is done after the solder mask and surface finish have been applied. - Vias Not Covered - This is the standard process in current printed circuit board fabrication. - With Vias Not Covered it is possible to have wicking of the solder paste into the via associated with a BGA pad. If you have a solder mask dam ( 0.1 mm wide minimum ) then this is not a concern during first pass assembly. It is a concern during rework as this narrow dam can be damaged during component removal. Now understanding more about tenting vs non-tenting I need to rework yet again a number of geometries. The general plan is the following: - Keep the solder maks back 0.1 mm from the drill hole, i.e. solder mask opening diameter is 0.2 mm greater than the drill hole diameter. Is this enough ? - Do allow the solder maks to cover the outer part of the via copper land, i.e. make the dam between the BGA pad and the via drill hole as rationally wide as possible. - The thermal vias in the QFN parts and the Switch chips must be a special case that I don't currently know how to handle. - There are lots of Geoms to study / fix including things like the via arrays and the high-speed differential via pairs with ground returns. - Need to understand how to handle keeping the via open for Blind vias. Can NOT have just one side of the via open and the other sided tented. Work over the weenend is probably all junk. If my CMX SN #0 card had ever been return from CERN (as was the agreed plan) then I could see how that quality bare board company handled redoing the tenting on CMX. During the dig into the tent vs un-tent issue I also leaned that I need to stop making painted gerber files for the area fills. I also need to look into delivering gerber in the X2 format. ------------------------------------------------------------------------ DATE: 27-May-2016 Topic(s): Routing work on Hub Routing work mostly in the support circuit: ROD and Hub LED translator/drivers, Sensor I2C bus buffers, JTAG translator/ buffers, ATCA Entry and Iso 12V. The IPMC is now all connected except for its 8 Crate Hardware Address output lines. Gave up having any chance at all to get the power traces through the "pinch". Have put in discrete wire vias for: IPMC_3V3, CNST_5V0, 2x Hold-Up capacitor wiring, and 2x Iso_12V as a suplement to area fills to carry Iso_12V through the pinch. Switched to using an AKA component to remote sense the Iso_12V away from the module. Pulled the "spare" Switch chip bypass caps out of the design. Worked to un-tent all SMD comps that use vias and all other vias. Still need to work on: MiniPOD, Config PROM, and Ethernet Magnetics and many others. comps 2594 rev 851 nets 3570 rev 427 connections 6993 finished 2510 rev 215 unfinished 254 guides 4229 ------------------------------------------------------------------------ DATE: 20-May-2016 Topic(s): Meeting on Monday with Pawel et al, Notes from Ian about schedule, help from Ed, and "Dual Sourcing", Work on Hub Routing. Meeting on Monday with Wade, Philippe, and Pawel about power supply current estimates. Still factors of two floating around between measurements and the Vivado estimator. Pawel will work on making a MGT setup for his demo board that will allow us to estimate the actual Hub usage. Before this meeting I send out a note with background on the 4 FPGA/FW topics that are guiding Hug hardware design: power, MGT Receivers vs Aurora Lanes, MAC to Phys I/O Bank pins, and CMX Eye Pattern. Notes with Ian about schedule, help from Ed, and "dual-sourcing". I still need to send Ian a reply about our bare PCB plans. Routing work this week included: moving the ROD by 6 mm North (it is still 2 mm South of the upper keep-out), and moved all of the Hub components that are bounded by the ROD North with it (e.g. DCDC 1, 2, 3 and 4), connected all of the Bulk DCDC Converter Input Filter components by making THD version of the D Case Tant and the 1206 ceramic, routed Zone 1 power through the fuses to the Power Entry Module, routed DCDC5 Swch converter, and Power Entry to Iso_12V, and the Iso12V module. All of this power wiring is more or less in final form (multiple rivets and such) but it still needs a final doubling and tripling or fills to get enough copper for the current flows. Routing started on the control/monitor lines for the two ATAC Modules and the Switch DCDC5 converter. The power buses in the Vertical Mat through the pinch look like a real problem, i.e. not enough space for heavy copper for the Iso_12V, IPMC_3V3, and CNST_5V power buses. I do not know the load on IPMC_3V3 but the entry module can make 3.5 Amps of this rail with a shutdown above 7 Amps. The load on the CNST_5V0 is low (10 mA or something like that) and the power entry module can make 150 mA with shut down at 400 mA. I'm looking for possible places to put vias to hand wire these buses. I would just dump the Hold-Up capacitors and the 2 additional power buses required for them but I don't know if the Power Entry Module would be happy without some version of these capacitors installed. There are a total of 5 power buses that need to go through the pinch. Tried to remove the component outlines for the SilkScreen only ROD components (silk_only_minipod, silk_only_virtex_7, ROD outline and mounting screws) but this did not work. Librarian is happy with a component that does not have a component outpline but Layout requires 3 or more vertexes in the comp outline layer. comps 2656 rev 807 nets 3570 rev 417 connections 7046 finished 2235 rev 191 unfinished 233 guides 4578 ------------------------------------------------------------------------ DATE: 13-May-2016 Topic(s): Work on routing in the Vertical Trace Mat, Meeting on Thursday afternoon Routed all of the Switch Chip LEDs in the Vertical Trace Mat and also almost finished the 8 Hardware Address lines and the two IPMB buses from the Zone 1 connector. Working on the Zone 1 traces required some initial work on the Zone 1 power connections to the 6 fuses. They could have made a more rational pinout of the Zone 1 power pins. I have concern about the long IPMB bus routes from Zone 1 up to near the top of the IPMC socket. To the extent possible I've kept the serial clocks lines spaced away from the serial data lines but things are tight going through the pinch. Tried to understand how the Shelf Manager and the IPMC actually make use of the two IPMB buses. I believe that both are in use during normal conditions so they received equal concern and spacings during routing. Wade was back from two weeks of bump meetins and we had a meeting in 2150 on Thrsday afternoon. The main point of that meeting is who is doing what next and what needs to happen to keep routing moving and what needs to happen so that we are not hung up when we have HW to work with. I need to send out a 4 points FW note and in mid June make another MSU Purchasing visit. comps 2656 rev 785 nets 3570 rev 414 connections 7094 finished 2088 rev 173 unfinished 236 guides 4770 ------------------------------------------------------------------------ DATE: 6-May-2016 Topic(s): Work on Phys Chip Routing and routing of the Vertical Trace Mat on the West side of the Phys Chips Both Phys Chip Blocks (the Phys chip with about 45 RC comps) are now fully routed including their Ethernet connection and the escapes for their LED connections. They are tightly packed and their layout looks good. The mapping of their connection into Bank 68 of the FPGA is laid out in detail and documented in circuit drawing #45. This mapping can route into the FPGA on just 3 pcb layers with the clocks landing on required pins and all of the high-speed rgmii traces having a short no criss-cross path free of extra vias. My concern about the vertical mat of traces that must route North-South just West of the Phys Chips grew this week. There is not other place for these traces. Some of them are just junk LED control signals but some are clocks and differential Ethernet traces that need a clean route and a quiet environment. There are about 133 signals in this Vertical Trace Mat. This must route North-South right through the front panel RJ45s and their magnetics. I must push this so that I know how wide this mat is before doing any more FPGA work. If this Vertical Trace Mat grows too wide then it will push the Config Flash and the Phys Chips East that that may/will change the plans for the optimum FPGA location. Details of the Vertical Trace Mat and the routing plans for it are in the trace routing strategy document. Work on the Vertical Trace Mat required a re-think of the front panel LEDs. For the bulk of these I've switched from putting the LED series resistor between the LED Anode and Vcc to putting the series resistor in the run to the LED cathode control signal and just tying the Anode directly to Vcc. This allowed me to move all of the Switch Chip LED series resistors to locations under the ATCA power modules (a location that is good for nothing else) and makes more space for the VTM and the other IPMC components. Routing of that has now started. The already routed Magnetics to RJ45 and Base IF under Zone 1 traces have to change layers for this new scheme. IPMC was moved 5 mm East, i.e. one half of the ROD move of a couple of weeks ago. The Quad LED geom was check and mistakes corrected. comps 2656 rev 765 nets 3570 rev 413 connections 7062 finished 1906 rev 145 unfinished 292 guides 4864 ------------------------------------------------------------------------ DATE: 29-Apr-2016 Topic(s): Working on FEX Data Fanout to Hub FPGA routing, Phys chip and Ethernet routing, Thursday meeting with Ed and Ian The current FEX to Hub mapping has been put into the hub_0_ab_FEX_MGT_fanout_map.txt file. This files has always been correct for the feed to the ROD but I have not been keeping it up to date for the feed to the Hub's FPGA. I did that work this week - even though I know that it will change as the layout is done. The files that show the FEX Data to Hub FPGA Mapping are: hub_0_ab_FEX_MGT_fanout_map.txt hub_0_ab_fpga_mgt_transceiver_usage.txt 22_gty_banks_11x_assignments.pdf 23_gth_banks_21x_assignments.pdf Net_Lists/Build_GTH_Readout_Nets/gth_fanout_to_hub_fpga_nets The 40 or 50 RCL components around each of the Phys chips U21 and U22 have been compacted and routed to these chips. The ethernet paths are planned out and I'm working to re-map their rgmii connections to Bank 68 to make escape and routing compact and via free to give more space for FPGA bypass and to find some place to put the 40.08 MHz PLL. I flipped the two halves of RJ1 and TRNS1 between ROD and IPMC. This was the usual mess of working with 7 files to get all of the documentation and LEDs correctly re-connected and described. This gives slightly better routing for these two ethernet circuits. On Thrusday we had a meeting with Ian and Ed about planning for the initial ROD + Hub tests which I think will be mostly IBERT tests and are now advertized for October. I can't prove that it will not happen by then. Sent note to Wade with more testing details. Must release the new rgmii FPGA Phys map and ask folks to make certain that the firmware and IP can work with those connections. Asked for eye diagram IBERT test for CMX so I can see how clean that FPGA escape looks in an eye diagram, e.g. would it work 1.5x faster ? and so that FOX studies can have eye diagrams, e.g. to compare attenuating to errors vs cable length multi-moding to errors. comps 2656 rev 743 nets 3570 rev 399 connections 7029 finished 1696 rev 128 unfinished 217 guides 5116 ------------------------------------------------------------------------ DATE: 22-Apr-2016 Topic(s): Working on FEX Data Fanout to Hub FPGA routing, Phys chip routing, and Config Flash routing. Early in the week I did another major remapping of the MGT Transceivers on the Hub's FPGA. I finally realized that driving the Combined Data lines from MGT Transmitter outputs packed near the East edge of the FPGA was not gaining me anything and that it required reaching the 4th ring of differential pairs. Spreading out the MGT connections to the Combined Data, Hub Readout, and Transmitter MiniPOD so that mostly only 3rd ring connections are used held. At the same time the FEX Data Fanout connections were remapped again. Most of the problem with these is in Quads 131 and 231. I started an "escape" sub-directory in the Xilinx web documentation. The hope is that the unused Banks 70 and 72 may provide a better path to the remote 4th ring inputs to Quads 131 and 231. In any case the FEX inputs are very distributed across Quads. Note sent to Pawel and all about FEX Data inputs on the Hub's FPGA. Need to organize and start the 3rd revision of the FPGA Geometry to drop the long dog bones at the perimeter of the MGT sides. All documentation matches the current MGT mapping except for hub_0_ab_FEX_MGT_fanout_map.txt which I will fix today. Placement for the Clock Generation again but it is still in the way. The 320.64 MHz PLL *may* be able to fit in up on the North side of its distribution. Real geometries are now in for the Phys chips and for the Config Flash. Serious placment work on both of these. Rotating U22 by 90 deg ccw looked like it would help but its connection to Switch "B" is still not direct and the resistor connections to its rgmii lines do not look good. Sliding U22 lines things up better but just make an unusable hole to its West. Swapping ports #4 and #5 on Switch "B" will help with the routing to U22 but I'm not certain that it leaves and escape for the connection up to the magnetics for the connection to the Other Hub. 4 of the 5 supply filter choles in each Phys chrcuit have been switched from 1206 to 0603 to help a little with space. I think that the DC resistance is still OK. Rotating the Config Flash by 180 deg may help its connections. A big question is can I gain anything by swapping the BULK_1V8 and BULK_3V3 fills between Signal layers 5 and 6. This may help, i.e. eliminate the need for special Switch 3V3 fills and may make for better 3V3 connection to its converter. This would leave the only BULK_1V8 connection being over the top of the MegArrays but this is better than the current setup. I had gone ahead a swapped the location of DCDC Converters for BULK_1V8 and BULK_3V3 and I will need to undo that. DCDC9 the BULK_2V5 has been moved South of the MiniPODs and the rest of the converters above the FPGA have been moved West to get them off of the FEX feed to ROD traces. This now looks almost OK. None of the fills have been adjusted to match this new setup but I hope that there is still connectivity. The three sets of FPGA bypass components for its MGT rails are now in a rational order. No work so far on the FPGAs CORE or 1V8 and 3V3 bypass. They are still sitting in blobs. The ATCA Shelf arrived on Tuesday. I have studied its backplane connectors and such but still need to probe the UpDate channel. Both eFEX and ROD used dual track routing of the differential pairs for their MGT connections. Received a note from Pawel about current draw on his demo board. I think that he is just using a small multi meter across the on board 4 terminal resistors and is not acutally using the system monitor readout of current per supply on the card. comps 2656 rev 708 nets 3570 rev 394 connections 7000 finished 1583 rev 112 unfinished 189 guides 5228 ------------------------------------------------------------------------ DATE: 15-Apr-2016 Topic(s): Work on placement and getting the FPGA ready to route. Moved the ROD 10 mm East. Changed one of the Signal layers used to route the Backplane to FEX Fanout and the FEX Fanout to ROD MegArray traces so that the bottom surface Signal layer if fully free to carry the Combined data runs to the Backplane. This required major rework of the FEX Fanout with its Differential Pair Via components. The top surface signal layer carries the Clock runs to the Backplane. Moved the coupling caps for both the Combined Data and for these Clocks. The Clock coupling capacitors are now East of the FEX Fanout and should not require any vias. Completely rearranged Clock Generation and Distribution. Now only the two Clock Distribution chips and their associated components are up directly East of the FPGA. Swapped the locations of the two MiniPODs. Moved the Configuration Flash down. Backplane signal issues are the two odd ball signals: Clock from the Other Hub and Combined Data from the Other Hub. Major rework of all of the MGT connections to make things a bit more rational for routing. Need to push on full geometries for: Flash, Phys, 48.08 MHz Clock Distribution, and 320.64 MHz Clock Distribution. Need to push on getting the Phys and their associated components compacted. Started more work to study the vcu110 demo board PCB design. comps 2656 rev 691 nets 3570 rev 390 connections 7008 finished 1583 rev 109 unfinished 197 guides 5228 ------------------------------------------------------------------------ DATE: 8-Apr-2016 Topic(s): Meeting with Wade on Mon or Tues, Finish the Switch for now, starting Backplane Combined Data and Clocks, also the real Geometry for Phy and Flash I have finished the routing of the Switch for now. It is pretty well cleaned up and complete. As things are sorted out one could still pack in a few more bypass caps or pads for jumpers that I currently do not think that we will need. Everything is routed including the front panel RJ45s. The LEDs and the 4 lines between the Swtiches and FPGA are still to do but routes have been left open for this. The 25 MHz Ethernet Clock and its Fanout are routed with runs to Phys and FPGA still to do. --> Still need to bring the drawing of the Switch Chips power distribution system up to data to match the actual routing, i.e. drawing #18. Currently working on the full Geometries for the Configuration Flash Memory and for the Phys chips. Also working on the Backplane connections to the Coupling Caps for the Combined Data and for the Clock runs to the Fex cards and Other Hub. Had a meeting on Monday or Tuesday afternoon with Wade. Concern about the accuracy of the Xilinx power estimation. He has asked Pawel to work on this: understand efex and compare Pawel's Ultra demo board to what the power estimator says. There is a possible new person to start working for HEP. May be here in May. Four possible initial tasks include: data in and programing of the Switch EEPROMs, data in and programming for the IPMC EEPROM, setup PC system to control/monitor the 7 I2C Bus visible DCDC converters, make a second serious look at the 33 jumpers on each Switch chip. comps 2629 rev 665 nets 3570 rev 377 connections 6934 finished 1583 rev 101 unfinished 197 guides 5154 ------------------------------------------------------------------------ DATE: 1-Apr-2016 Topic(s): Routing Base Interface Switch Working on routing all of the traces to Switches "A" and "C". This is being pushed as tight as rational to save the most space possible for the other functions. The swapping for ports on Switches "A" and "C" tentatively looks finished. All of the documents related to these Switch ports and their LEDs and such is back up to date. Front panel LED are back matching the actual Switch port connections. As expected the number and type of bypass capacitors has moved around a bit during the routing of Switches "A" and "C". The documents about this are not currently up to date. So far the switch routing looks rational and the escapes for LED, Zone 1, and the RJ45 traces looks more or less OK. The two ATCA power modules and their RC comps have been moved East and spread out some (e.g. 8 mm). So far I have no space for jumper pads for the jumpers that I don't *think* that we need to install. Status at close of business on Friday with the "A" and "C" Switches basically routed: comps 2624 rev 629 nets 3570 rev 371 connections 6909 finished 1113 rev 76 unfinished 158 guides 5638 ------------------------------------------------------------------------ DATE: 25-Mar-2016 Topic(s): Routing Base Interface Switch to the Backplane On Tuesday the 22nd I finally fixed the position of Switch "C" and started routing through the magnetics to J23 and J24 - saving traces. On Thursday problems developed in the escape path to the lower edge of the Switch and as part of the fix I was able to move U33 another 2 mm South and 1 mm East. Rip out all of the Switch to Magnetics routing. To make this change I need to re-map the Switch Port to Magnetics links but not the Magnetics to P23/P24 links. For now edit JUST the Switch to backplane netlist which means that once the dust has settled I still need to edit or at least check: led_connection_nets switch_chips_to_adf_conn_nets hub_0_ab_ethernet_line_circuits.txt hub_0_ab_led_front_panel.txt hub_0_ab_switch_ethernet_base_if.txt 04_hub_ethernet_switch_details.pdf 44_hub_fp_connectors_and_cables.pdf Status at close of business on Friday with 6 of 8 Switch "C" ports tentatively routed: comps 2621 rev 598 nets 3570 rev 365 connections 6880 finished 558 rev 49 unfinished 83 guides 6239 ------------------------------------------------------------------------ DATE: 18-Mar-2016 Topic(s): Hub and FW Meetings, Switch Routing Friday March 11th we had a firmware meeting with the folks from Indiana to start sketching out the blocks that can be common with Hub and the (or all) other L1 components. Using Auora for the Combined Data link from Hub to ROD and FEXs *may* have timing uncertainty implications. There will not be regular Friday firmware meetings. Monday March 14th normal global MSU Hub meeting. Pawel now has some per rail MGT power requirement numbers. Working on Switch routing. For the Magnetics to backplane routing I have dropped the unused bottom two chicklets in P24 which would carry the Base Interface to the 15th and 16th slots. I have also dropped the unused backplane Ethernet, Rign Voltage, Metallic Test, and unused drill holes from the Zone 1 connector. The "No_Conn_" nets have been dropped to the removed pieces of P24 and Zone 1. This allows a fairly clean route from the magnetics to the backplane and keeps these traces away from the MGT FEX connections. The RC components under the Magnetics have all been redone to allow a clean route on the bottom layer only with only two vias to Ground per side. The routing paths for the signals in/out the magnetics are in. This is setup for all 10 dual Ethernet magnetics. Magnetics geometry now has built in vias on all 48 pins. All 100 or so RCl components under the Switch chips have been arranged for routing. The bulk of the bypass caps are packed under the Switch itself and remain in its relatively positioned component set. A few of these comps have been brought out for final placement. Details about the changes to the Switch RCL components are in the Switch "as built" file. The Switch Chip geometry now has its fancy Broadcom specified thermal pad with 72 thermal/ground vias, 56 Solder Mask windows for the thermal pad and rational perimeter pad layout. Talked with the new sales contact at Comtel and the Shelf order is back almost underway. comps 2622 rev 580 nets 3570 rev 359 6880 connections 361 finished ------------------------------------------------------------------------ DATE: 9-Mar-2016 Topic(s): Switch component/port and routing Some time ago the arrangement of the 3 switch chips was changed from an "L" to a straight line B - A - C. To allow routing without 10**9 trace criss-crosses this requires a new assignment of the Switch Ports to Customers Map. Basically all 24 Ports must change along with their LED connections to the front panel. Changing the Switch Ports to Customers Map involves editing the following 10 files and drawings: led_connection_nets switch_chips_no_conn_nets switch_chips_to_adf_conn_nets switch_chips_to_rj2_conn_nets switch_chips_to_rj3_conn_nets switch_chip_to_cap_coupled_nets hub_0_ab_ethernet_line_circuits.txt hub_0_ab_led_front_panel.txt hub_0_ab_switch_ethernet_base_if.txt 04_hub_ethernet_switch_details.pdf 44_hub_fp_connectors_and_cables.pdf As part of this the geometry for the Zone 1 connector was also modified to remove its non-existent JTAG pins and thus allow the Switch Chip Magnetics for the Base Interface to move closer to the backplane. Doing this dumps the 12 No_Conn_ nets to the non-existent backplane JTAG and the non-existant backplane ATCA Ring Voltage and Metallic Test. Still need to move all Switches East, add area fills for power under the switches, move coupling caps between B-A, try moving Enet Clock to the West side of Switch B. comps 2622 rev 561 nets 3586 rev 355 6883 connections 361 finished ------------------------------------------------------------------------ DATE: 7-Mar-2016 Topic(s): Hub Firmware Meeting, BNL and Stony Brook trip We had a Hub FW meeting on Monday the 7th with just the MSU people. The pure IBERT work is about finished and Yuri is working on understanding the GBT Felix TTC optical stuff. Last week Tuesday through Friday was a visit to BNL for ATCA and LArTPC discussions. BNL has made a number (6-8) of other ATCA cards besides the gFEX. Tang the gFEX engineer is working on the 3rd version. Dean's ATCA mother board will run in USA15 and handles just the trigger data feed to L1Calo. He started out working on the uTCA mizzanine card for it. ------------------------------------------------------------------------ DATE: 23-Feb-2016 Topic(s): Drawings and "as built" documents, Hub Firmware meeting, Xilinx docs, ATCA visits, next Hub PCB work Over the past two weeks or so all of the drawings and all of the "as built" documents have been worked on to make them current. It was known that there was much old and/or wrong information in the "as builts" but I also found many problems in the drawings. I don't think that there are any more lies in either the as builts or drawings but much more work will slowly contimue on both. On Monday the 22rd we had a Hub FW meeting with all Hub Team members in attendance. Pawel is working on IBERT designs for his demo board and then for the real Hub. The first interesting point will be the 320.64 MHz Logic Clock running transceivers on both pieces of Si. There is still a LVPECL issue with running this clock into Bank #71 that I need to look into and I need to talk to the Xilinx folks about multi SLR documentation. Next week is a Monday FW meeting with Ed and Indiana. Layers of overlap include: pulling clock and data from the Felix optical TCC signal, recovering Auora FEX data, IPBus registers and communications, format and receiving of the "Combined Data". Still a question of, does the ROD need the Hub's "Combined Data". Next week is BNL LArTPC meeting and ATCA visits to Stony Brook and to gFEX. The next Hub PCB work nees to be on the complicated geometries (switch, phys, pod, flash) and to straighten out the Switch Port maping so that routing of the Switch Port traces will fit with the new physical arrangement of the Switch chips - now all in one horizontal row. Will start by working on the 12 backplane to FEX BI Ethernet links. The issues are the Switch to Magnetics mapping and the Magnetics to Zone 2 connector mapping. Must un-tangle both and have a real layer use strategy. These nets are all in one file which may help or may be too much. The issues are criss-cross: of ports, criss-cross of the 4 lines within an Ethernet link, and criss-cross of signal polarity. As far as I know all 8 lanes within one magnetics module are equivalent so I can both swap and flip polarity as needed to get a rational layout of these 96 signals for routing. comps 2620 rev 559 nets 3598 rev 346 6879 connections 361 finished ------------------------------------------------------------------------ DATE: 10-Feb-2016 Topic(s): Work on Area Fills for the power distribution and on the As Built files, Hub Firmware Meeting today Have 38 Area Fills in the design. It's still not clear whether or not a jumper will be needed to connect any of the power distribution areas. Currently the CLK_2V5 is still not connected. The Hold_Up caps are not connected. Working on the power and clock files in the As Built documents. We had a Hub Firmware meeting today and Pawel presented how he will move forward starting with IBERT. Concern remains about fully understanding multi SLR parts vis-a-vis PCB layout and firmware. comps 2620 rev 556 nets 3598 rev 343 6879 connections 361 finished ------------------------------------------------------------------------ DATE: 3-Feb-2016 Topic(s): Hub Module Area Fills I need to start the work on Area Fills to make certain that the required power distribution is going to work out OK with the current component placements and with the current use of 4 stackup layers for power. All of the power distribution in the Hub Module must be done with area fills because all 4 of the stackup's power layers are multi function layers involving multipe power buses on a given stackup layer and on 2 of the stackup power layers we also need to run differential signal traces. Recall also that some sections of a given fill must be done at high resolution (e.g. under the BGAs) while other sections can can be done a lower resolution to keep the file size under control. The point for now is not to set the exact borders between fills and miter the corners but rather I need to prove that the layout will work at all. This whole area fill topic is complicated enough that it will need its own documentation file. For this card I want to try shell scripting the whole fill generation process instead of just bio-robot scripting as has been done in the past. For now setup the following 4 files as parts of the overall pcb geometry file set: fill_shapes_signal__5_nom_1v8.txt # L9 in the stackup # includes diff signals fill_shapes_signal_11_nom_core_and_avcc.txt # L11 in the stackup # for high current fill_shapes_signal_12_nom_core_and_avtt.txt # L12 in the stackup # for high current fill_shapes_signal__6_nom_3v3.txt # L14 in the stackup # includes diff signals ------------------------------------------------------------------------ DATE: 2-Feb-2016 Topic(s): Pre-Routing Work, Next Steps I have been moving around lots of blocks (e.g. BULK 1V8 and 3V3 supplies, MiniPODs) to make things more practical to route. All of the Select I/O Banks on the West side have been reworked to make things more practical to route. This means trying to get rid of all connections to the inner most rings and using escapes to the North and South from Banks: 84, 94, 68. Note that these N/S may interfere with placing bypass caps in these areas. Note that Bank 66 has been completely cleared to allow access to the deep rings in Bank 65 that are required for Configuration. I may need to pull out the Vcco power feed to Bank 66 to get wide enought routing channels. The current automated process for making the U1 geometry with just SMD pads for its single pin nets appears to work OK but some of the comment lines need to be cleaned up. Next Steps: Must bring the As-Built documents up to date very soon. Need to fix the obvious criss-crosses in the Switch Ports. Need to start the Area Fill boarders to prove that the power planes have a chance of working. comps 2620 rev 552 nets 3599 rev 342 6878 connections 361 finished ------------------------------------------------------------------------ DATE: 29-Jan-2016 Topic(s): FLVC2104 Geometry, Power Supply Placement, Front-Panel Mounting Finish moving around and rotating the power supplies for now. Pushed on the FPGA geometry so that it now has pad and via pin/pad stacks by quadrants and special further out via placement for just the outer most ring. The script to build this geometry pulls the single pin nets from the sorted netlist file and places just SMD pads for these device pins. The intent is to study the feasibility of placing bypass caps on the back of the FPGA using the areas of single pin nets for the pads for these caps and to place the vias to connect these bypass caps. The big concern is getting bypass caps on the East end of the FPGA_CORE supply finger. Work on the front-panel mechanical mounting and the holes required for this on the Hub PCB. The change in the connection count is due to the FPGA Ground pins now directly picking up the ground plane. comps 2610 rev 546 nets 3599 rev 337 6858 connections 361 finished ------------------------------------------------------------------------ DATE: 25-Jan-2016 Topic(s): 2nd FW Meeting, Power Supply Work Second of the weekly Firmware meetings with Yuri and Pawel. Discussed: MGT power, Clock setup on the Hub PCB, and what FW is needed when. Power supply work trying to rotate and make a near final placement for DCDC_6, DCDC_7, and DCDC_8. Placement conflicts with air-flow and big caps, etherent magnetics, and filter inductor. Break up the Bulk input filter into 3 sections as it should have been in the first place. Rotating the FAN_1V8 converter 90 deg does not help. ------------------------------------------------------------------------ DATE: 21-Jan-2016 Topic(s): Power Supply Work Working on the orienataion and positioning of the BULK_1V8 (DCDC6), FAN_1V8 (DCDC7), and BULK_3V3 (DCDC8) converters. DCDC5 and DCDC6 still need pin-arrays and clean up. PS drawings brought up to date. comps 2583 rev 524 nets 3599 rev 332 7576 connections 361 finished ------------------------------------------------------------------------ DATE: 20-Jan-2016 Topic(s): Power Supply Changes Based on the latest MGT power estimates I have gone ahead and changed the MGT_AVCC supply to a 20 AMP unit. The FPGA_CORE, MGT_AVCC, and MGT_AVTT supplies have all been rotated 90 degrees CCW and there may be routing advantage in also rotating the FAN_1V8 and BULK_3V3 supplies. - The output filter inductors in the MGT_AVCC and MGT_AVTT supplies are changed from the 470 nH 0.32 mOhm units to 680 nH 1.35 mOhm. The zero to full load drop will be about 15 mV. - Add bulk input filter caps for the DCDC5 SWCH_1V2 converter under the ATCA power entry module. These are in the dcdc_bulk_input_filter files. - Add bypass caps for the FPGA 3V3 VCCO supply. - Add Tant caps for the: BULK_3V3, SWCH_1V2, and FAN_1V8 supplies. The BULK_3V3 uses the 330 uFd 6.3V "V" case T520. These are in the Distributed_Bypass_Capacitors files. - Rotate DCDC5 SWCH_1V2 by 180 degrees. ------------------------------------------------------------------------ DATE: 15-Jan-2016 Topic(s): Power Supply Changes - All of the DCDC Converters are getting clamp zener diodes on their outputs: MMSZ4680T1G 2.2V zener for supplies <= 1.2V MMSZ4683T1G 3.0V zener for supplies <= 2.5V or MMSZ4686T1G 3.9V zener for supplies <= 3.3V. These are On-Semi part numbers. They are SOD-123 size, 500 mW, with the poor zener resistance that you would expect at these voltages but Xilinx likes them. They turn on forward at about 0.9V. - The current official expected MGT current draws for all of the links on the Hub with the XCVU125 part are the following: Full 109 Port Hub UltraScale 125 ----------------- Core: 20.77 Amps AVCC: 10.76 AVTT: 10.01 AVAUX: 0.59 - Based on the above change the AVCC converter DCDC2 from a MDT040 to a UDT020. The intent is to save space that can be used for decoupling caps. - Rotate the CORE converter DCDC1 by 90 deg CCW to move it further from U1. The hope is better air flow and better routing. - Study rotating DCDC2 and DCDC3 to see if that gives a better fit for the filter inductors. ------------------------------------------------------------------------ DATE: 12-Jan-2016 Topic(s): All FPGA spare pins labeled, Condo RJ-45 Notch, FPGA Heatsink, Front Panel Attachment Points, Plot Restored hub_fpga_select_io_usage.txt and ultra_no_connect_pins_nets from Durand and now all spare FPGA pins has associated nets. Currently we have an even 3600 nets at rev 323. I've added the required notch along the front edge of the card for the condo RJ-45 connectors. - The current setup is to make this notch 0.5 mm taller in the Y direction than the expected 16.00 mm width of this connector. Except for concern about the diameter of the pcb routing tool that is used to make this notch - this height in the Y direction looks fine. - The harder decision is how deep to set these connectors. In any case the edge of the pcb needs to be 10.55 mm from the center of this geometry. In theory the X set back for these connectors should be 18.58 mm with a 8.03 mm deep PCB cutout. I will set them at X = 17.55 mm which will require a 7.00 mm deep in X pcb Cutout. This puts the front surface of these condo RJ-45 connectors about 2.88 mm proud of the exterior front serface of the front panel. This should look fine and matches what I see on other equipment and gives us an extra 1 mm on the card. The 3 condo RJ-45s are spaced in Y by 22.00 mm. The required front panel cutout is 16.89 mm tall in Y by 23.88 mm wide across the panel. 22.00 - 16.89 = 5.11 mm tall bars across the panel between the connectors whcih sould be stron enough and OK for EDM machining. Add a place keeper FPGA Heat-Sink to the design. For now this is mostly to get some holes in the card to mount this heat-sink. Use 4-40 screws with the same relief as in CMX. - Use 4 pinch mounting screws which are for now centered on the 4 edges and 12 mm out from the device. - Use 3 motion control screws that are set 5mm back from 3 of the corners of the heat-sink. - For now make the heat-sink square with 120 mm on an edge and make the center of this geometry the physical center. Possible locations for front panel attachment points are: - make a bracket for the top side of the card that uses the normal front panel pivot screw and then attaches at another point going across the front panel and attaches to the pcb at a larger X dimention point (same Y as the pivot screw). - attach just below the front panel switch SW1. - can not attach just below the front panel access connector because of the leaver to actuate SW1. - attach just below the lowest RJ-45 - attach above the top RJ-45 but below the next upper LED complicated by the location of the MiniPODs or DCDC Converters close to front edge. - attach bridging over the Lemo connector The current best setup to plot the pcb from layout is to set Pin IDs to "none", turn on both Signal_1 and Pad_1 to get something for all pins, then use extended print, current view, landscape, and then in the .ps file set "1 P" to "5000 P". comps 2564 rev 498 nets 3600 rev 323 7567 connections 361 finished ------------------------------------------------------------------------ DATE: 8-Jan-2016 Topic(s): Design topics completed, Status and concerns, Meeting with Wade and Philippe Since returning the following sections have been added to the design: - Clocks: 25.000 MHz, 40.08 MHz LHC, 320.64 MHz LHC - Power Supply: Startup, Supervision, All OK, Startup Reset signals, Auxiliary Always-On, SysMon Ref supply - ROD Power Control - LED and Lemo drives and translators - Configuration Memory and overall Banks 0, 65 design. - JTAG string and skipping - I2C Bus and buffer/translation - DCI and VRef and MGT Calibration resistors - MiniPOD serial management and control buses - Crate/Slot Physical Address - Spare ROD-Hub lines The technical drawings are not up to date but the detailed written descriptions are not up to date. Status and Design Concerns: Routing: - Placement both sections (MiniPODs vs DCDC) and individual comps - Geoms: all need to be checked, complex parts, e.g. fpga, switches, Phys, MiniPODs are not finished yet. - FPGA connections: Still need to optimize MGT and Select I/O - Power Planes: Can we provide power distribution with this layout, Fill outlines are not yet started. - Can we escape the inner rings of the Banks with heavy use ? - Can we route all of the backplane J20:J24 under the GTH Fanout with the current placement and layer strategy ? - Known wrong things: Clock Gen placement and isolation with power supplies, No route for Iso +12V Mechanical: - Hole locations required before routing - Complex heat-sink designs are not yet started - Front Panel mechanical not yet started - No space to attach Front Panel. IPMC: - Need pins and software to get and present Shelf HW Address. - Need input for the SMB Alert signal - May want a control pin to turn off IPMC Sensor I2C Bus Monitoring Software and EPROM Content: - Switch chip EPROM contents - ATCA FRU Sensor I2C Monitoring EPROM contents - DCDC Converter control and monitor SW, e.g. GE or TI UltraScale points: - Different from bla,6,7 multi SLRs, must read books - Need FW sign-off on design, e.g. Clks, MGT, MACs - All 125 so far with no 160 work so far - Is the power available OK ? Missing: - Overall Hub block diagram - full Sensor I2C address map - connections, e.g. spare lines FPGA to IPMC Meeting - Major decisions: - give up on making this a vu160 design that is optimally backed off to a vu125 at build time. - need to get FW folks involved in "OKing" the design, e.g. the layout of the MGTs and clocks. I wrote a description and background note about this and mailed it and I updated the FW topics file on the web. ------------------------------------------------------------------------ DATE: 1-Oct-2015 Topic(s): Xilinx/Avnet meeting, design status, leaving for 2 weeks In our meeting with Mike, Greg, and Nick from Avnet we learned that the availability and schedule for the vu125 and vu160 look OK. After the meeting the decision was made to order 8 of the vu125. Nick is going to get us information about the Mechanical Sample package for the 2104 pin part. I'm going to get a BOM to Mike. Design entry work continues. The current state is: Step #5 - Calculate the number of pins that are connecter on certain components: U31 (Switch Chip A) has 257 pins with assigned nets out of 257 U32 (Switch Chip B) has 257 pins with assigned nets out of 257 U33 (Switch Chip C) has 257 pins with assigned nets out of 257 U21 (Phys to Other Switch) has 49 pins with assigned nets out of 49 U22 (Phys to This Switch) has 49 pins with assigned nets out of 49 Transmitter MiniPOD MP1 has 76 pins with assigned nets out of 81 Receiver MiniPOD MP2 has 76 pins with assigned nets out of 81 U1 (Virtex 7 FPGA) has 1599 pins with assigned nets out of 2104 Connector Meg-Array 1 has 396 pins with assigned nets out of 400 Connector Meg-Array 2 has 392 pins with assigned nets out of 400 Configuration Flash Memory has 64 pins with assigned nets out of 64 Backplane Connector P10 has 34 pins with assigned nets out of 34 Backplane Connector J20 has 112 pins with assigned nets out of 160 Backplane Connector J21 has 160 pins with assigned nets out of 160 Backplane Connector J22 has 160 pins with assigned nets out of 160 Backplane Connector J23 has 142 pins with assigned nets out of 160 Backplane Connector J24 has 160 pins with assigned nets out of 160 comps 2244 rev 432 nets 2867 rev 249 6720 connections 361 finished ------------------------------------------------------------------------ DATE: 25-Sept-2015 Topic(s): Design entry work continues, Meeting with Avnet/Xilinx for next week We have received more availability information about the XCVU125 that makes it look like this may not be a problem. Meeting with them next week on Wednesday. Design entry work continues, working on the various Level Translators. comps 2239 rev 427 nets 2736 rev 237 6594 connections 361 finished ------------------------------------------------------------------------ DATE: 18-Sept-2015 Topic(s): Design entry work continues, Trying to learn delivery schedule for VU125, Had a meeting with Yuri to discuss Hub design updates Setup a meeting with Avnet and Xilinx FAE on Wednesday Sept 30 to discuss the schedule for the VU125. On Wednesday Sept 16 we had a meeting with Yuri to discuss Hub design updates. Focused on Firmware: MACs for Phys and Switch management, Clocks for MGT and Logic, new need for I2C Master, and Configuration scheme. Talked about other various topics in the Hub design. Written notes in email. Design entry work on: the Phys chips, Configuration, and as always the power supplies. comps 2202 rev 409 nets 2661 rev 227 6478 connections 361 finished ------------------------------------------------------------------------ DATE: 8-Sept-2015 Topic(s): Connections to the Hub FPGA GTH/GTY Transceivers, Virtex-7 / Ultra moves Hub FPGA MGT Transceiver Connections - The list of FEX backplane input signal connections to the Hub FPGA (and to the ROD) are fully described in the file: hub_0_ab_gth_fanout_map.txt - The net_list file that makes the FEX input data connections to the Hub's FPGA is: .../Net_Lists/Build_GTH_Readout_Nets/gth_fanout_to_hub_fpga_nets - The net_list file that makes the Combined Data Output connections to the lines that run to the FEX cards is: .../Net_Lists/combined_data_distribution_nets - The net_list file that holds the following sundry MGT nets is: .../Net_Lists/hub_all_other_gth_nets 1 GTH input for the Other Hub's TCC + Readout Control Combined Data 1 GTH input for This Hub's ROD Readout Control Data 4 GTH inputs from the Receiver MiniPOD (its first 4 channels) 12 GTH outputs to the Transmitter MiniPOD 2 GTH outputs to send This Hub's readout data to the ROD on This Hub 2 GTH outputs to send This Hub's readout data to the Other Hub If I have to flip-flop between Virtex-7 and UltraScale it's not going to be super easy or fast. The archive to get all of the Virtex-7 stuff is: /home3/edmunds/BackUps/backup_hub_0_fri_7.tar from August 28th But I do NOT want to just extract this full archive because a bunch of other work (i.e. not Virtex-7 / Ultra) was done during this same period. A sketch to restore Virtex-7 is: get the Virtex-7 BGA geometry from ./Not_Current Edit the comps file to use the Virtex-7 geometry Change net_names in dcdc_2, dcdc_3, dcdc_4 Fix a filename or two in the nets build script restore the Virtex-7 gth_fanout_to_hub_fpga_nets restore the Virtex-7 combined_data_distribution_nets restore the Virtex-7 hub_all_other_gth_nets Swap the Virtex-7 / Ultra ultra_fpga_bypass_cap_nets ultra_fpga_power_ground_nets ultra_no_connect_pins Restore the Virtex-7 .../Text/hub_0_ab_gth_fanout_map.txt A lot of clean up was done during the move to Ultra, e.g. the SFP+ was fully pulled out and cleaned up, filenames were cleared up. ------------------------------------------------------------------------ DATE: 4-Sept-2015 Topic(s): Hub design moved to Ultra XCVU125 Finished moving the Hub design to UltraScale XCVU125 ub the FLVC2104 package. The 1115 power and ground pins and all of the GTH and GTY Transceiver pins used in the Hub design have been moved over. The required net names have been changed to make them appropreate for the UltraScale part. Status: comps 2079 rev 394 nets 2598 rev 213 6243 connections 361 finished ------------------------------------------------------------------------ DATE: 26-Aug-2015 Topic(s): Hub design moves to Ultra-Scale, No Hub connection to the 4 Spare_R2H signals from the ROD. Decision to move the Hub design to Ultra-Scale. This will be the XVU125 part. That is, we are staying with 80 Transceivers. Issues to rework the FPGA power and bypassing as required. A fast initial study needs to be done on how to allocate the different types of Transceivers on the Ultra-Scale part and how to best use the 2 QPLLs and reference clock distribution. Discussion about the Hub making no connection to any of the 4 spare ROD to Hub signals on MegArray S2: SPARE_R2H0 ... SPARE_R2H3. No change in Mentor counts. Power supply simulation work continues. ------------------------------------------------------------------------ DATE: 24-Aug-2015 Topic(s): Design entry work on Hub supplies A big concern has been the noise from the GE Power Modules and whether or not this was going to cause a problem for the FPGA GTH circuits or for the GTH Fanout. The main problem with doing a nice job to filter out this noise is that there is no space on the card for the required components. Multiple solutions have been looked at: very large output capacitor filter banks (does not work), LC filter with feedback after the filter (no space and servo loop will oscillate), LC filter with feedback before the filter (problem of uncontrolled DC drop across the filter - needs physically large low resistance inductors). I now have a simulation of the GE buck converter, its output capacitor bank, its servo loop, and an optional "external" LC filter. This is a fancy simulation with capacitor ESL and ESR, and inductor ESR, and approximate trace (area fill) resistance. The limitation is guessing what the GE folks actually put in their converters. Main conclusions: feedback after an external LC filter does not work, even putting just the DC component after the filter does not work. The problem is we are stuck with the type III compensator in the GE module. Given full control over the 6 components in the type III compensator it looks like you can make things nice an stable with either just an output capacitor bank or with feedback taken before and external LC filter. Lack of a clear zero in the output capacitor bank because of the multiple types of capacitors used does not seem to be a major problem, i.e. tuning the values lets your work around this problem. Worked on more cleanup of the GE power module pcb layouts. comps 2078 rev 390 nets 2470 rev 203 6021 connections 361 finished ------------------------------------------------------------------------ DATE: 4-Aug-2015 Topic(s): Design entry work on Hub supplies Detailed designs are now in for the 40 Amp and 20 Amp supplies. There is still a little work on the 20 Amp filter capacitors but it is mostly all in. I wish that I could rotate the 40 Amp and 20 Amp by 90 deg CW but I think that would make for poor air flow through the supplies. I wish that I could move the BULK_1V8 and the POD_2V5 to the west of the MiniPODs but again there is probably an air flow problem. Coloring the map of power fills looks more or less OK - but so far no solution for getting the ISO_12V to the north of the power supplies. The supervisor design - both the sequencing of the Hub power supplies and the On/Off control of the ROD are now pretty firm and look OK. comps 2029 rev 366 nets 2464 rev 193 5933 connections 361 finished ------------------------------------------------------------------------ DATE: 31-July-2015 Topic(s): Design work on Hub Power Supplies All design work this week has been on the power supply system for the Hub Module. This has mostly involved the Input Filter capacitors and the Output Filter capacitors for the GE DCDC Converters. The Input Filter array is divided into a "Local" section right at each converter and a common "Bulk" array that is located on side #2 under the ROD. The Output Filter capacitors for each converter are divided into the "Local" capacitors right at each supply and the ByPass capacitors that are located near their loads. For the FPGA supplies there are very significant amounts of ByPass capacitors located at the loads. Many issues remain: - Will these supplies be quiet enough for GTH ? In some cases, at best, they look too noisy by a factor of 2. - Cooling of these supplies look not optimal. If placed in the specified prefered air flow direction then the input and output pins are in a bad place for all 3 types of supplies. By bad place I mean, they take up extra space in that orientation, the power planes must cross over each other to get to the pins, not enough space for the Local capacitors. So I'm putting them in a not prefered air flow direction - but who know the direction of the air flow right next to the ROD mezzanine anyway. Ed and company are also working on ps design for the ROD and he has been passing information about their work to us. The layout work for the power supplies has included making power via arrays to make it easier to route the card. Also worked on the sequencer for the supplies. Status: comps 1976 rev 357 nets 2452 rev 190 5774 connections 361 finished ------------------------------------------------------------------------ DATE: 24-July-2015 Topic(s): Meeting about link speeds, move to GE DCDC Converters, ROD - Hub mounting Today we had a meeting with the usual suspects and with people from Felix about the links between Felix and L1Calo. This was pushed by wanting to understand the required number of clock nets and their frequencies on the Hub Module. From this meeting I think it is clear that the Felix to Hub "Optical TTC Signal" will for now and always be 4.8 Gbps. The speed of the readout data links to Felix is still not understood. Lots of people have different ideas. I would like to see something in writing but everything is still mostly oral tradition told around the camp fire. From the Felix discussion Wade had the good idea that all of the Hub's life boat optical connections (if ever used) will run to Felix. Thus nothing is special about the SFP+ optical input for the Optical TTC Signal. Thus we do not need a SFP+ on the Hub just to receive the Optical TTC Signal. Rather we can use the Receiver MiniPOD to ingest the Optical TTC Signal. Thus we can dump the SFP+ and its associated power supply filter components. As part of this Wade wonders if we should route out the optical fiber ribbons from the Hub's 2 MiniPODs on the backplane MPO connectors to the Rear Transistion Module. That could mean that the Hub does not need its Front Panel MPO feedthrough connectors. I have completed the move to GE DCDC Converters. The Hub currently has 7 GE DCDC Converters, 2 Linear Regulators and 2 reference type supplies. This saved space mostly because the GE converters specify smaller capacitors on their input and output filters. The hope is that they will actually meet the noise level requirements with these smaller capacitors. One one hand they do switch at 500 kHz vs 300 kHz but on the other they are the same buck topology converter so how can they have a lower noise level. Bypass caps for the Virtex FPGA and for the DCDC Converter bulk input filter are now also in. From Ed, the hardwware for the standoffs between ROD and Hub will be size M3. A normal M3 screw head is 6 mm dia. A standard M3 washer is 7 mm OD. A standard oversize M3 washer is 9 mm OD. A M3 nut is 5.5 mm across flats. I will try to enforce a 1 cm keep out on Hub and drop to a 7mm keep out only if necessary. comps 1948 rev 318 nets 2452 rev 182 5412 connections 361 finished ------------------------------------------------------------------------ DATE: 13-July-2015 Topic(s): Work on new DC/DC converters Work on moving to GE DC/DC Converters. The main thing that we may get from this is that both the Hub and ROD will have the same type of PMBus controlled/monitored power supplies and thus the overall setup will appear more uniform. - These are a newer design but on the inside they are still just Buck topology. - They typically use less input and output capacitance for a given noise level perhaps because they are 500 kHz vs 300 kHz and perhaps because of better magnetics. - I think that the feedback setup and loop stability may be easier to understand. - I think that these are real SMD parts which if so means that we can not replace them in-house. - I don't know yet if the bigger ones are multi-phase but hope that they are. As part of this power supply change I'm moving the GTH Fanout to its private converter. From Ed's work it appears that the fanout chips run as well or better from a 1V8 supply than from a 2V5 supply. The issue in running them directly from the BULK_1V8 bus is that we may have a high noise on the general purpose BULK_1V8 bus and it hard to put a choke in series with the 13 Amp load of the fanout chips. ------------------------------------------------------------------------ DATE: 10-July-2015 Topic(s): Hub Design Work All work has been on trying to make the power supplies smaller and verifying that the Ethernet Magnetics will work and is routable. It may be worthwhile to actually route the Ethernet Magnetics into the Zone 2 connectors. Still big question about where to put the Etherent Magnets for the connections at the top of Zone 2. ------------------------------------------------------------------------ DATE: 6-July-2015 Topic(s): Import from Durand, Hub Component Layout Import: traces.traces_36 from Durand and replace the original office traces.traces_29 with it. This completes for now the routing work in the GTH Fanout - but there is still a ton of detailed routing work in this area to be done: finalize bends in the unit cell and then copy, add bends to the long runs, equalizer enable section routes, Clock and Combined Data routes on the inner layers under the GTH Fanout, best use of space and non- overlaps on the 45 deg runs. Start work on new component layout to try to fit on all of the required parts. The general plan is: - Rework power supplies, GTH Fanout is now 1V8, so maybe both GTH_AUX and 2V5 for MiniPODs can be linear ? - Move the ATCA Power Entry and Isolated 12V modules away from the backplane to make space for the Ethernet Magnetics - but this makes too much free space in this area - how to best make use of this "extra" space ? - It's OK to move the ATCA power modules away from the backplane Zone 1 connector because there are not really very many traces to it and none are that high of a current. - Shove all of the Ethernet Switch stuff down into this area including its front panel connectors ? Is there interferrence with the front panel handle ? or an issue with the PCB cutouts for the condo Ethernet connectors ? - Must move the Hub's Virtex FPGA so that it is centered vertically on the GTH Fanout. This is to minimize the space required to route the 74 GTH readout traces into it. - Dump the ATCA side 2 cover standard mounting screw hole locations. At least two of these are clearly smack in the middle of where we need to put things and we will need a custom side 2 cover for air circulation around the GTH Fanout anyway. - May need or want to route some all of the Ethernet magnetics and Zone 2 connections to prove that it all will fit in. comps 1718 rev 297 nets 2441 rev 174 5206 connections 361 finished ------------------------------------------------------------------------ DATE: 4-July-2015 Topic(s): File imports from Durand Import: aa_build_megarray_s2.sh, megarray_s1_lower_template.txt, and megarray_s2_lower_template.txt from Durand and rebuild both the S1 and S2 MegArray Geometries. Import: traces.traces_33 from Durand and replace the original office traces.traces_29 with it. The filename of the original office traces.traces_29 picks up the sufix _office. ------------------------------------------------------------------------ DATE: 2-July-2015 Topic(s): Gnd Via Field Fill, S1,S2 Geometry While working on the Gnd Via Field Fill I discovered a problem in the S1 and S2 MegArray geometries when I try to invert the signals. I was doing it wrong, i.e. major fatal screw up and a lost day of routing. Rules for the MegArray Geometry: Columns E and H can use only NE and SE versions of the pad-stack. Columns F and J can use only NW and SW versions of the pad-stack. The goal is to swap which signal has its via above or below the row - not to invert the polarity. Don't be stupid again. Add only the MegArray escapes to the design that you are going to actually route during a given traces saved session. Don't add all of them at once because if you need to change things then they are trashed. Rules: All polarity inversions are done in the Net List file and have clear supporting comments. Zero criss-cross routing is accomplished by controlling the MegArray Geometry, i.e. which signal escapes over the top of the row and which signal escapes under the row. These are clearly separate goals, both are required, and with a little organization there is no reason to get things mixed up again. ------------------------------------------------------------------------ DATE: 1-July-2015 Topic(s): MegArray S2 Escape, Gnd Via Field Started and finished the S2 MegArray escape traces. Started work on filling in the Ground Via Field in the high-speed section of the MegArray connectors. Many questions: is it worth the effort ?, any problems with two dog-bones on a given BGA pad ? But yes one can make the Gnd Vias symmetric around the high-speed pads and escapes. Sent note to Ed and Ian to release the GTH Fanout Map to the ROD. ------------------------------------------------------------------------ DATE: 29,30-June-2015 Topic(s): Work on the "Map" file and the escape traces from the MegArray Wrote the "Map" file to describe the connections from the Zone 2 Fabric Interface inputs, through the GTH Fanout Array, and up to the MegArray connectors for the ROD. Wrote the Mighty routine to generate the escape traces from the S1 MegArray. These are setup to be on the correct PCB Layers to match their connections from the GTH Fanout Array outputs and these escape traces include the high-speed diff pair miters. The same scheme can be used to generate the S2 escape but I should probably route the S1 first just to prove that it is OK. comps 1718 rev 293 nets 2441 rev 172 5276 connections ------------------------------------------------------------------------ DATE: 26-June-2015 Topic(s): Work on the GTH Fanout to MegArray connector routing - In both S1 and S2 I need to flip the over vs under escape in the lower pin 21:40 section of the connector for both the E,F and H,J columns in S1 (and the B,C and E,F columns of S2). This is not a netlist change - it's just a change in the geometry about which pin, e.g. E or F, escapes over and which escapes under. The top half of both the S1 and S2 geometries are OK as is. - In both the S1 and S2 geometries I need to reduce the pad land size and the drill size of the high-speed differential pair vias. This is both to inprove the 10 Gbps signal environment but is also necessary on the Gnd vias that the double track route goes through. So start another 4 patterns of BGA Pad and Via this time using the standard high-speed 0.25 mm drill via setup. Call PAD_SML_VIA In connector S1 these are used on all of the GTH differential pairs in Columns E,F and G,H and on all of the Row 2:39 Gnd pins in Columns F,G,H,J,K. Only connector S1 has been modified so far. - Because of the English dimensions of the MegArray connectors and the need for absolute control of the double track escape routing I'm going to try to build the escape of the high-speed pairs into the S1 and S2 geometry. This escape will require a width change (as in the FPGA BGA escape. - Save version 27 of the traces file as the last known good version before the hack to try to escape the MegArrays. - The basic two track escape strategy with the 1.27 mm pitch and 0.56 mm via lands is: 0.56mm via, 0.14mm space, 0.13mm trace, 0.17mm space, 0.13mm trace, 0.14mm space, 0.56mm via. ------------------------------------------------------------------------ DATE: 25-June-2015 Topic(s): Modifications to the GTH Fanout Array for routing high-speed signals to the MegArray connectors Decisions: - GTH Fanout Channels 4, 8, 12, 16, ..., 68, 72 will route to the MegArray connectors on layer Signal-10. Thus pull out of the comps design and remove from the netlist: DPV412, DPV424, DPV436, DPV448, ..., DPV604, DPV616. - Rework of the placement of the West most DC Blocking Caps and their associated Differential Via Pairs. The placement of these components at the very West edge of the fanout array can be different than in the normal "unit cell" and it can be arranged to save perhaps 0.5 mm in the X dimension. The components that need to be rearranged are: DPV402, DPV403, C401, C402, C403, C404; DPV426, DPV427, C457, C458, C459, C460; DPV450, DPV451, C513, C514, C515, C516; ....; DPV494, DPV495, C849, C850, C851, C852. - Move to placing the Coupling Caps 0.9 mm center-to-center instead of 1.0 mm. This makes the GTH Fanout Array look a little better but will now requuire routing on a 0.05 mm grid - but I think that I needed that anyway. The coupling caps are: 0.3 mm thick, 0.3 mm wide, and 0.6 mm long. So even at a 0.9 mm center-to-center there is still a nominal 0.6 mm between the caps and there is 0.50 mm between adjacent pads at closest approach. ------------------------------------------------------------------------ DATE: 24-June-2015 Topic(s): Real MegArray Geometries and GTH Nets from the GTH Fanout to the MegArray Connectors We now have a realistic working pair of MegArray geometries for S1 and S2. For the high-speed diff pairs they use the same escape pattern as Ed used on the Host board. Now I need to setup the routes from the GTH Fanout to these MegArray connectors to take out the inversion that some GTH Fanout channels have from there Zone 2 input trace routing. The intent is to then modify the MegArray or straight through route, with or without inversion, so that overall all channels to the ROD have no inversion. This will be a lot of back and forth work between GTH Fanout to MegArray NETS and the MegArray Geometry. Reacall the GTH Fanout Channels with Inverted Inputs: Note that some signals are "inverted" as they leave this net list file. This is to eliminate the need to flip these traces during routing. - In the lower physical half of the GTH Fanout Array, i.e. FEX-03 through FEX-08, the EVEN numbered GTH Fanout Channel inputs are inverted. That is, in the GTH Fanout Channel range 1:36, the EVEN numbered GTH Fanout Channel have inverted inputs. - In the upper physical half of the GTH Fanout Array, i.e. FEX-09 through FEX-12, the ODD numbered GTH Fanout Channel inputs are inverted. That is, in the GTH Fanout Channel range 39:74, the ODD numbered GTH Fanout Channel have inverted inputs. - NOTE that GTH Fanout Ch #72, i.e. FEX-12 Lane 3 is an exception. GTH Fanout Ch #72 is inverted to allow a clean route into the 10 cells in the top, i.e. 9th row of the GTH Fanout Array. - From the "Other Hub" the input to GTH Fanout Channel 37 was inverted to facilitate routing. The Hub's Virtex FPGA has been moved out of the way of GTH Fanout to MegArray high-speed trace routing. The Hub has room for either its FPGA or for the GTH Fanout Array. ------------------------------------------------------------------------ DATE: 22,23-June-2015 Topic(s): Work on a real MegArray Geometry Worked to understand how the MegArray is laid out on Ed's Host card. The point of this is that the ROD will be laid out about the same way and that it might be good if the Hub matches this so that the 10 Gbps signals only need to learn how to make it through one complicated MegArray escape. The Host board layout uses a nice double trace between the 1.27 mm pitch BGA pins and then a nice symmetric transition to the top surface layer that can easily make a polarity flip. The bad parts are: the Ground Thru-Vias are not symmetric around the differential pair. in places two Gnd BGA pads share a Gnd via, in some places even 3 Gnd BGA pads share one Gnd via, the layout of S1 and S2 need to be different. There is also the issue of figuring out how to handle all of this with Mentor. A point is that this will be a THD component with extra SMD pads. All of this can be handled but it is hand work and not quick to change. The point for now is to understand and route the highest priority signals, i.e. the 10 Gbps GTH Fanout. So for now I will make a rational as possible columns D:K for S1 and columns A:G for S2. The plan is to build this by separate scripts and use two runs of the Multi Instance Generator (North Half and South Half, and put in the odd rows 1 and 40 by hand. ------------------------------------------------------------------------ DATE: 19-June-2015 Topic(s): Work on GTH Fanout Routing into the GTH Fanout from the Zone 2 connectors looks OK. The GTH Fanout Unit Cell looks OK. Working on the routing from the fanout up to the MegArray connectors. The netlist for this has been rewritten to reflect the new requirements. Need a "real" MegArray geometry, i.e. with the correct pad via locations before any routing work into the MegArray can start. Checked the Host board Gerbers and I do not understand how they match the MegArray_Pinout_V1p4.pdf 07-May-2015 specification. Need to talk to Ed. comps rev 285 nets rev 162 1737 components 2437 nets 5204 connections ------------------------------------------------------------------------ DATE: 18-June-2015 Topic(s): Work on the GTH Fanout The position and unit cell spacing of the GTH Fanout Array now looks tentatively fixed. More tune-up moves in the unit cell: DVP and coupling caps 0.2mm west, inboard I/O pairs further out 0.1mm. That makes the DVP to the center of the inboard I/O pair space 1.2 mm and the inboard to center pair space 1.9 mm. All work today was on clean up of the input to the lower section and the start of routing into the upper section of the GTH Fanout Array. 74 - 10 (from the long top row) = 64 pairs to the MegArray connectors must route up through a vertical channel between the GTH Fanout Array and the FPGA. 64 pairs taken 4 at a time is 16 paths or 15 x 2.0 + 1.2 = 31.2 mm wide channel. We don't have 32 mm. ------------------------------------------------------------------------ DATE: 17-June-2015 Topic(s): All work on GTH Fanout Work on the placement of the GTH Fanout Array, the high-speed differential via pairs to bring signals in and out of it and the routing of the Zone 2 signals into it. The routing to the Zone 2 connectors is the major point in determining how far East I can shove the Fanout Array. At some level the issue is the "quality" of these high-speed routes. Look at differential trace lengths for different ways of escaping the Zone 2 connectors and routing into the Fanout Chip Array. These are near final routes but not yet smoothed with curve sections of trace. In all cases the polarity flip is set so that there is no trace crossovers. Standard Escape Under and Enter through DVP: GTH_FO_CH_30_IN_DIR 42.71 mm GTH_FO_CH_30_IN_CMP 43.31 mm delta 0.60 mm Special Escape Over and Enter through DVP: GTH_FO_CH_29_IN_DIR 58.62 GTH_FO_CH_29_IN_CMP 59.38 delta 0.76 Standard Escape Under and Direct Enter: GTH_FO_CH_32_IN_DIR 21.91 GTH_FO_CH_32_IN_CMP 22.59 delta 0.68 Special Escape Over and Direct Enter: GTH_FO_CH_24_IN_DIR 30.20 delta 0.69 GTH_FO_CH_24_IN_CMP 29.51 There is no clear delta length advantage to the "over the top" escape in the Zone 2 connector so the shorter and more direct "under" escape will be used for all connections to the bottom half of the fanout chip arrary inputs. Ed has checked operation with 1V8 and 2V5. So far there is no clear advantage to the 2V5. He also checked with the equalizer On and Off. The equalizer probably helps. His setup now includes a cable section before the fanout chip (and after ?) so it is more realistic thatn first thought as far as the signals having suffered some attenuation before getting to the fanout chip. comps rev 271 nets rev 151 1729 components 2437 nets 5212 connections ------------------------------------------------------------------------ DATE: 16-June-2015 Topic(s): Start Routing the Fanout Array Shift the 1000 components in the Fanout array again to finalize its horizontal location. Rules for the Zone 2 input traces: - Pair center to West 0.60 via center 1.20 mm - pair center to East 0.80 pin center 1.40 mm (recall press fit) - pair-to-pair centers 2.00 mm (5x rule and 8 pairs) So need 16.60 mm from the West via center to the East pin center. Shift East by 1.40 mm. Vertically the via center-to-center is 6.20 mm i.e. 1.10 + 2.00 + 2.00 + 1.10 = 6.20 mm. I'm switching to 0.30 mm trace width for the ground and power pins to the fanout chips. This is up from the 0.20 mm used on CMX but Motorola increased the reccommended pad width on their qfn_16 by 0.05 mm. ------------------------------------------------------------------------ DATE: 15-June-2015 Topic(s): GTH Fanout Design Rules A "flow through layout of the GTH Fanout will be tried with the following rules. Space for 3 diff routes between the rows is needed. - HS Diff pairs are drawn as 0.14 mm wide spaced 0.40 mm - Center-to-Center HS Diff Pairs are kept 2.00 mm - HS Diff Pair center to the center of a neighbour via 1.10 mm This is in the horozontal channel between rows. In other areas try to hold to 1.20 mm pair center to neighbor via. - HS Diff Pair Vias 1.00 mm center-to-center signal vias 0.25 mm finished hole diameter 0.56 mm land pad 1.00 mm plane relief - HS Diff Pair Vias 1.00 mm ground to signal vias center-to-center 0.30 mm finished hole diameter 0.60 mm land pad 0.87 mm plane relief There needs to be a large routing channel to the East of the Fanout Array to connect to the Zone 2 input signals. This should not need to be larger than 1.20 mm + 7 x 2.0 mm + 1.20 mm = 16.40 mm but this does not take into consideration the via pairs to lift the Other Hub's readout. Dump all traces to start over. ------------------------------------------------------------------------ DATE: 12-June-2015 Topic(s): ROD-Hub Aurora Meeting On Thursday the 11th we had a ROD-Hub meeting about the recent decision to use Aurora protocol for the 6 lanes of readout from each FEX card. This has some implications for the Hub Module: - The statement in the Hub design report about routing the GTH signals for best signal fidelity will no longer be followed as they now want to receive signals in an order on the ROD. - The notes with Ed about FEX and Hub readout ports being the interchangeable is no longer in effect. - They talked about needing a separate reference clock feed to each Quad and Weiming likes 2 reference clocks to each quad. Tried to rule out 9.6 Gbps but I do not think that it worked, i.e. still not clear what reference to use. It's clear that the GTH fanout is going to take much more space and that it can not be routed with the current floor plan. Setup to route through the GTH fanout in order and to hop the Other Hub readout over the top before the fanout. To gain more space for the GTH Fanout and to move it down to center it over where these signals arrive in Zone 2 (at a Y of about 127 mm), move out 1/2 of the Ethernet Magnetics. Setup to do the HS Diff Vias as a component. The HS Diff Via component and the cap_0201 comp have built in ground cutouts. This plus net types makes the ground plane cutouts automatic. Confirmation from Ian: the FEXs are named by logical slot number and the Aurora lane to ATCA Channel Port maps is: Aurora 0, 1, 2, 3, 4, 5 FEX End ATCA Tx0, Tx1, Tx2, Tx3, Rx2, Rx3 Hub End ATCA Rx0, Rx1, Rx2, Rx3, Tx2, Tx3 Hub Zone 2 Pins c,d g,h c,d g,h a,b e,f Hub Zone 2 Row low low up up up up comps rev 248 nets rev 143 1734 components 2437 nets 5249 connections ------------------------------------------------------------------------ DATE: 5-June-2015 Topic(s): End of week status Worked on test routes in the GTH Fanout Array. The original plan for this was a disaster: comp layout could not work, nets could not work, double side mounting could not work. Unless the GTH Fanout Array can squeeze a lot in "X" then I can prove that the vertical routing channels are not big enough. I've already squeezed the "X" pitch down to 5.5 mm. Something will have to give. The FPGA needs to come down and that means that the Switch layout will not work and that means that the power supply layout will not work. Finally now have a fast setup to change the "X" and "Y" pitch of the GTH Fanout Array and move it in "X" and "Y" about the PCB and to have different Side 1 and Side 2 layouts. Need to implement the same for nets as I can prove that the Top and Bottom need to be different. comps rev 231 nets rev 133 1512 components 2430 nets 4758 connections ------------------------------------------------------------------------ DATE: 3-June-2015 Topic(s): Move to realistic set Layers Made a guess at a stackup that will work for the Hub Module, i.e. 8 routing layers, 2 split routing and power, 2 power, and 10 ground planes. Then moved the Mentor design to represent this 22 Layer stackup for the Hub PCB. Currently I can prove that you can not do the Hub in less than a 22 Layer PCB. At the same time I moved to a realistic set of design rules for a 22 Layer stackup. All of this gave some problems (as expected): - undefined via geometries in the tech.tech file caused by the current baby geometries for the big BGA parts. - Layers missing in the default artwork order because of the obvious. - Hub PCB layer miss-match to the tech.tech - obvious - fixed. - Invalid Placement of the Quad_LED part - curious. This came not from the realistic layers but from moving to realistic design rules. The "Invalid Placement" is actually a "trace to pin" violation which is actually a "pad to drill hole" spacing problem with this Quad_LED component. There is no way around this tight pad to drill hole spacing with this component. I will try moving all of these Quad_LED nets to a private set of design rules. Note that the layer strategy implemented today is just a guess at what rational setup will work for the Hub and what the PCB House can actually manufacture. The focus now is on proving that the GTH Fanout and Zone 2 can be routed so no additional design entry so far this week. From the first try in the GTH Fanout array: - Zone 2 to inputs on just the top side FO chips need to be flipped. - The FO chip filter caps should probably rotate 90 deg. comps rev 218 nets rev 131 1512 components 2430 nets 4756 connections ------------------------------------------------------------------------ DATE: 1-June-2015 Topic(s): Design Entry Work Pushed on the chokes and filter caps for the Switch Chips and both types of optical modules. To fit some rather non- conservative parts were selected but it is now all in the design. Now really need to focus on: will the plan for routing this actually work ?, will the planes work ?, and order parts. comps rev 218 nets rev 129 1512 components 2430 nets 4756 connections ------------------------------------------------------------------------ DATE: 26-May-2015 Topic(s): Design Entry Work The IMPC has been moved to the East side of the ROD to provide a ROD fiber optic ribbon storage space. In Hub coordinates the SW corner of the ROD is now at 25.0 mm 210 mm. Now using the correct ROD major component coordinates. The script to building the net list now shows the number of connected pins on the major multi pin components. With basically all of the Switch and GTH Fanout components the focus now has to be: - Verify that this card is routable with the current layout. - Verify that the power plane and ground plane layout will work. - Order the long leadtime parts. The details of many sections of the card still need to be entered: - power supplies - power supply supervision - power supply OK Limits - power supply monitoring, i.e. Volt.Amp,Temp monitoring - FPGA Configuration - and the rest of FPGA Bank Zero - JTAG from the front panel - Sensor I2C Bus - MiniPOD Serial Buses - SFP+ Serial Bus - GTX Fanout Equalizer Control - level translators both static and bi-directional. comps rev 204 nets rev 121 1469 components 2388 nets 4657 connections ------------------------------------------------------------------------ DATE: 8-May-2015 Topic(s): Design Entry Work Much time spent trying to understand the required: jumpers, eeprom setup, and path for FPGA control and monitoring of the Ethernet Switches. Still no detailed design for: the power supplies, their supervision and monitoring, the FPGA configuration, the JTAG, the Sensor I2C, or the required level translators both static and bi-directional. Working on component placement to make fiber optic ribbon routing more rational. There is almost enough in to get very very serious about routing all the ADF backplane connector signals and the power plane layout (which are connected). comps rev 193 nets rev 107 1387 components 2044 nets 4489 connections ------------------------------------------------------------------------ DATE: 1-May-2015 Topic(s): Meetings, Design Entry On Friday May 1st we had a meeting with Yuri focused on FW and SW that will be needed for both the initial MSU tests of the Hub Module and this falls CERN Link Tests. On Thursday April 30th we had a video meeting with Ed. The meeting focused on details of the ROD and Hub designs and connecting them. Various documents were exchanged as part of this meeting. On Tuesday April 28th Ian held an overall meeting to plan for the Link Tests at CERN this fall. This meeting was LAr and L1Calo people. Hub design entry has focused on finishing the details of the Base Interface Ethernet Switches and on trying to understand all of the routing under the GTH Fanout. comps rev 180 nets rev 97 1355 components 1960 nets 4361 connections ------------------------------------------------------------------------ DATE: 24-April-2015 Topic(s): Design Work Continues Design work has been focused on trying to completely finish the entry of the Switch section of the overall Hub Module. Connections are being made to the Meg-Array connectors according to Ed's p1p3 list from 24-Mar-2015. Current Counts: comps rev 173 nets rev 77 1322 components 1880 nets 3983 connections ------------------------------------------------------------------------ DATE: 17-April-2015 Topic(s): Design Work Continues Design work on all sections of the Hub Module continues. No section is finished yet. Current Counts: comps rev 151 nets rev 50 846 components 1368 nets 2496 connections ------------------------------------------------------------------------ DATE: 10-April-2015 Topic(s): Building Nets and Comps files Both the Nets and Comps files are now real and being built from scripts. The current counts are: comps rev 133 nets rev 25 483 components 705 nets 1673 connections ------------------------------------------------------------------------ DATE: 25-Mar-2015 Topic(s): Hub Module Card Count The official Hub Module Card Counts from Wade on 25-Mar-2015 are: Prototype Build in the summer of 2015: --------------------------------------- 8 fully working cards: 2 for MSU, 2 for CERN, 1 for Rutherford, 1 for Brookhaven, 1 for Cambridge/Birmingham, 1 spare 1 card without the expensive parts installed, this is for power supply checks 2 bar PCB: Thermal Profile and view/check layout Pre-Production Build in t 201?: -------------------------------- 4 fully working cards Production Build in t 201?: ---------------------------- 19 fully working cards The parts purchases at this time will be: - for expensive stuff just enough to support the summer 2015 prototype build - for inexpensive stuff enough for all 3 builds ------------------------------------------------------------------------ DATE: 24-Mar-2015 Topic(s): Building Hub Module Comps file I have finally switched over to using an overall script file and a bunch of "sub-routines" to build the Hub Module Comps file. The sub-routines called are: comp_line_comments_remove.sh comps_clean_it_up.sh convert_mm_to_deca_nm.py migt_f.py mrpcs.py The points of these are to: generate multiple instances, move relatively positioned component sets, strip out comments at the end of component statement lines, strip out all other formatting for the benefit of humans, and prevent/remove any rounding error (going off grid) when converting from mm to tens of nano meters. Working on the placement of the GTH Fanout components so that it is possible to route this section of the card. Currently: 364 Comps 141 Nets 142 Connections 142 Guides At version 90 of the Mentor comps file. ------------------------------------------------------------------------ DATE: 12-Mar-2015 Topic(s): ROD-Hub Video Meeting - Hub Documents We had a Hub video meeting with Ed and Maurice. The focus was on the non-GTH connections between ROD and Hub and of the physical layout of the two cards. They are pushing to release the Host board for manufacture. We now are public with: Hub FPGA Topics and non-GTH Connection Definitions. ------------------------------------------------------------------------ DATE: 4-Mar-2015 Topic(s): Ship Xilinx VC709 I shipped the VC709 demo board (and a CMX CANBus uProc. cable) to Yuri. Philippe took some pictures of the VC709 before I shipped it - especially of the back side which is not covered in the User's Guide. ------------------------------------------------------------------------ DATE: 26-Feb-2015 Topic(s): ROD-Hub Video Meeting Hub video meeting with Ed - a get organized and get working on Hub again meeting for me. ------------------------------------------------------------------------ DATE: 18-Feb-2015 Topic(s): Start the push on Hub Module CMX cards SN-21, SN-22, SN-23 were shipped to Yuri on Friday 13-Feb-2015. Used a couple of days to clean up the CMX parts stock, documentation, and test setup and then today started spending the majority of effort on the Hub Module. ------------------------------------------------------------------------ DATE: 1-Oct-2014 Topic(s): Hub Review Meeting Today was the official Hub Prototype Review Meeting. This was a video meeting with a fire drill and a move to the Plant Biology Building across the street. ------------------------------------------------------------------------ DATE: 23:28-Sept-2014 Topic(s): Meetings at CERN Trip to CERN for L1Calo meeting and a specific ROD-Hub meeting and to watch frogs fling themselves off mountains. ------------------------------------------------------------------------ DATE: 21-Sept-2014 Topic(s): Hub Specification on the Street Released the "Technical Specification Atlas Level-1 Calorimeter Trigger Upgrade FEX System Switch Module (FEX Hub) Prototype" Draft Version: 0.3 ------------------------------------------------------------------------ DATE: 22-Apr-2014 Topic(s): X,Y 0,0 of the Mentor Design The ATCA specification does not dimension things wrt the lower left-hand corner of the card. Rather the ATCA dimensions are wrt the center of a required hole that is located in the lower left-hand corner of the card. The center of this hole is at X = 3.57 Y = 5.55 wrt the lower left-hand corner of the card. All dimensions in the Mentor design of the Hub-Module will be wrt the lower left-hand corner of the card. ------------------------------------------------------------------------ DATE: 17-Apr-2014 Topic(s): Start a Hub_0 Mentor design. Start the Hub_0 Mentor design. ------------------------------------------------------------------------ END