Measure the  Stability of the Latency  of the
   LHC Reference Clock from TTC Crate to FEX Card
  ------------------------------------------------


Note:  I use the phrase Reference Clock  because the clk
signal that the Hub sends across the backplane is not
really a clock,  i.e. it does not directly cause things
to happen,  rather it is the reference for PLL "jitter
cleaners"  that generate the actual Clocks.



Possible phrases to use in the Title:
-------------------------------------

    Full Path from FELIX input to LHC Ref clock on the FEX

    Stability of the Latency

Note:  we are not measuring a latency - rather over time
and over restarts of the Hub FPGA we are checking the
stability of this latency.



Short Explanation:
------------------

The two traces on the oscilloscope are used to test the
stability of the LHC Reference Clock latency over the
full timing path:

 - from the 40.08 MHz clock in the TTC VME crate,

 - through the VC-709 FELIX system

 - then through the GBT Receiver, PLL jitter cleaner,
   and Reference Clock Fanout on the Hub Module

 - then across the ATCA Shelf Backplane

 - and finally received on the HTM (FEX) card where
   it passes through a PLL jitter cleaner and is then
   delivered to the HTM FPGA and to a front panel
   clock monitor Lemo connector



Longer or Backup Explanation:
-----------------------------

The 40.08 MHz TTC Crate clock signal on the oscilloscope
(upper trace Ch 4)  comes from the front panel "Clock Out"
Lemo connector on the TTCvx module.  This is a copy of the
clock signal that directly controls the shifting out of
the TTC optical data stream from the TTCvx module.

The optical TTC data stream from the TTCvx module is
connected to an optical input on the VC-709 card that
operates as the FELIX system.

The optical FELIX version of the TTC data stream is
connected from an optical output on the VC-709 card to a
MiniPOD Receiver channel on the Hub Module in slot #1
of the ATCA Crate.

In the Hub Module a  FPGA  GBT receiver circuit recovers
the 40.08 MHz reference clock.  This reference clock is
immediately sent out of the Hub FPGA to a PLL jitter
cleaner.  From this jitter cleaner the 40.08 MHz reference
clock passes through a fanout from where it is distributed
to:  the Hub FPGA,  the ROD,  and to the 12 FEX slots via
the ATCA backplane.

An HTM card in a FEX slot receives this reference clock
from the backplane, passes it through a PLL jitter cleaner,
and then sends it to the HTM card FPGA and to a front panel
clock monitor Lemo connector.  The FEX reference clock
signal on the oscilloscope  (lower trace Ch 3)  comes from
this HTM clock monitor Lemo connector.



Future Tests:
-------------

We have the TTC VME crate programmed to issue L1-Accepts
at random locations in a turn of the LHC.   From a front
panel LEMO connector in the TTC setup we can see on the
oscilloscope when it issues a L1-Accept

Using the HTM Card's front panel "Access Signals"
(that come directly out of its FPGA)  we can see when
the L1-Accept is issued from the output of the 128 bit
wide D-Register  that is the last step in Pawel's
TTC / Readout Control  Combined Data  decoding FW that
runs in the HTM / FEX.

Thus in addition to the end-to-end Reference Clock latency
stability described above,  we can also see on the
oscilloscope when the L1-Accept is issued in the TTC Crate
and when that L1-Accept is issued from the D-Register at
the output of Pawel's Combined Data decoding FW.

Thus we can verify that there are always the same integer
number of 25 nsec periods between the generation of the
L1-Accept in the TTC VME Crate  to  issuing that L1-Accept
to the users of it in the FEX FW.