Tests  and  Scope pictures  of the

           Power Supplies  on the  Hub Module
          ------------------------------------


                                      Original Rev. 30-May-2017
                                       Current Rev.  3-Jun-2017


Initial tests on Hub Module SN 01  i.e. the card without an FPGA:


30-May-2017

  scope_hub_pwr_101_30may17.tif       4 msec per div

      Ch #1  Bulk_3V3
      Ch #2  FPGA_Core
      Ch #3  Fan_1V8

      This shows a Ramp-Up time for the FPGA supplies
      of about 4 msec.  The allowed range is:


  scope_hub_pwr_102_30may17.tif       4 msec per div

      Ch #1  Bulk_3V3
      Ch #2  FPGA_Core
      Ch #3  Bulk_1V8

      This shows all of the ramp controlled supplies
      ramping up in a volt per volt way.

      There is a  0.5 Ohm  load on the FPGA_Core rail.
      The Bulk_1V8 and Bulk_3V3 rails are loaded only
      by the components on the FPGA less  card.



31-May-2017

  scope_hub_pwr_103_31may17.tif      20 msec per div

      Ch #1  Bulk_3V3
      Ch #2  FPGA_Core
      Ch #3  Swch_1V2
      Ch #4  Swch_Reset_B     from U2963  pin 4

      Swch_1V2  turns ON about  80 msec  after the
      Bulk_3V3  supply has reached a valid level.


  scope_hub_pwr_104_31may17.tif     100 msec per div

      Ch #1  Bulk_3V3
      Ch #2  FPGA_Core
      Ch #3  Swch_1V2
      Ch #4  Swch_Reset_B     from U2963  pin 4

      Swch_Reset_B  is released about  560 msec  after the
      Swch_1V2  supply is turned ON.



1-June-2017

  scope_hub_pwr_105_1jun17.tif     100 msec per div

      Ch #1  Bulk_3V3
      Ch #2  First_Enable     from U2954  pin 8
      Ch #3  Swch_1V2
      Ch #4  Swch_Reset_B     from U2963  pin 4

      It is assumed that the  Iso_12V  reached a valid level
      about 400 msec before this scope trace begins.

      The  First_Enable  signal falls to a Low level and
      that enables all of the DCDC Converters except for
      the SWCH_1V2 converter,  i.e. DCDC-5

      120 msec later the Ramp Sequence starts up and you
      can see the Bulk_3V3 rail rise.

      120 msec later you can see the Swch_1V2 supply,
      i.e. DCDC-5  turn ON.

      560 msec later you can see that the Swch_Reset_B
      is released to Hi.


  scope_hub_pwr_106_1jun17.tif      20 usec per div

      Ch #1  MGT_AVTT     at C133 South of FPGA
      Ch #2  Load Box Pulse Signal

      This picture is looking at the stability of the
      MGT_AVTT  supply as its load is pulsed from 7.2 Amps
      up to 12.0 Amps at a 500 Hz rate.

      The 7.2 Amp static load is from 3 resistors of 0.5 Ohm.
      Two of these resistors are attached to MGT_AVTT
      capacitors on the North side of the FPGA and one
      of them is attached on the South side.

      The 4.8 Amps of pulse load comes from 2 more of
      the 0.5 Ohm resistors.  Both of these are attached
      on the South side of the FPGA.

      The scope monitoring of the MGT_AVTT rail is on
      the South side of the FPGA.



3-June-2017     Check noise on the Fan_1V8 supply

  On Hub SN-01 with all supplies running check the nose
  on the Fan_1V8 supply.  This is using the small coax with
  toroid chokes connected directly to a Fan_1V8 bypass
  capacitor at the bottom of the MGT Fanout array on the
  front side.  These are all single shot scope pictures.

  scope_hub_pwr_107_3jun17.tif       2 usec per div
  scope_hub_pwr_108_3jun17.tif      20 usec per div
  scope_hub_pwr_109_3jun17.tif     200 usec per div
  scope_hub_pwr_110_3jun17.tif       2 msec per div