DeCode of the Ostinato Packet from the Phys Chip -------------------------------------------------- Original Rev. 19-Jan-2018 Current Rev. 21-Jan-2018 General Setup: -------------- The Ethernet packet is generated by Ostinato on the Hubttc machine and monitored by WireShark which is also running on that machine. The Ethernet connection from Hubttc runs through a 100 Mbit/sec hub/switch and then a cable to the backplane of a vertical Hub card and then to the U21 Phys chip on that Hub card. The RGMII receiver output from U21 Phys is running at 25 Mhz Clock with data clocked by the rising edge of this clock (not double edge clocked). The Rx_Ctrl, Rx_D0, Rx_D1, and Rx_Clk are monitored in one set of scope pictures while the Rx_Ctrl, Rx_D2, Rx_D3, and Rx_Clk are monitored in a second set of scope pictures. Both sets of scope pictures are taken under the exact same conditions - specifically sweep delay conditions. A number of pictures with different delays are needed to capture the full Ethernet packet. The vertical cursors (separated by 880 nsec aka 22 clocks) are used to mark the last clock at the right of picture N that matches the first clock at the left of picture N+1. Phys Chip Rx Signals vs Scope Channels: --------------------------------------- Scope Ch d0d1 Files d2d3 Files -------- ---------- ---------- 1 Rx_Ctrl Rx_Ctrl 2 Rx_D0 Rx_D2 3 Rx_D1 Rx_D3 4 Rx_Clk Rx_Clk List of the Scope Images: ------------------------- d0d1_setup_hold_.png --- d0d1_1st__396.8_.png d2d3_1st__396.8_.png d0d1_2nd_1084.8_.png d2d3_2nd_1084.8_.png d0d1_3rd_1962.8_.png d2d3_3rd_1962.8_.png d0d1_4th_2844.8_.png d2d3_4th_2844.8_.png d0d1_5th_3722.8_.png d2d3_5th_3722.8_.png d0d1_6th_4604.8_.png d2d3_6th_4604.8_.png d0d1_7th_5482.8_.png d2d3_7th_5482.8_.png d0d1_8th_one___5684.8_.png d2d3_8th_one___5684.8_.png d0d1_8th_two___5684.8_.png d2d3_8th_two___5684.8_.png d0d1_8th_three_5684.8_.png d2d3_8th_three_5684.8_.png d0d1_8th_four__5684.8_.png d2d3_8th_four__5684.8_.png d0d1_8th_five__5684.8_.png d2d3_8th_five__5684.8_.png Ostinato Packet Data as seen by WireShark: ------------------------------------------ da 08 02 03 04 05 5a 01 02 03 04 05 ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ef ee ed ec eb ea e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 -- -- -- -- 60 db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf -- -- -- 61 db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce -- -- 62 db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce cd -- 63 db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce cd cc 64 The first 48 bytes, i.e the first 3 lines of 16 bytes each, are always the same. The final line of bytes varies in length between 12 and 16. protocol: 0x fffe length: 60, 61, 62, 63, 64 different packets show different length Info: Ethernet II Setup and Hold Time measured in the file: d0d1_setup_hold_.png --------------------------------------------------------------- The Setup time is about 13.6 nsec The Hold time is about 26.4 nsec WireShark Packet Contents vs RGMII Packet Data: ------------------------------------------------- The WireShark display seems to show just: Destination MAC Address Source MAC Address Length/Type Payload The RGMII data from the Hub Phys Chip shows: InBand Status between Packets Rx_DV goes HI Full 16 byte Preamble with Start bit Destination MAC Address 6 bytes Source MAC Address 6 bytes Length/Type Payload CRC-32 8 bytes Rx_DV goes LOW InBand Status between Packets Recall that the CRC-32 is generated and checked in the MAC level of the stack and thus the 8 byte CRC-32 is passed between the Phys Chip and the MAC.