# # Clock Generation and Distribution # # Hub Module Key In Components File # ------------------------------------- # # # Original Rev. 15-Apr-2015 # Most Recent Rev. 26-Oct-2016 # # # This Comps file holds all of the components for the # Clock Generation and Distribution on the Hub Module. # # - The first major section of this comps file is the # 25 MHz Clock for all of the Ethernet circuits: # Switches, Phys, FPGA MACs. # # - The second major section of this comps file is the # 40.08 MHz and 320.64 MHz LHC Locked Clocks for the # Hub FPGA Logic and the Reference for the MGT # Transceivers. # # # # 25.000 MHz Clock Generation and Distribution Chips # # - Components for the 25 MHz Clock Oscillator and its # 6x Fanout Buff that feeds the 25 MHz clock to the: # # 3x Switch Chips # 1x FPGA # 2x Phys Chips # # - All outputs from the 1 to 6 fanout have series # terminator resistors. # U38 IC_CWX_813_25_MHz SY_JUNK OSC_25_MHz 31.00 60.00 1 0 U39 IC_TI_CDCLVC1106 SY_JUNK tssop_14 41.50 61.50 1 0 L391 Wurth_742792116 SY_JUNK Wurth_1206_Ind 30.20 68.00 1 180 C391 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 36.50 68.00 2 180 C392 Cap_100_nFd_0603 SY_JUNK cap_0603 29.30 65.50 1 0 C393 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 31.00 60.00 2 180 C394 Cap_100_nFd_0603 SY_JUNK cap_0603 41.50 57.00 1 180 C395 Cap_220_nFd_0603 SY_JUNK cap_0603 41.50 66.00 1 0 # # Now the Ethernet 25 MHz Clock Series Terminator Resistors: # # 3x to the Switch Chips, 1x to the FPGA, 2x to the Phys Chips # R501 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 66.50 1 0 R1916 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 64.50 1 0 R1966 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 62.50 1 0 R2119 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 60.50 1 180 R2019 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 58.50 1 180 R2219 Res_22_Ohm_0603 SY_JUNK res_0603 49.00 56.50 1 180 # # # ***** Now start the second major section of this comps file. ***** # ***** ***** # ***** the 40.08 MHz and 320.64 MHz LHC Locked Clocks ***** # # # IC components for the 48.08 MHz and 320.64 MHz Clock Generation: # U501 IC_65LVDT2 SY_JUNK sot_23_5 88.00 93.90 1 270 U502 IC_PLL_40M0787 SY_JUNK Connor_SFX 98.10 91.00 1 0 U503 IC_CDCLVD1204 SY_JUNK qfn_16_ti 135.00 87.00 1 270 U504 IC_CDCLVD1216 SY_JUNK qfn_48 173.50 118.00 1 0 U505 IC_65LVDT2 SY_JUNK sot_23_5 146.50 88.20 1 270 U506 IC_PLL_320M6296 SY_JUNK Connor_SFX 156.50 89.00 1 0 U507 IC_MC100LVEP111 SY_JUNK qfn_32 160.50 138.40 1 180 # # Series terminate the output of the two LVDS Clock Receivers. # R1607 Res_49R9_Ohm_0603 SY_JUNK res_0603 89.30 86.50 1 270 R1608 Res_49R9_Ohm_0603 SY_JUNK res_0603 147.70 83.90 1 270 # # Isolation resistors for the two Lock Detect signals # from the PLLs to the Hub FPGA. # R1609 Res_4.99k_Ohm_0603 SY_JUNK res_0603 92.00 100.20 1 180 R1610 Res_4.99k_Ohm_0603 SY_JUNK res_0603 146.70 94.30 1 180 # # Input RCs for the FIRST 40.08 MHz Fanout # -=====-------------------- # # Input AC Coupling Capacitors and Series Back Terminator Resistors # We use the Back Terminators to get from LVPECL swing to LVDS Diff Swing. R1613 Res_49R9_Ohm_0603 SY_JUNK res_0603 122.50 87.90 1 0 R1614 Res_49R9_Ohm_0603 SY_JUNK res_0603 122.50 86.10 1 0 C1651 Cap_47_nFd_0402 SY_JUNK cap_0402 130.30 87.60 1 0 C1652 Cap_47_nFd_0402 SY_JUNK cap_0402 130.30 86.40 1 0 # Terminator Resistors for the FIRST 40.08 MHz Fanout R1615 Res_49R9_Ohm_0603 SY_JUNK res_0603 129.70 87.90 2 0 R1616 Res_49R9_Ohm_0603 SY_JUNK res_0603 129.70 86.10 2 0 # ByPass Capacitor for the Input Reference on FIRST 40.08 MHz Fanout C374 Cap_100_nFd_0603 SY_JUNK cap_0603 129.70 84.30 2 180 # Input Select for the FIRST 40.08 MHz Fanout R1611 Res_1k_Ohm_0603 SY_JUNK res_0603 135.40 91.50 1 90 # Resistor to Tie off the unused IN #1 input to the 40.08 MHz Fanout R1620 Res_1k_Ohm_0603 SY_JUNK res_0603 133.60 91.50 1 90 # # Input RCs for the SECOND 40.08 MHz Fanout # -======-------------------- # # Input AC Coupling Capacitors C1655 Cap_47_nFd_0402 SY_JUNK cap_0402 165.60 115.80 1 0 C1656 Cap_47_nFd_0402 SY_JUNK cap_0402 165.60 117.20 1 0 # Terminator Resistors for the SECOND 40.08 MHz Fanout R1601 Res_49R9_Ohm_0603 SY_JUNK res_0603 165.00 115.50 2 0 R1602 Res_49R9_Ohm_0603 SY_JUNK res_0603 165.00 117.50 2 0 # ByPass Capacitor for the Input Reference on SECOND 40.08 MHz Fanout C372 Cap_100_nFd_0603 SY_JUNK cap_0603 165.00 119.50 2 180 # Input Selec aka Output Disable for the SECOND 40.08 MHz Fanout R1617 Res_4.99k_Ohm_0603 SY_JUNK res_0603 166.10 123.10 1 180 R1618 Res_4.99k_Ohm_0603 SY_JUNK res_0603 166.10 121.20 1 180 # Tie Off Resistor for the IN #1 Pos of the SECOND 40.08 MHz Fanout R1619 Res_1k_Ohm_0603 SY_JUNK res_0603 169.20 127.00 1 90 # # Input RCs for the 320.64 MHz Fanout # -------------------- # # Input AC Coupling Capacitors C1653 Cap_47_nFd_0402 SY_JUNK cap_0402 164.90 131.60 1 90 C1654 Cap_47_nFd_0402 SY_JUNK cap_0402 166.10 131.60 1 90 # Terminator Resistors for the Input to the 320.64 MHz Fanout R1603 Res_49R9_Ohm_0603 SY_JUNK res_0603 164.60 131.00 2 270 R1604 Res_49R9_Ohm_0603 SY_JUNK res_0603 166.40 131.00 2 270 # Resistors to set the Common Mode Voltage at this Input R1605 Res_1k_Ohm_0603 SY_JUNK res_0603 168.60 133.10 2 270 R1606 Res_1k_Ohm_0603 SY_JUNK res_0603 170.50 133.10 2 270 # Bypass Capacitor for this Common Mode Control Voltage C373 Cap_100_nFd_0603 SY_JUNK cap_0603 169.40 130.20 2 180 # Input Select R1612 Res_1k_Ohm_0603 SY_JUNK res_0603 162.50 131.00 1 270 # # Now for the AC Coupling capacitors in the 40.08 MHz # Clock Signals to the Zone 2 Backplane and thus to # the 12 FEX Cards and to the Other Hub. # # Y deltas 1.2 mm within a diff pair # 5.0 mm between diff pairs # # Notes: I assume that the backplane to capacitor # traces will route out of the backplane # Below the connected row. # # I assume that I will route 3 differential # clock pairs between rows of FEX FanOut. # # # FEX_14 is at the top of this list. # ... # FEX_03 is next to the bottom of this list. # Other_Hub is at the bottom of this list. # C1626 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 152.60 1 0 C1625 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 151.40 1 0 C1624 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 147.60 1 0 C1623 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 146.40 1 0 C1622 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 142.60 1 0 C1621 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 141.40 1 0 C1620 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 137.60 1 0 C1619 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 136.40 1 0 C1618 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 132.60 1 0 C1617 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 131.40 1 0 C1616 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 127.60 1 0 C1615 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 126.40 1 0 C1614 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 122.60 1 0 C1613 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 121.40 1 0 C1612 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 117.60 1 0 C1611 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 116.40 1 0 C1610 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 112.60 1 0 C1609 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 111.40 1 0 C1608 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 107.60 1 0 C1607 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 106.40 1 0 C1606 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 102.60 1 0 C1605 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 101.40 1 0 C1604 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 97.60 1 0 C1603 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 96.40 1 0 C1602 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 92.60 1 0 C1601 Cap_47_nFd_0402 SY_JUNK cap_0402 254.00 91.40 1 0 # # Now for the AC Coupling capacitors for the 40.08 MHz # Clock Signals to the ROD Mezzanine on This Hub Module. # C1628 Cap_47_nFd_0402 SY_JUNK cap_0402 141.20 90.20 1 90 C1627 Cap_47_nFd_0402 SY_JUNK cap_0402 142.40 90.20 1 90 # # Now for the AC Coupling capacitors for the 40.08 MHz # Logic Clock Signals to the Virtex FPGA on This Hub Mdoule. # C1630 Cap_47_nFd_0402 SY_JUNK cap_0402 138.30 90.20 1 90 C1629 Cap_47_nFd_0402 SY_JUNK cap_0402 139.50 90.20 1 90 # # Now for the Pull-Down Resistors and Coupling Capacitors # for the LVPECL 320.64 MHz Clock Signals # # to the MGT Reference Clock inputs 8x # and to the Hub FPGA 320 MHz Logic Clock input 1x R1639 & R1640. # # Both Rs and Cs are on the Top Side for direct connection # to the 320.64 MHz Fanout Chip. # # For the Rs: # Delta Y within a pair is 1.8 mm # The unit cell is 3.2 mm --> 1.4 mm between Cs in adjacent pairs # # For the Cs: # Delta Y within a pair is 1.2 mm # The unit cell is 3.2 mm --> 2.0 mm between Cs in adjacent pairs # # These RCs are shoved as far to the West as possible, # i.e. right up against the power distribution Area Fills. # This is so that as little as possible of the 320.64 MHz # fanout chip is covering the MGT traces running up to the ROD. # # Note that the 320.64 MHz "Logic" clock connection to a # Global Clock Input in HP IO Bank 71 is Special. These # are AC coupled LVPECL signals with a typical swing of # 750 mV. This is perfect for the MGT Reference Clock Inputs # but is more than the maximum reccommended swing of 600 mV # for the HP IO Bank LVDS input. The solution is to back # terminate the 320.64 MHz Fanout output that goes to the # HP IO Bank Global Logic Clock input. Just this one Fanout # output is back terminated. Resistors R1651 and R1652 # are the back termination resistors for the HP IO Bank input. # R1648 Res_150_Ohm_0402 SY_JUNK res_0402 156.10 153.70 1 180 R1647 Res_150_Ohm_0402 SY_JUNK res_0402 156.10 151.90 1 180 R1646 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 150.50 1 180 R1645 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 148.70 1 180 R1644 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 147.30 1 180 R1643 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 145.50 1 180 R1642 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 144.10 1 180 R1641 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 142.30 1 180 R1640 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 140.90 1 180 R1639 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 139.10 1 180 R1638 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 137.70 1 180 R1637 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 135.90 1 180 R1636 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 134.50 1 180 R1635 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 132.70 1 180 R1634 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 131.30 1 180 R1633 Res_150_Ohm_0402 SY_JUNK res_0402 154.00 129.50 1 180 R1632 Res_150_Ohm_0402 SY_JUNK res_0402 156.10 128.10 1 180 R1631 Res_150_Ohm_0402 SY_JUNK res_0402 156.10 126.30 1 180 C1648 Cap_47_nFd_0402 SY_JUNK cap_0402 153.80 153.40 1 0 C1647 Cap_47_nFd_0402 SY_JUNK cap_0402 153.80 152.20 1 0 C1646 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 150.20 1 0 C1645 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 149.00 1 0 C1644 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 147.00 1 0 C1643 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 145.80 1 0 C1642 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 143.80 1 0 C1641 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 142.60 1 0 C1640 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 140.60 1 0 C1639 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 139.40 1 0 C1638 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 137.40 1 0 C1637 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 136.20 1 0 C1636 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 134.20 1 0 C1635 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 133.00 1 0 C1634 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 131.00 1 0 C1633 Cap_47_nFd_0402 SY_JUNK cap_0402 151.70 129.80 1 0 C1632 Cap_47_nFd_0402 SY_JUNK cap_0402 153.80 127.80 1 0 C1631 Cap_47_nFd_0402 SY_JUNK cap_0402 153.80 126.60 1 0 # # Back Terminators for the HP IO Bank Global Logic Clock 320.64 MHz Input # R1652 Res_49R9_Ohm_0603 SY_JUNK res_0603 148.00 140.80 1 180 R1651 Res_49R9_Ohm_0603 SY_JUNK res_0603 148.00 139.20 1 180 # # Power Input Filter Inductors and Capacitors # for the 40.08 MHz and 320.64 MHz Clocks: # # CLK_3V3 Power Filter C351 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 79.10 99.50 2 180 L351 Wurth_744311470 SY_JUNK Wurth_6969_Ind 80.50 95.50 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA11_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 77.90 97.40 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA12_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 75.90 95.50 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA13_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 77.90 93.60 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA14_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 83.10 97.40 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA15_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 81.00 95.50 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA16_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 83.10 93.60 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") # CLK_2V5 Power Filter WTERM52 Not_a_Part SY_JUNK Wrap_3mm0 174.50 86.00 1 0 C352 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 174.50 89.80 2 90 L352 Wurth_744311470 SY_JUNK Wurth_6969_Ind 168.50 88.50 1 90 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA1_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 166.60 91.10 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA2_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 170.40 91.10 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA3_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 168.50 89.00 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") PVA4_CLK Not_a_Part SY_JUNK x1y1_Power_Via_Array 166.60 86.00 1 0 ($G,"$O,$V") (COMPONENT_TYPE,"Array_Grp") # # Power Bypass Capacitors for the CLK_3V3 supply: # to the two LVDS Receivers: U501 and U505 # to the two ConWin PLLs: U502 and U506. # C353 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 93.70 91.30 2 270 C354 Cap_220_nFd_0603 SY_JUNK cap_0603 97.20 91.60 2 270 C355 Cap_47_nFd_0402 SY_JUNK cap_0402 95.60 92.10 2 270 C356 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 152.10 89.30 2 270 C357 Cap_220_nFd_0603 SY_JUNK cap_0603 155.60 89.60 2 270 C358 Cap_47_nFd_0402 SY_JUNK cap_0402 154.00 90.10 2 270 C370 Cap_100_nFd_0603 SY_JUNK cap_0603 88.20 97.70 2 0 C371 Cap_100_nFd_0603 SY_JUNK cap_0603 146.70 92.00 1 180 # # Power Bypass Capacitors for the CLK_2V5 supply # to the three Fanout Chips: U503, U504, U507 # to the three Diff Common Mode Ref Supplies # at the input to these fanout chips. # # 40.08 Mhz FIRST Fanout U504 C375 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 129.90 91.00 2 90 C376 Cap_220_nFd_0603 SY_JUNK cap_0603 133.30 90.80 2 90 C377 Cap_47_nFd_0402 SY_JUNK cap_0402 134.70 88.50 2 180 # 40.08 Mhz SECOND Fanout U504 C359 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 168.60 115.30 2 270 C360 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 168.60 120.70 2 90 C361 Cap_220_nFd_0603 SY_JUNK cap_0603 176.90 116.30 2 90 C362 Cap_220_nFd_0603 SY_JUNK cap_0603 176.90 119.70 2 270 C363 Cap_47_nFd_0402 SY_JUNK cap_0402 171.20 120.90 2 270 C364 Cap_47_nFd_0402 SY_JUNK cap_0402 171.20 115.10 2 90 # 320.64 MHz Fanout U507 C365 Cap_10_uFd_10_V_0805 SY_JUNK cap_0805 163.90 138.40 2 0 C366 Cap_220_nFd_0603 SY_JUNK cap_0603 161.50 141.30 2 270 C367 Cap_220_nFd_0603 SY_JUNK cap_0603 161.50 135.50 2 90 C368 Cap_47_nFd_0402 SY_JUNK cap_0402 159.30 136.00 2 90 C369 Cap_47_nFd_0402 SY_JUNK cap_0402 159.30 140.80 2 270