#
#                          Virtex  FPGA
#
#                 Key In Components File  for the
#                 HUB-0   ATLAS L1Calo Hub Module
#              ---=====-----------------------------
#
#                                                 Original Rev.  15-Mar-2015
#                                              Most Recent Rev.  21-Oct-2016
#
#
#   This file holds all of the Virtex FPGA components on the
#   Hub Module.  This includes the FPGA itself and all of the
#   components that are directly associated with the FPGA.
#
#   - First include all of the FPGA Bypass Capacitors
#     that are located adjacent to the Virtex FPGA:
#
#        FPGA_CORE
#        Bulk_1V8
#        MTG_AVCC
#        MTG_AVTT
#        MTG_AVAUX
#
#
#  - Now include the  Digitally Controlled Impedance  DCI
#    calibration resistors  240 Ohm  from the  VRP  pins
#    to Ground.
#
#        We have these for HP Banks: 65, 66, 67, 68.
#
#        We do not include them for the unused HP Banks: 70, 71, 72.
#
#        The DCI VRP pins do not exist for the HR Banks: 84, 94.
#
#
#  - Now include the  pull-down  resistors on the  VREF  pins
#    that are required for any Select I/O Bank that uses an
#    I/O standard that uses a differential input buffer and
#    uses an internal source of VREF  (VREF_Internal or VREF_Scan).
#    These are 1k Ohm from the VREF pin to Ground.
#
#        We have these for the HP Banks:  65, 66, 67, 68.
#
#        We do not have these for the unused HP Banks: 70, 71, 72.
#
#        We have these for the HR Banks: 84, 94.
#
#
#  - Now includ the required MGT Termination Calibration Resistors
#    for the GTH and GTY transceivers.   Thsese 100 Ohm from the
#    MGTRREF pin to the MGTAVTTCAL pin and then to the MGTAVTT pin.
#
#        We need all 4 of these MGT Calibration Resistors
#        that are located near Quads:  125, 130, 226, 231.
#
#
#  - Note that on 25-Aug-16 this file was divided into two sections,
#    i.e. the original file and a standard non-rpcs file.
#
#  - Note that as of 21-Oct-2016 all of the components that had been
#    in this file,  except for the FPGA itself and its Heat-Sink,
#    have been moved to the standard non-rpcs section of the FPGA
#    comps file.
#
#



#
#                                                       Board_Location
# Ref    Part_Number   Symbol     Geometry                 X       Y     Properties
#-----   -----------   ------   ------------------      --------------   ----------
#

#
#    Hub Virtex FPGA Comps  -  Now with the xvu125 Ultra-Scale FPGA
#

U1   IC_XCVU125   SY_JUNK   FLVC_2104_Geom       0.00   0.00   1  270   ($G,"$O,$V") (COMPONENT_TYPE,"Mech_Comp")



#
#    Hub FPGA Heat Sink
#

HS1   FPGA_Heat_Sink   SY_JUNK   HEAT_SINK_HUB   0.00   0.00   1    0   ($G,"$O,$V") (COMPONENT_TYPE,"Mech_Comp")