// // // // Shape Edit Section of the // -==========----------------- // // Hub Module Printed Circuit Board Geometry File // -------------------------------------------------- // // // Area Fills on Signal Layer 11 <--- // ---------------------------==== // // // // Original Rev. 3-Feb-2016 // Current Rev. 12-Jan-2017 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed on Signal_11 // are: FPGA_CORE and MGT_AVCC. // // - These fills are kept back at least 4.5 mm from the // top and bottom edges so that the area fills will not be // exposed when the top and bottom edges are milled to // allow this card to fit into the crate card guides. // // - These fills are kept back at least 1mm from the front // and back edges to comply with normal decorum. // // - EVERYTHING in this Signal_11 fill file is repeated // on both the layers: SHAPE_EDIT and DIELECTRIC_1. // See the bottom section of this file. // // - As of 17-Oct-2016 there are 22 shapes defined in this file. // // - List of Fills in this file: // // FPGA_CORE: From the DCDC_1 Converter to FPGA Medium Res // Under the FPGA Hi Res // // MGT_AVCC: From the DCDC_2 Converter to FPGA Medium Res // Under the FPGA Hi Res // // FAN_1V8: // // ISO_12V: // // Individual Switch AVDDL: Under each Switch Chip, a fill for // that Switch's Filtered AVDDL supply // // Individual Phys DVDDL: Under each Phys Chip, a fill for // that Phys's Filtered DVDDL supply // // CLK_3V3: // // // - Currently many sections of the ISO_12V fills on Signal_11 and // Signal_12 have exactly the same Shape pattern. // // NOTE: For those sections of the overall ISO_12V fill that have // exactly the same Shape on Signal_11 and Signal_12, I'm // only generating this Shape in the Signal_11 Shape // source file. I'm not repeating it in the // Signal_12 Shape source file. That is, some of the // ISO_12V fills on both layers Sig_11 and Sig_12 will // be based on the Shapes that come from the Sig_11 Shape // source file. // // I do not want to risk confusion by having two copies // of exactly the same Shape in the Hub design. // // There is no point in needing to edit both the Sig_11 // and Sig_12 files to make a change in the ISO_12V fills. // // - The corners of the shapes in this file that sould not // be mitered are marked with the comment text, "NO_MITER". // // // // // Net: FPGA_CORE // // Fill Layer: Signal_11 // // Location: From Converter DCDC_1 to the FPGA // // Resolution: Medium // $$initial([ 78.5, 207.4 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 45.5, 207.4 ] ); // Go West across the Top $$terminal([ 45.5, 134.3 ] ); // NO_MITER Go Down most of the West edge $$terminal([ 64.8, 115.0 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 91.2, 115.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 91.2, 194.7 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 78.5, 207.4 ] ); // NO_MITER Go 45 deg to the NW and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: FPGA_CORE // // Fill Layer: Signal_11 // // Location: FPGA_CORE Pins under the FPGA // // Resolution: Hi // $$initial([ 89.5, 176.1 ], , @nosnap ); // NO_MITER Start in the NW corner and go CCW $$terminal([ 89.5, 115.0 ] ); // NO_MITER Go Down the West edge $$terminal([ 102.8, 115.0 ] ); // Go a East coming out of the overlap $$terminal([ 102.8, 126.6 ] ); // NO_MITER Go North into the pin array $$terminal([ 106.4, 130.2 ] ); // NO_MITER Go about 45 deg to the NE $$terminal([ 129.8, 130.2 ] ); // Go East Across the Bottom of the FPGA Core pins $$terminal([ 129.8, 149.8 ] ); // Go Up the East edge of the FPGA Core pins $$terminal([ 106.4, 149.8 ] ); // NO_MITER Go West across the Top of the FPGA Core pins $$terminal([ 102.8, 153.4 ] ); // NO_MITER Go about 45 deg to the NW $$terminal([ 102.8, 166.3 ] ); // NO_MITER Go North up through the pin array $$terminal([ 96.1, 173.0 ] ); // NO_MITER Go 45 deg North West $$terminal([ 92.6, 173.0 ] ); // NO_MITER Go West $$terminal([ 89.5, 176.1 ] ); // NO_MITER Go 45 deg North West and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVCC // // Fill Layer: Signal_11 // // Location: DCDC_2 Output Filter Choke to FPGA // // Resolution: Medium // $$initial([ 126.0, 200.5 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 104.0, 200.5 ] ); // Go West across the Top $$terminal([ 104.0, 195.0 ] ); // NO_MITER Go Down a small West Edge $$terminal([ 91.8, 192.0 ] ); // NO_MITER Go about 45 deg to the SW $$terminal([ 91.8, 173.4 ] ); // Go South $$terminal([ 96.3, 173.4 ] ); // NO_MITER Go West $$terminal([ 103.2, 166.5 ] ); // NO_MITER Go 45 deg SW $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 91.8, 113.5 ] ); // NO_MITER Go West $$terminal([ 91.8, 100.0 ] ); // Go South $$terminal([ 107.5, 100.0 ] ); // NO_MITER Run East over to just before C91 $$terminal([ 113.0, 94.5 ] ); // NO_MITER Run 45 deg SE to pick up C91 $$terminal([ 119.5, 94.5 ] ); // NO_MITER Run East under C91 $$terminal([ 125.0, 100.0 ] ); // NO_MITER Run 45 deg NE back up to normal Y $$terminal([ 156.5, 100.0 ] ); // Go Finish running East Across the Bottom $$terminal([ 156.5, 186.0 ] ); // NO_MITER Go Up the East edge of the fill $$terminal([ 126.0, 195.0 ] ); // NO_MITER Go about 45 deg to the NW $$terminal([ 126.0, 200.5 ] ); // Go Up the East edge to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVCC // // Fill Layer: Signal_11 // // Location: MGT_AVCC Pins under the FPGA // // Resolution: Hi // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 103.2, 167.0 ] ); // NO_MITER Go West across the Top $$terminal([ 103.2, 153.6 ] ); // NO_MITER Go South $$terminal([ 106.6, 150.2 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 130.2, 150.2 ] ); // Go East under the FPGA AVCC pins $$terminal([ 130.2, 129.8 ] ); // Go South just East of the Core supply finger $$terminal([ 106.6, 129.8 ] ); // NO_MITER Go West above the FPGA AVCC pins $$terminal([ 103.2, 126.4 ] ); // NO_MITER Go about 45 Deg to the SW $$terminal([ 103.2, 114.6 ] ); // Go South $$terminal([ 91.8, 114.6 ] ); // Go West $$terminal([ 91.8, 113.0 ] ); // NO_MITER Go South $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go Up the East edge and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: FAN_1V8 // // Fill Layer: Signal_11 // // Location: DCDC_7 Output Filter and area under the FEX Data Fanout // // Resolution: Medium // $$initial([ 260.0, 204.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 180.5, 204.0 ] ); // Go far West across all of the Top $$terminal([ 180.5, 138.0 ] ); // Go Soouth along the West side until // we need to start the jog part way East $$terminal([ 192.0, 138.0 ] ); // Go East to get inside of the Eq Enb Ctrl $$terminal([ 192.0, 67.5 ] ); // Go South down the the rest of the West edge $$terminal([ 234.0, 67.5 ] ); // NO_MITER Go East across Part of the Bottom // to pick up some bypass capacitors $$terminal([ 238.5, 72.0 ] ); // NO_MITER Go NE at 45 Deg to get above // the worst of the Ethernet stuff. $$terminal([ 259.0, 72.0 ] ); // Go East across the rest of the Bottom $$terminal([ 259.0, 174.5 ] ); // NO_MITER Go North up the East edge $$terminal([ 262.0, 177.5 ] ); // NO_MITER Go NE at 45 degrees $$terminal([ 262.0, 193.0 ] ); // NO_MITER Go part way up the East edge $$terminal([ 260.0, 195.0 ] ); // NO_MITER Jog back NW at 45 deg to clear TRNS4 $$terminal([ 260.0, 204.0 ] ); // Go Up the East edge to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: AVDDL_FLTR_A // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "A" aka U31 // // Resolution: Medium or HI // $$initial([ 141.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 110.0, 82.0 ] ); // Go West across the Top $$terminal([ 110.0, 48.7 ] ); // Go Down the West edge $$terminal([ 141.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 141.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: AVDDL_FLTR_B // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "B" aka U32 // // Resolution: Medium or HI // $$initial([ 91.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 60.0, 82.0 ] ); // Go West across the Top $$terminal([ 60.0, 48.7 ] ); // Go Down the West edge $$terminal([ 91.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 91.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: AVDDL_FLTR_C // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "C" aka U33 // // Resolution: Medium or HI // $$initial([ 184.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 153.0, 82.0 ] ); // Go West across the Top $$terminal([ 153.0, 48.7 ] ); // Go Down the West edge $$terminal([ 184.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 184.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: Phys_U21_DVDDL // // Fill Layer: Signal_11 // // Location: DVDDL Fill under Phys Chip U21 // // Resolution: HI // $$initial([ 60.0, 119.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 51.8, 119.0 ] ); // Go West across the Top $$terminal([ 51.8, 105.2 ] ); // Go Down the West edge $$terminal([ 61.0, 105.2 ] ); // Go East Across the Bottom $$terminal([ 61.0, 118.0 ] ); // NO_MITER Go Up the East edge part way $$terminal([ 60.0, 119.0 ] ); // NO_MITER Go NW 45 deg and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: Phys_U22_DVDDL // // Fill Layer: Signal_11 // // Location: DVDDL Fill under Phys Chip U22 // // Resolution: HI // $$initial([ 61.0, 101.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 51.8, 101.0 ] ); // Go West across the Top $$terminal([ 51.8, 87.2 ] ); // Go Down the West edge $$terminal([ 61.0, 87.2 ] ); // Go East Across the Bottom $$terminal([ 61.0, 101.0 ] ); // Go Up the East edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: CLK_3V3 // // Fill Layer: Signal_11 // // Location: CLK_3V3 Fill under Clock Generator PLLs U502 and U506 // // Resolution: Medium ? // $$initial([ 79.0, 99.0 ], , @nosnap ); // Start in the NW corner and go CCW $$terminal([ 79.0, 83.0 ] ); // Go Down the West edge $$terminal([ 164.0, 83.0 ] ); // Go East across the Bottom $$terminal([ 164.0, 99.0 ] ); // Go Up the East edge $$terminal([ 125.0, 99.0 ] ); // NO_MITER Run West over to just before C91 $$terminal([ 120.0, 94.0 ] ); // NO_MITER Run 45 deg SW to avoid C91 $$terminal([ 112.5, 94.0 ] ); // NO_MITER Run West under C91 $$terminal([ 107.5, 99.0 ] ); // NO_MITER Run 45 deg NW back up to normal Y $$terminal([ 79.0, 99.0 ] ); // Finish running West across the Top edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: CNST_5V0 // // Fill Layer: Signal_11 // // Location: North-West corner of the card // // Resolution: Medium // $$initial([ 112.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 23.0, 316.0 ] ); // Go West $$terminal([ 23.0, 296.0 ] ); // Go South $$terminal([ 98.0, 296.0 ] ); // NO_MITER Go part way back East $$terminal([ 112.0, 310.0 ] ); // NO_MITER Go 45 deg NE cutting the corner // to give more space for ISO_12V $$terminal([ 112.0, 316.0 ] ); // Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Start the ISO_12V Shapes on Signal_11 // // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Isolated +12V from its ATCA Module // to the Input Filter Capacitors for the DCDC Converters // // NOTES: 8 of the following Shapes are used to generate the // ISO_12V Fills on both pcb layers Sig_11 and Sig_12. // // Resolution: Medium // $$initial([ 293.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 113.0, 316.0 ] ); // Go West across part of the Top $$terminal([ 113.0, 309.3 ] ); // NO_MITER Go South to clear the CNST_5V0 fill $$terminal([ 98.7, 295.0 ] ); // NO_MITER Go 45 deg SW to clear the CNST_5V0 $$terminal([ 49.0, 295.0 ] ); // Go West across the rest of the Bulk Input Filter $$terminal([ 49.0, 263.0 ] ); // Go South down past some of the Bulk Input Filter $$terminal([ 1.0, 263.0 ] ); // Go East out to the Front Panel $$terminal([ 1.0, 134.0 ] ); // Go South to the top of the RJ45 Cut Out $$terminal([ 8.0, 134.0 ] ); // Go East to clear the Cut Out for the RJ45s $$terminal([ 8.0, 70.0 ] ); // Go South past the RJ45 Cut Out $$terminal([ 1.0, 70.0 ] ); // Go West back out to the Front Panel $$terminal([ 1.0, 11.0 ] ); // Go South to the top of the lower Front Panel Mount $$terminal([ 9.0, 11.0 ] ); // Go East to clear the lower Front Panel Mount $$terminal([ 9.0, 4.5 ] ); // Go South to pick up the C964 connection $$terminal([ 50.0, 4.5 ] ); // NO_MITER Go East so we can pickup all of the Iso 12V Caps $$terminal([ 50.0, 35.0 ] ); // NO_MITER Go North to pick up these Modules Output Caps $$terminal([ 44.5, 35.0 ] ); // Go West to setup the X for the run north $$terminal([ 44.5, 219.0 ] ); // NO_MITER Go North up to the area of the Bulk Input Filter $$terminal([ 130.0, 219.0 ] ); // Go East along the lower border of the Bulk Input Caps $$terminal([ 130.0, 284.5 ] ); // NO_MITER Go North between Bulk Input Caps and MegArray #1 $$terminal([ 256.0, 284.5 ] ); // Go East over to the smaller group of Bulk Input Caps $$terminal([ 256.0, 215.5 ] ); // NO_MITER Go South past the west border of // this smaller grp of Caps $$terminal([ 293.0, 215.5 ] ); // Go East to pick up the starting X $$terminal([ 293.0, 316.0 ] ); // Go Up the East edge of these Caps to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Finger to pick up the DCDC_5 Converter and its Caps // // Resolution: Medium // $$initial([ 179.0, 4.5 ], , @nosnap ); // Start in the SE corner $$terminal([ 179.0, 14.7 ] ); // Go Up the East edge of DCDC_5 $$terminal([ 167.2, 14.7 ] ); // NO_MITER Go West part way across the top of DCDC_5 $$terminal([ 159.8, 22.1 ] ); // NO_MITER Go 45 deg NW $$terminal([ 155.5, 22.1 ] ); // Go West under the Input module pin $$terminal([ 155.5, 27.2 ] ); // Go North to get more Cu on west side of pins. $$terminal([ 145.0, 27.2 ] ); // Go West under Entry module and get more heigth $$terminal([ 143.5, 28.7 ] ); // Go North up past an input module pin $$terminal([ 114.0, 28.7 ] ); // Go West thru most of the Power Entry Module $$terminal([ 114.0, 35.0 ] ); // Go North $$terminal([ 49.0, 35.0 ] ); // NO_MITER Go West to make an overlap $$terminal([ 49.0, 4.5 ] ); // NO_MITER Go South past the Iso 12V connection $$terminal([ 179.0, 4.5 ] ); // Go East back to the DCDC5 Conv and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_1 Converter and its Caps // // Resolution: Medium // $$initial([ 58.0, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 43.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 43.5, 208.5 ] ); // NO_MITER Go South $$terminal([ 58.0, 208.5 ] ); // Go East $$terminal([ 58.0, 220.0 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_2 Converter and its Caps // // Resolution: Medium // $$initial([ 92.5, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 82.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 82.5, 209.0 ] ); // Go South $$terminal([ 92.5, 209.0 ] ); // Go East $$terminal([ 92.5, 220.0 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the Wire Terminal Feed WTERM24 // // Resolution: Medium // $$initial([ 116.5, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 106.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 106.5, 209.0 ] ); // Go South $$terminal([ 116.5, 209.0 ] ); // Go East $$terminal([ 116.5, 220.0 ] ); // NO_MITER Go Up the East edge $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_3 Converter and its Caps // // Resolution: Medium // $$initial([ 127.0, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 117.0, 220.0 ] ); // NO_MITER Go West $$terminal([ 117.0, 209.0 ] ); // Go South $$terminal([ 127.0, 209.0 ] ); // Go East $$terminal([ 127.0, 220.0 ] ); // NO_MITER Go Up the East edge $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_6 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 253.5 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 249.0, 253.5 ] ); // Go West $$terminal([ 249.0, 243.5 ] ); // Go South $$terminal([ 257.0, 243.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 253.5 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_7 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 235.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 230.0, 235.0 ] ); // Go West $$terminal([ 230.0, 228.0 ] ); // Go South $$terminal([ 215.0, 228.0 ] ); // Go West $$terminal([ 215.0, 210.5 ] ); // Go South $$terminal([ 235.0, 210.5 ] ); // Go East $$terminal([ 235.0, 215.5 ] ); // Go North a little $$terminal([ 257.0, 215.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 235.0 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_8 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 282.5 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 249.0, 282.5 ] ); // Go West $$terminal([ 249.0, 272.5 ] ); // Go South $$terminal([ 257.0, 272.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 282.5 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the MegArray #1 feed to the ROD // // Resolution: Hi // $$initial([ 134.2, 285.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 129.0, 285.0 ] ); // NO_MITER Go West $$terminal([ 129.0, 230.0 ] ); // NO_MITER Go South $$terminal([ 134.2, 230.0 ] ); // Go East $$terminal([ 134.2, 285.0 ] ); // NO_MITER Go Up the East edge to home $$path( "SHAPE_EDIT", 0.0 ); // // End the ISO_12V Fills // // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_1", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: FPGA_CORE // // Fill Layer: Signal_11 // // Location: From Converter DCDC_1 to the FPGA // // Resolution: Medium // $$initial([ 78.5, 207.4 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 45.5, 207.4 ] ); // Go West across the Top $$terminal([ 45.5, 134.3 ] ); // NO_MITER Go Down most of the West edge $$terminal([ 64.8, 115.0 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 91.2, 115.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 91.2, 194.7 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 78.5, 207.4 ] ); // NO_MITER Go 45 deg to the NW and Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: FPGA_CORE // // Fill Layer: Signal_11 // // Location: FPGA_CORE Pins under the FPGA // // Resolution: Hi // $$initial([ 89.5, 176.1 ], , @nosnap ); // NO_MITER Start in the NW corner and go CCW $$terminal([ 89.5, 115.0 ] ); // NO_MITER Go Down the West edge $$terminal([ 102.8, 115.0 ] ); // Go a East coming out of the overlap $$terminal([ 102.8, 126.6 ] ); // NO_MITER Go North into the pin array $$terminal([ 106.4, 130.2 ] ); // NO_MITER Go about 45 deg to the NE $$terminal([ 129.8, 130.2 ] ); // Go East Across the Bottom of the FPGA Core pins $$terminal([ 129.8, 149.8 ] ); // Go Up the East edge of the FPGA Core pins $$terminal([ 106.4, 149.8 ] ); // NO_MITER Go West across the Top of the FPGA Core pins $$terminal([ 102.8, 153.4 ] ); // NO_MITER Go about 45 deg to the NW $$terminal([ 102.8, 166.3 ] ); // NO_MITER Go North up through the pin array $$terminal([ 96.1, 173.0 ] ); // NO_MITER Go 45 deg North West $$terminal([ 92.6, 173.0 ] ); // NO_MITER Go West $$terminal([ 89.5, 176.1 ] ); // NO_MITER Go 45 deg North West and Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: MGT_AVCC // // Fill Layer: Signal_11 // // Location: DCDC_2 Output Filter Choke to FPGA // // Resolution: Medium // $$initial([ 126.0, 200.5 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 104.0, 200.5 ] ); // Go West across the Top $$terminal([ 104.0, 195.0 ] ); // NO_MITER Go Down a small West Edge $$terminal([ 91.8, 192.0 ] ); // NO_MITER Go about 45 deg to the SW $$terminal([ 91.8, 173.4 ] ); // Go South $$terminal([ 96.3, 173.4 ] ); // NO_MITER Go West $$terminal([ 103.2, 166.5 ] ); // NO_MITER Go 45 deg SW $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 91.8, 113.5 ] ); // NO_MITER Go West $$terminal([ 91.8, 100.0 ] ); // Go South $$terminal([ 107.5, 100.0 ] ); // NO_MITER Run East over to just before C91 $$terminal([ 113.0, 94.5 ] ); // NO_MITER Run 45 deg SE to pick up C91 $$terminal([ 119.5, 94.5 ] ); // NO_MITER Run East under C91 $$terminal([ 125.0, 100.0 ] ); // NO_MITER Run 45 deg NE back up to normal Y $$terminal([ 156.5, 100.0 ] ); // Go Finish running East Across the Bottom $$terminal([ 156.5, 186.0 ] ); // NO_MITER Go Up the East edge of the fill $$terminal([ 126.0, 195.0 ] ); // NO_MITER Go about 45 deg to the NW $$terminal([ 126.0, 200.5 ] ); // Go Up the East edge to Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: MGT_AVCC // // Fill Layer: Signal_11 // // Location: MGT_AVCC Pins under the FPGA // // Resolution: Hi // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 103.2, 167.0 ] ); // NO_MITER Go West across the Top $$terminal([ 103.2, 153.6 ] ); // NO_MITER Go South $$terminal([ 106.6, 150.2 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 130.2, 150.2 ] ); // Go East under the FPGA AVCC pins $$terminal([ 130.2, 129.8 ] ); // Go South just East of the Core supply finger $$terminal([ 106.6, 129.8 ] ); // NO_MITER Go West above the FPGA AVCC pins $$terminal([ 103.2, 126.4 ] ); // NO_MITER Go about 45 Deg to the SW $$terminal([ 103.2, 114.6 ] ); // Go South $$terminal([ 91.8, 114.6 ] ); // Go West $$terminal([ 91.8, 113.0 ] ); // NO_MITER Go South $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go Up the East edge and Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: FAN_1V8 // // Fill Layer: Signal_11 // // Location: DCDC_7 Output Filter and area under the FEX Data Fanout // // Resolution: Medium // $$initial([ 260.0, 204.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 180.5, 204.0 ] ); // Go far West across all of the Top $$terminal([ 180.5, 138.0 ] ); // Go Soouth along the West side until // we need to start the jog part way East $$terminal([ 192.0, 138.0 ] ); // Go East to get inside of the Eq Enb Ctrl $$terminal([ 192.0, 67.5 ] ); // Go South down the the rest of the West edge $$terminal([ 234.0, 67.5 ] ); // NO_MITER Go East across Part of the Bottom // to pick up some bypass capacitors $$terminal([ 238.5, 72.0 ] ); // NO_MITER Go NE at 45 Deg to get above // the worst of the Ethernet stuff. $$terminal([ 259.0, 72.0 ] ); // Go East across the rest of the Bottom $$terminal([ 259.0, 174.5 ] ); // NO_MITER Go North up the East edge $$terminal([ 262.0, 177.5 ] ); // NO_MITER Go NE at 45 degrees $$terminal([ 262.0, 193.0 ] ); // NO_MITER Go part way up the East edge $$terminal([ 260.0, 195.0 ] ); // NO_MITER Jog back NW at 45 deg to clear TRNS4 $$terminal([ 260.0, 204.0 ] ); // Go Up the East edge to Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: AVDDL_FLTR_A // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "A" aka U31 // // Resolution: Medium or HI // $$initial([ 141.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 110.0, 82.0 ] ); // Go West across the Top $$terminal([ 110.0, 48.7 ] ); // Go Down the West edge $$terminal([ 141.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 141.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: AVDDL_FLTR_B // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "B" aka U32 // // Resolution: Medium or HI // $$initial([ 91.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 60.0, 82.0 ] ); // Go West across the Top $$terminal([ 60.0, 48.7 ] ); // Go Down the West edge $$terminal([ 91.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 91.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: AVDDL_FLTR_C // // Fill Layer: Signal_11 // // Location: AVDDL Fill under Switch Chip "C" aka U33 // // Resolution: Medium or HI // $$initial([ 184.5, 82.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 153.0, 82.0 ] ); // Go West across the Top $$terminal([ 153.0, 48.7 ] ); // Go Down the West edge $$terminal([ 184.5, 48.7 ] ); // Go East Across the Bottom $$terminal([ 184.5, 82.0 ] ); // Go Up the rest of the east edge and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: Phys_U21_DVDDL // // Fill Layer: Signal_11 // // Location: DVDDL Fill under Phys Chip U21 // // Resolution: HI // $$initial([ 60.0, 119.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 51.8, 119.0 ] ); // Go West across the Top $$terminal([ 51.8, 105.2 ] ); // Go Down the West edge $$terminal([ 61.0, 105.2 ] ); // Go East Across the Bottom $$terminal([ 61.0, 118.0 ] ); // NO_MITER Go Up the East edge part way $$terminal([ 60.0, 119.0 ] ); // NO_MITER Go NW 45 deg and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: Phys_U22_DVDDL // // Fill Layer: Signal_11 // // Location: DVDDL Fill under Phys Chip U22 // // Resolution: HI // $$initial([ 61.0, 101.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 51.8, 101.0 ] ); // Go West across the Top $$terminal([ 51.8, 87.2 ] ); // Go Down the West edge $$terminal([ 61.0, 87.2 ] ); // Go East Across the Bottom $$terminal([ 61.0, 101.0 ] ); // Go Up the East edge and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: CLK_3V3 // // Fill Layer: Signal_11 // // Location: CLK_3V3 Fill under Clock Generator PLLs U502 and U506 // // Resolution: Medium ? // $$initial([ 79.0, 99.0 ], , @nosnap ); // Start in the NW corner and go CCW $$terminal([ 79.0, 83.0 ] ); // Go Down the West edge $$terminal([ 164.0, 83.0 ] ); // Go East across the Bottom $$terminal([ 164.0, 99.0 ] ); // Go Up the East edge $$terminal([ 125.0, 99.0 ] ); // NO_MITER Run West over to just before C91 $$terminal([ 120.0, 94.0 ] ); // NO_MITER Run 45 deg SW to avoid C91 $$terminal([ 112.5, 94.0 ] ); // NO_MITER Run West under C91 $$terminal([ 107.5, 99.0 ] ); // NO_MITER Run 45 deg NW back up to normal Y $$terminal([ 79.0, 99.0 ] ); // Finish running West across the Top edge and home $$path( "DIELECTRIC_1", 0.0 ); // // Net: CNST_5V0 // // Fill Layer: Signal_11 // // Location: North-West corner of the card // // Resolution: Medium // $$initial([ 112.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 23.0, 316.0 ] ); // Go West $$terminal([ 23.0, 296.0 ] ); // Go South $$terminal([ 98.0, 296.0 ] ); // NO_MITER Go part way back East $$terminal([ 112.0, 310.0 ] ); // NO_MITER Go 45 deg NE cutting the corner // to give more space for ISO_12V $$terminal([ 112.0, 316.0 ] ); // Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Start the ISO_12V Shapes on Signal_11 // // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Isolated +12V from its ATCA Module // to the Input Filter Capacitors for the DCDC Converters // // NOTES: 8 of the following Shapes are used to generate the // ISO_12V Fills on both pcb layers Sig_11 and Sig_12. // // Resolution: Medium // $$initial([ 293.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 113.0, 316.0 ] ); // Go West across part of the Top $$terminal([ 113.0, 309.3 ] ); // NO_MITER Go South to clear the CNST_5V0 fill $$terminal([ 98.7, 295.0 ] ); // NO_MITER Go 45 deg SW to clear the CNST_5V0 $$terminal([ 49.0, 295.0 ] ); // Go West across the rest of the Bulk Input Filter $$terminal([ 49.0, 263.0 ] ); // Go South down past some of the Bulk Input Filter $$terminal([ 1.0, 263.0 ] ); // Go East out to the Front Panel $$terminal([ 1.0, 134.0 ] ); // Go South to the top of the RJ45 Cut Out $$terminal([ 8.0, 134.0 ] ); // Go East to clear the Cut Out for the RJ45s $$terminal([ 8.0, 70.0 ] ); // Go South past the RJ45 Cut Out $$terminal([ 1.0, 70.0 ] ); // Go West back out to the Front Panel $$terminal([ 1.0, 11.0 ] ); // Go South to the top of the lower Front Panel Mount $$terminal([ 9.0, 11.0 ] ); // Go East to clear the lower Front Panel Mount $$terminal([ 9.0, 4.5 ] ); // Go South to pick up the C964 connection $$terminal([ 50.0, 4.5 ] ); // NO_MITER Go East so we can pickup all of the Iso 12V Caps $$terminal([ 50.0, 35.0 ] ); // NO_MITER Go North to pick up these Modules Output Caps $$terminal([ 44.5, 35.0 ] ); // Go West to setup the X for the run north $$terminal([ 44.5, 219.0 ] ); // NO_MITER Go North up to the area of the Bulk Input Filter $$terminal([ 130.0, 219.0 ] ); // Go East along the lower border of the Bulk Input Caps $$terminal([ 130.0, 284.5 ] ); // NO_MITER Go North between Bulk Input Caps and MegArray #1 $$terminal([ 256.0, 284.5 ] ); // Go East over to the smaller group of Bulk Input Caps $$terminal([ 256.0, 215.5 ] ); // NO_MITER Go South past the west border of // this smaller grp of Caps $$terminal([ 293.0, 215.5 ] ); // Go East to pick up the starting X $$terminal([ 293.0, 316.0 ] ); // Go Up the East edge of these Caps to Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Finger to pick up the DCDC_5 Converter and its Caps // // Resolution: Medium // $$initial([ 179.0, 4.5 ], , @nosnap ); // Start in the SE corner $$terminal([ 179.0, 14.7 ] ); // Go Up the East edge of DCDC_5 $$terminal([ 167.2, 14.7 ] ); // NO_MITER Go West part way across the top of DCDC_5 $$terminal([ 159.8, 22.1 ] ); // NO_MITER Go 45 deg NW $$terminal([ 155.5, 22.1 ] ); // Go West under the Input module pin $$terminal([ 155.5, 27.2 ] ); // Go North to get more Cu on west side of pins. $$terminal([ 145.0, 27.2 ] ); // Go West under Entry module and get more heigth $$terminal([ 143.5, 28.7 ] ); // Go North up past an input module pin $$terminal([ 114.0, 28.7 ] ); // Go West thru most of the Power Entry Module $$terminal([ 114.0, 35.0 ] ); // Go North $$terminal([ 49.0, 35.0 ] ); // NO_MITER Go West to make an overlap $$terminal([ 49.0, 4.5 ] ); // NO_MITER Go South past the Iso 12V connection $$terminal([ 179.0, 4.5 ] ); // Go East back to the DCDC5 Conv and Home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_1 Converter and its Caps // // Resolution: Medium // $$initial([ 58.0, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 43.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 43.5, 208.5 ] ); // NO_MITER Go South $$terminal([ 58.0, 208.5 ] ); // Go East $$terminal([ 58.0, 220.0 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_2 Converter and its Caps // // Resolution: Medium // $$initial([ 92.5, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 82.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 82.5, 209.0 ] ); // Go South $$terminal([ 92.5, 209.0 ] ); // Go East $$terminal([ 92.5, 220.0 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the Wire Terminal Feed WTERM24 // // Resolution: Medium // $$initial([ 116.5, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 106.5, 220.0 ] ); // NO_MITER Go West $$terminal([ 106.5, 209.0 ] ); // Go South $$terminal([ 116.5, 209.0 ] ); // Go East $$terminal([ 116.5, 220.0 ] ); // NO_MITER Go Up the East edge $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_3 Converter and its Caps // // Resolution: Medium // $$initial([ 127.0, 220.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 117.0, 220.0 ] ); // NO_MITER Go West $$terminal([ 117.0, 209.0 ] ); // Go South $$terminal([ 127.0, 209.0 ] ); // Go East $$terminal([ 127.0, 220.0 ] ); // NO_MITER Go Up the East edge $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_6 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 253.5 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 249.0, 253.5 ] ); // Go West $$terminal([ 249.0, 243.5 ] ); // Go South $$terminal([ 257.0, 243.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 253.5 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_7 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 235.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 230.0, 235.0 ] ); // Go West $$terminal([ 230.0, 228.0 ] ); // Go South $$terminal([ 215.0, 228.0 ] ); // Go West $$terminal([ 215.0, 210.5 ] ); // Go South $$terminal([ 235.0, 210.5 ] ); // Go East $$terminal([ 235.0, 215.5 ] ); // Go North a little $$terminal([ 257.0, 215.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 235.0 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the DCDC_8 Converter and its Caps // // Resolution: Medium // $$initial([ 257.0, 282.5 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 249.0, 282.5 ] ); // Go West $$terminal([ 249.0, 272.5 ] ); // Go South $$terminal([ 257.0, 272.5 ] ); // NO_MITER Go East $$terminal([ 257.0, 282.5 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Tab to to pick up the MegArray #1 feed to the ROD // // Resolution: Hi // $$initial([ 134.2, 285.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 129.0, 285.0 ] ); // NO_MITER Go West $$terminal([ 129.0, 230.0 ] ); // NO_MITER Go South $$terminal([ 134.2, 230.0 ] ); // Go East $$terminal([ 134.2, 285.0 ] ); // NO_MITER Go Up the East edge to home $$path( "DIELECTRIC_1", 0.0 ); // // End the ISO_12V Fills //