// // // // Shape Edit Section of the // -==========----------------- // // Hub Module Printed Circuit Board Geometry File // -------------------------------------------------- // // // Area Fills on Signal Layer 12 <--- // ---------------------------==== // // // // Original Rev. 3-Feb-2016 // Current Rev. 19-Nov-2016 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed on Signal_12 // are: FPGA_CORE and MGT_AVTT. // // - These fills are kept back at least 4.5 mm from the // top and bottom edges so that the area fills will not be // exposed when the top and bottom edges are milled to // allow this card to fit into the crate card guides. // // - These fills are kept back at least 1mm from the front // and back edges to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: SHAPE_EDIT and DIELECTRIC_2. // See the bottom section of this file. // // - As of 17-Oct-2016 there are 9 shapes defined in this file. // // - List of Fills in this file: // // FPGA_CORE: Converter DCDC_1 to the FPGA Core pins // MGT_AVTT: Converter DCDC_3 to the FPGA AVTT pins // FAN_1V8: // SWCH_1V2: // ISO_12V: // CLK_2V5: // IPMC_3V3: // // // // - Currently many sections of the ISO_12V fills on Signal_11 and // Signal_12 have exactly the same Shape pattern. // // NOTE: For those sections of the overall ISO_12V fill that have // exactly the same Shape on Signal_11 and Signal_12, I'm // only generating this Shape in the Signal_11 Shape // source file. I'm not repeating it in the // Signal_12 Shape source file. That is, some of the // ISO_12V fills on both layers Sig_11 and Sig_12 will // be based on the Shapes that come from the Sig_11 Shape // source file. // // I do not want to risk confusion by having two copies // of exactly the same Shape in the Hub design. // // There is no point in needing to edit both the Sig_11 // and Sig_12 files to make a change in the ISO_12V fills. // // // // // Net: FPGA_CORE // // Fill Layer: Signal_12 // // Location: From Converter DCDC_1 to the FPGA // // Resolution: Medium // $$initial([ 78.5, 207.4 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 45.5, 207.4 ] ); // Go West across the Top $$terminal([ 45.5, 134.3 ] ); // NO_MITER Go Down most of the West edge $$terminal([ 64.3, 115.5 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 90.5, 115.5 ] ); // Go East Across the Bottom $$terminal([ 90.5, 195.4 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 78.5, 207.4 ] ); // NO_MITER Go 45 deg to the NW and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: FPGA_CORE // // Fill Layer: Signal_12 // // Location: FPGA_CORE Pins under the FPGA // // Resolution: HI // $$initial([ 90.5, 153.3 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 89.5, 153.3 ] ); // NO_MITER Go West just a little for overlap $$terminal([ 89.5, 126.7 ] ); // NO_MITER Go South $$terminal([ 90.5, 126.7 ] ); // NO_MITER Go East to the start of the Core finger $$terminal([ 91.0, 127.2 ] ); // NO_MITER Go about 45 deg to the NE $$terminal([ 128.8, 127.2 ] ); // Go East Across the Bottom of the FPGA Core pins $$terminal([ 128.8, 152.8 ] ); // Go Up the East edge of the FPGA Core pins $$terminal([ 91.0, 152.8 ] ); // NO_MITER Go West across the Top of the FPGA Core pins $$terminal([ 90.5, 153.3 ] ); // NO_MITER Go about 45 deg to the NW and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVTT // // Fill Layer: Signal_12 // // Location: DCDC_3 Output Filter Choke to FPGA // // Resolution: Medium // $$initial([ 158.0, 200.5 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 131.5, 200.5 ] ); // Go West across the Top $$terminal([ 131.5, 192.5 ] ); // Go Down a small West Edge $$terminal([ 121.5, 192.5 ] ); // NO_MITER Go East across part of the top of the fill $$terminal([ 117.0, 188.0 ] ); // NO_MITER Go 45 deg SW $$terminal([ 91.0, 188.0 ] ); // Go East across the rest of the top of the fill $$terminal([ 91.0, 166.5 ] ); // NO_MITER Go Down the West Edge of this fill $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 91.0, 113.5 ] ); // NO_MITER Go West $$terminal([ 91.0, 98.0 ] ); // Go South $$terminal([ 105.0, 98.0 ] ); // Go East across part of the bottom // to pickup some bypass capacitors $$terminal([ 105.0, 89.5 ] ); // Go South to get under these caps $$terminal([ 128.5, 89.5 ] ); // Go East undet these caps $$terminal([ 128.5, 99.5 ] ); // Go North back up to the norm line $$terminal([ 155.5, 99.5 ] ); // Finish Going East Across the Bottom $$terminal([ 155.5, 144.0 ] ); // NO_MITER Go North part way up the East edge $$terminal([ 162.0, 150.5 ] ); // NO_MITER Go 45 degrees to the NE $$terminal([ 162.0, 196.5 ] ); // NO_MITER Go North most of the rest of the way $$terminal([ 158.0, 200.5 ] ); // NO_MITER Go 45 deg NW to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVTT // // Fill Layer: Signal_12 // // Location: MGT_AVTT pins under the FPGA // // Resolution: HI // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 91.0, 167.0 ] ); // NO_MITER Go West $$terminal([ 91.0, 153.7 ] ); // NO_MITER Go Down the West Edge of this fill $$terminal([ 91.5, 153.2 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 129.2, 153.2 ] ); // Go East under the FPGA AVTT pins $$terminal([ 129.2, 126.8 ] ); // Go South past the FPGA Core finger $$terminal([ 91.5, 126.8 ] ); // NO_MITER Go West above the FPGA AVTT pins $$terminal([ 91.0, 126.3 ] ); // NO_MITER Go about 45 Deg to the SW $$terminal([ 91.0, 113.0 ] ); // NO_MITER Go South $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go North to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: FAN_1V8 // // Fill Layer: Signal_12 // // Location: DCDC_7 Output and area under the FEX Data Fanout Chips // // Resolution: Medium // $$initial([ 260.0, 204.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 180.5, 204.0 ] ); // Go far West across all of the Top $$terminal([ 180.5, 103.5 ] ); // NO_MITER Go Soouth along the West side until // we need to start the jog part way East $$terminal([ 191.0, 93.0 ] ); // NO_MITER Go SE at about 45 degrees to jog back East $$terminal([ 191.0, 67.5 ] ); // Go South down the the rest of the West edge $$terminal([ 234.0, 67.5 ] ); // NO_MITER Go East part way across the bottom // under the bypass caps: C256, C262, C278 $$terminal([ 238.5, 72.0 ] ); // NO_MITER Go 45 deg NE back to normal Y $$terminal([ 260.0, 72.0 ] ); // Go the rest of the way East across the bottom $$terminal([ 260.0, 171.5 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 262.5, 174.0 ] ); // NO_MITER Go 45 degress NE to jog East to get more // width in the pinch by the low Row of Fanouts $$terminal([ 262.5, 192.5 ] ); // NO_MITER Go North until we need to jog back West // to avoid the Ethernet Magnetics $$terminal([ 260.0, 195.0 ] ); // NO_MITER Go 45 degrees NW to jog West of the ENet Mag. $$terminal([ 260.0, 204.0 ] ); // Go Up the rest of the East edge to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: SWCH_1V2 // // Fill Layer: Signal_12 // // Location: DCDC_5 Output to area under the 3 Switch chips and 2 Phys chips // // Resolution: Medium // $$initial([ 186.0, 15.7 ], , @nosnap ); // Start in the SE corner $$terminal([ 186.0, 41.8 ] ); // Go North part way up to the Switch chips $$terminal([ 189.6, 41.8 ] ); // Go East to pick up all of Switch chip "C" $$terminal([ 189.6, 82.5 ] ); // Go North up the East side of the Switch chip "C" $$terminal([ 128.5, 82.5 ] ); // NO_MITER Go part way West across the top of the Switch chips $$terminal([ 127.0, 84.0 ] ); // NO_MITER Go North a little to get more Cu above Switches $$terminal([ 72.0, 84.0 ] ); // Finish going West across the top of the Switch chips $$terminal([ 72.0, 107.0 ] ); // NO_MITER Go North part way up the Phys chip's East side $$terminal([ 54.0, 125.0 ] ); // NO_MITER Go NW at 45 deg up to the top of the Phys chips $$terminal([ 46.0, 125.0 ] ); // Go West across the Top of the Phys chips $$terminal([ 46.0, 37.0 ] ); // Go South down the West edge of the Phys chips // and the Switch chips $$terminal([ 159.8, 37.0 ] ); // Go East under the bottom edge of the Switch chips $$terminal([ 159.8, 23.4 ] ); // NO_MITER Go South part way down the West edge of DCDC_5 $$terminal([ 167.5, 15.7 ] ); // NO_MITER Go 45 deg SE down the rest of DCDC_5 West edge $$terminal([ 186.0, 15.7 ] ); // Go East under DCDC_5 to Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: CLK_2V5 // // Fill Layer: Signal_12 // // Location: Clock Fanout Area especially under: U503, U504, U507 // // Resolution: Medium ?? // $$initial([ 129.0, 99.0 ], , @nosnap ); // Start in the Lower NW corner and go CCW $$terminal([ 129.0, 83.0 ] ); // Go Down the lower West edge $$terminal([ 179.5, 83.0 ] ); // Go East across the Bottom $$terminal([ 179.5, 144.5 ] ); // Go Up the East edge $$terminal([ 156.0, 144.5 ] ); // Go West across part of the Top $$terminal([ 156.0, 99.0 ] ); // Go Down the upper West edge $$terminal([ 129.0, 99.0 ] ); // Go West across the rest of the Top and Home $$path( "SHAPE_EDIT", 0.0 ); // // Net: IPMC_3V3 // // Fill Layer: Signal_12 // // Location: IPMC_3V3 Fill Under Northern part of IPMC Socket and East of there // // Resolution: Midium // $$initial([ 50.5, 305.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 23.0, 305.0 ] ); // Go West across the Top $$terminal([ 23.0, 260.0 ] ); // Go Down the West edge $$terminal([ 50.5, 260.0 ] ); // Go East Across the Bottom $$terminal([ 50.5, 305.0 ] ); // Go Up the East edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Start the ISO_12V Shapes on Signal_12 // // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Isolated +12V from its ATCA Module to the // Bulk Input Filter Capacitors for the DCDC Converters // // NOTES: This ISO_12V Shape is different on Sig_11 and Sig_12 // // The approximately 8 other ISO_12V Fill Shapes are // exactly the same on Sig_11 and Sig_12. These Shapes // are in the Sig_11 file and are not repeated in this // Sig_12 Shape source file. // // Resolution: Medium // $$initial([ 293.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 51.0, 316.0 ] ); // Go West across part of the Top $$terminal([ 51.0, 259.0 ] ); // Go South down past some of the Bulk Input Filter $$terminal([ 1.0, 259.0 ] ); // Go East out to the Front Panel $$terminal([ 1.0, 134.0 ] ); // Go South to the top of the RJ45 Cut Out $$terminal([ 8.0, 134.0 ] ); // Go East to clear the Cut Out for the RJ45s $$terminal([ 8.0, 70.0 ] ); // Go South past the RJ45 Cut Out $$terminal([ 1.0, 70.0 ] ); // Go West back out to the Front Panel $$terminal([ 1.0, 11.0 ] ); // Go South to the top of the lower Front Panel Mount $$terminal([ 9.0, 11.0 ] ); // Go East to clear the lower Front Panel Mount $$terminal([ 9.0, 4.5 ] ); // Go South to pick up the C964 connection $$terminal([ 50.0, 4.5 ] ); // NO_MITER Go East so we can pickup all of the Iso 12V Caps $$terminal([ 50.0, 35.0 ] ); // NO_MITER Go North to pick up these Modules Output Caps $$terminal([ 44.5, 35.0 ] ); // Go West to setup the X for the run north $$terminal([ 44.5, 219.0 ] ); // NO_MITER Go North up to the area of the Bulk Input Filter $$terminal([ 130.0, 219.0 ] ); // Go East along the lower border of the Bulk Input Caps $$terminal([ 130.0, 284.5 ] ); // NO_MITER Go North between Bulk Input Caps and MegArray #1 $$terminal([ 256.0, 284.5 ] ); // Go East over to the smaller group of Bulk Input Caps $$terminal([ 256.0, 220.0 ] ); // NO_MITER Go South past the west border of // this smaller grp of Caps $$terminal([ 293.0, 220.0 ] ); // Go East to pick up the starting X $$terminal([ 293.0, 316.0 ] ); // Go Up the East edge of these Caps to Home $$path( "SHAPE_EDIT", 0.0 ); // // Do not repeat the fill shapes from the Signal_11 // fill file that are used for feeding ISO_12V to the // individual DCDC Converters on both Signal_11 and Signal_12. // // These shapes appear only in the Signal_11 fill shape file // but they are used when generating the fills for both Signal_11 // on for Signal_12. // // // End the ISO_12V Fills // // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: FPGA_CORE // // Fill Layer: Signal_12 // // Location: From Converter DCDC_1 to the FPGA // // Resolution: Medium // $$initial([ 78.5, 207.4 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 45.5, 207.4 ] ); // Go West across the Top $$terminal([ 45.5, 134.3 ] ); // NO_MITER Go Down most of the West edge $$terminal([ 64.3, 115.5 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 90.5, 115.5 ] ); // Go East Across the Bottom $$terminal([ 90.5, 195.4 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 78.5, 207.4 ] ); // NO_MITER Go 45 deg to the NW and Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: FPGA_CORE // // Fill Layer: Signal_12 // // Location: FPGA_CORE Pins under the FPGA // // Resolution: HI // $$initial([ 90.5, 153.3 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 89.5, 153.3 ] ); // NO_MITER Go West just a little for overlap $$terminal([ 89.5, 126.7 ] ); // NO_MITER Go South $$terminal([ 90.5, 126.7 ] ); // NO_MITER Go East to the start of the Core finger $$terminal([ 91.0, 127.2 ] ); // NO_MITER Go about 45 deg to the NE $$terminal([ 128.8, 127.2 ] ); // Go East Across the Bottom of the FPGA Core pins $$terminal([ 128.8, 152.8 ] ); // Go Up the East edge of the FPGA Core pins $$terminal([ 91.0, 152.8 ] ); // NO_MITER Go West across the Top of the FPGA Core pins $$terminal([ 90.5, 153.3 ] ); // NO_MITER Go about 45 deg to the NW and Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: MGT_AVTT // // Fill Layer: Signal_12 // // Location: DCDC_3 Output Filter Choke to FPGA // // Resolution: Medium // $$initial([ 158.0, 200.5 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 131.5, 200.5 ] ); // Go West across the Top $$terminal([ 131.5, 192.5 ] ); // Go Down a small West Edge $$terminal([ 121.5, 192.5 ] ); // NO_MITER Go East across part of the top of the fill $$terminal([ 117.0, 188.0 ] ); // NO_MITER Go 45 deg SW $$terminal([ 91.0, 188.0 ] ); // Go East across the rest of the top of the fill $$terminal([ 91.0, 166.5 ] ); // NO_MITER Go Down the West Edge of this fill $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 91.0, 113.5 ] ); // NO_MITER Go West $$terminal([ 91.0, 98.0 ] ); // Go South $$terminal([ 105.0, 98.0 ] ); // Go East across part of the bottom // to pickup some bypass capacitors $$terminal([ 105.0, 89.5 ] ); // Go South to get under these caps $$terminal([ 128.5, 89.5 ] ); // Go East undet these caps $$terminal([ 128.5, 99.5 ] ); // Go North back up to the norm line $$terminal([ 155.5, 99.5 ] ); // Finish Going East Across the Bottom $$terminal([ 155.5, 144.0 ] ); // NO_MITER Go North part way up the East edge $$terminal([ 162.0, 150.5 ] ); // NO_MITER Go 45 degrees to the NE $$terminal([ 162.0, 196.5 ] ); // NO_MITER Go North most of the rest of the way $$terminal([ 158.0, 200.5 ] ); // NO_MITER Go 45 deg NW to Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: MGT_AVTT // // Fill Layer: Signal_12 // // Location: MGT_AVTT pins under the FPGA // // Resolution: HI // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner and go CCW $$terminal([ 91.0, 167.0 ] ); // NO_MITER Go West $$terminal([ 91.0, 153.7 ] ); // NO_MITER Go Down the West Edge of this fill $$terminal([ 91.5, 153.2 ] ); // NO_MITER Go about 45 deg to the SE $$terminal([ 129.2, 153.2 ] ); // Go East under the FPGA AVTT pins $$terminal([ 129.2, 126.8 ] ); // Go South past the FPGA Core finger $$terminal([ 91.5, 126.8 ] ); // NO_MITER Go West above the FPGA AVTT pins $$terminal([ 91.0, 126.3 ] ); // NO_MITER Go about 45 Deg to the SW $$terminal([ 91.0, 113.0 ] ); // NO_MITER Go South $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go North to Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: FAN_1V8 // // Fill Layer: Signal_12 // // Location: DCDC_7 Output and area under the FEX Data Fanout Chips // // Resolution: Medium // $$initial([ 260.0, 204.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 180.5, 204.0 ] ); // Go far West across all of the Top $$terminal([ 180.5, 103.5 ] ); // NO_MITER Go Soouth along the West side until // we need to start the jog part way East $$terminal([ 191.0, 93.0 ] ); // NO_MITER Go SE at about 45 degrees to jog back East $$terminal([ 191.0, 67.5 ] ); // Go South down the the rest of the West edge $$terminal([ 234.0, 67.5 ] ); // NO_MITER Go East part way across the bottom // under the bypass caps: C256, C262, C278 $$terminal([ 238.5, 72.0 ] ); // NO_MITER Go 45 deg NE back to normal Y $$terminal([ 260.0, 72.0 ] ); // Go the rest of the way East across the bottom $$terminal([ 260.0, 171.5 ] ); // NO_MITER Go Up the East edge most of the way $$terminal([ 262.5, 174.0 ] ); // NO_MITER Go 45 degress NE to jog East to get more // width in the pinch by the low Row of Fanouts $$terminal([ 262.5, 192.5 ] ); // NO_MITER Go North until we need to jog back West // to avoid the Ethernet Magnetics $$terminal([ 260.0, 195.0 ] ); // NO_MITER Go 45 degrees NW to jog West of the ENet Mag. $$terminal([ 260.0, 204.0 ] ); // Go Up the rest of the East edge to Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: SWCH_1V2 // // Fill Layer: Signal_12 // // Location: DCDC_5 Output to area under the 3 Switch chips and 2 Phys chips // // Resolution: Medium // $$initial([ 186.0, 15.7 ], , @nosnap ); // Start in the SE corner $$terminal([ 186.0, 41.8 ] ); // Go North part way up to the Switch chips $$terminal([ 189.6, 41.8 ] ); // Go East to pick up all of Switch chip "C" $$terminal([ 189.6, 82.5 ] ); // Go North up the East side of the Switch chip "C" $$terminal([ 128.5, 82.5 ] ); // NO_MITER Go part way West across the top of the Switch chips $$terminal([ 127.0, 84.0 ] ); // NO_MITER Go North a little to get more Cu above Switches $$terminal([ 72.0, 84.0 ] ); // Finish going West across the top of the Switch chips $$terminal([ 72.0, 107.0 ] ); // NO_MITER Go North part way up the Phys chip's East side $$terminal([ 54.0, 125.0 ] ); // NO_MITER Go NW at 45 deg up to the top of the Phys chips $$terminal([ 46.0, 125.0 ] ); // Go West across the Top of the Phys chips $$terminal([ 46.0, 37.0 ] ); // Go South down the West edge of the Phys chips // and the Switch chips $$terminal([ 159.8, 37.0 ] ); // Go East under the bottom edge of the Switch chips $$terminal([ 159.8, 23.4 ] ); // NO_MITER Go South part way down the West edge of DCDC_5 $$terminal([ 167.5, 15.7 ] ); // NO_MITER Go 45 deg SE down the rest of DCDC_5 West edge $$terminal([ 186.0, 15.7 ] ); // Go East under DCDC_5 to Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: CLK_2V5 // // Fill Layer: Signal_12 // // Location: Clock Fanout Area especially under: U503, U504, U507 // // Resolution: Medium ?? // $$initial([ 129.0, 99.0 ], , @nosnap ); // Start in the Lower NW corner and go CCW $$terminal([ 129.0, 83.0 ] ); // Go Down the lower West edge $$terminal([ 179.5, 83.0 ] ); // Go East across the Bottom $$terminal([ 179.5, 144.5 ] ); // Go Up the East edge $$terminal([ 156.0, 144.5 ] ); // Go West across part of the Top $$terminal([ 156.0, 99.0 ] ); // Go Down the upper West edge $$terminal([ 129.0, 99.0 ] ); // Go West across the rest of the Top and Home $$path( "DIELECTRIC_2", 0.0 ); // // Net: IPMC_3V3 // // Fill Layer: Signal_12 // // Location: IPMC_3V3 Fill Under Northern part of IPMC Socket and East of there // // Resolution: Midium // $$initial([ 50.5, 305.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 23.0, 305.0 ] ); // Go West across the Top $$terminal([ 23.0, 260.0 ] ); // Go Down the West edge $$terminal([ 50.5, 260.0 ] ); // Go East Across the Bottom $$terminal([ 50.5, 305.0 ] ); // Go Up the East edge and home $$path( "DIELECTRIC_2", 0.0 ); // // Start the ISO_12V Shapes on Signal_12 // // // Net: ISO_12V // // Fill Layer: Signal_11 // // Location: Isolated +12V from its ATCA Module to the // Bulk Input Filter Capacitors for the DCDC Converters // // NOTES: This ISO_12V Shape is different on Sig_11 and Sig_12 // // The approximately 8 other ISO_12V Fill Shapes are // exactly the same on Sig_11 and Sig_12. These Shapes // are in the Sig_11 file and are not repeated in this // Sig_12 Shape source file. // // Resolution: Medium // $$initial([ 293.0, 316.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 51.0, 316.0 ] ); // Go West across part of the Top $$terminal([ 51.0, 259.0 ] ); // Go South down past some of the Bulk Input Filter $$terminal([ 1.0, 259.0 ] ); // Go East out to the Front Panel $$terminal([ 1.0, 134.0 ] ); // Go South to the top of the RJ45 Cut Out $$terminal([ 8.0, 134.0 ] ); // Go East to clear the Cut Out for the RJ45s $$terminal([ 8.0, 70.0 ] ); // Go South past the RJ45 Cut Out $$terminal([ 1.0, 70.0 ] ); // Go West back out to the Front Panel $$terminal([ 1.0, 11.0 ] ); // Go South to the top of the lower Front Panel Mount $$terminal([ 9.0, 11.0 ] ); // Go East to clear the lower Front Panel Mount $$terminal([ 9.0, 4.5 ] ); // Go South to pick up the C964 connection $$terminal([ 50.0, 4.5 ] ); // NO_MITER Go East so we can pickup all of the Iso 12V Caps $$terminal([ 50.0, 35.0 ] ); // NO_MITER Go North to pick up these Modules Output Caps $$terminal([ 44.5, 35.0 ] ); // Go West to setup the X for the run north $$terminal([ 44.5, 219.0 ] ); // NO_MITER Go North up to the area of the Bulk Input Filter $$terminal([ 130.0, 219.0 ] ); // Go East along the lower border of the Bulk Input Caps $$terminal([ 130.0, 284.5 ] ); // NO_MITER Go North between Bulk Input Caps and MegArray #1 $$terminal([ 256.0, 284.5 ] ); // Go East over to the smaller group of Bulk Input Caps $$terminal([ 256.0, 220.0 ] ); // NO_MITER Go South past the west border of // this smaller grp of Caps $$terminal([ 293.0, 220.0 ] ); // Go East to pick up the starting X $$terminal([ 293.0, 316.0 ] ); // Go Up the East edge of these Caps to Home $$path( "DIELECTRIC_2", 0.0 ); // // Do not repeat the fill shapes from the Signal_11 // fill file that are used for feeding ISO_12V to the // individual DCDC Converters on both Signal_11 and Signal_12. // // These shapes appear only in the Signal_11 fill shape file // but they are used when generating the fills for both Signal_11 // on for Signal_12. // // // End the ISO_12V Fills //