// // // // Shape Edit Section of the // -==========----------------- // // Hub Module Printed Circuit Board Geometry File // -------------------------------------------------- // // // Area Fills on Signal Layer 6 <--- // ---------------------------=== // // // // Original Rev. 3-Feb-2016 // Current Rev. 9-Jan-2017 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power net that is distributed on Signal_6 // is: BULK_1V8. // // - These fills are kept back at least 4.5 mm from the // top and bottom edges so that the area fills will not be // exposed when the top and bottom edges are milled to // allow this card to fit into the crate card guides. // // - These fills are kept back at least 1mm from the front // and back edges to comply with normal decorum. // // - EVERYTHING in this Signal_6 fill file is repeated // on both the layers: SHAPE_EDIT and DIELECTRIC_4. // See the bottom section of this file. // // - Note that a discrete trace run is required to connect // the BULK_1V8 rail to the JTAG level translators in the // SW corner of the card next to the J2 connector, i.e. // not all BULK_1V8 distribution is accomplished by fill. // // - As of 17-Oct-2016 there are 6 shapes defined in this file. // // - List of Fills in this file: // // BULK_1V8: Main BULK_1V8 fill over a large section of the card // Hi Resolution BULK_1V8 fill under the FPGA // Hi Resolution BULK_1V8 fill under the Config Flash Memory // // MGT_AVAUX: MGT_AVAUX fill from DCDC4 to under Eastern part of FPGA // A Midium Resolution yoke from DCDC-4 on the FPGA's East edge // A Hi Resolution MGT_AVAUX fill under the FPGA // // ECLK_3V3 Under the 25 MHz Ethernet Clock Oscillator and its Fanout // // // // // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: Main BULK_1V8 fill over a big section of the Hub PCB. // // Resolution: Medium // $$initial([ 250.0, 317.5 ], , @nosnap ); // Start in the NE corner $$terminal([ 24.5, 317.5 ] ); // Go West across the Top $$terminal([ 24.5, 210.0 ] ); // NO_MITER Go Down the West edge - stop // near the bottom of the IPMC connector. $$terminal([ 44.5, 190.0 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 44.5, 105.5 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 46.0, 104.0 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 46.0, 88.0 ] ); // Go the rest of the way Down to the bottom of the Phys Chips $$terminal([ 74.0, 88.0 ] ); // Go East Across the Bottom of the Phys Chips $$terminal([ 74.0, 101.0 ] ); // Go North to get just above the Clock chips $$terminal([ 90.0, 101.0 ] ); // Go East to pick of the West edge of FPGA $$terminal([ 90.0, 196.0 ] ); // NO_MITER Go North up the West edge of the FPGA // Note there is a separate high resolution // BULK_1V8 Fill Finger under the FPGA $$terminal([ 83.0, 203.0 ] ); // NO_MITER Jog at 45 deg to the NW to get a little West // to keep out of the DCDC2 Converter $$terminal([ 83.0, 222.0 ] ); // Finish going North $$terminal([ 130.0, 222.0 ] ); // Go East over to the West edge // of the S1 MegArray connector $$terminal([ 130.0, 283.0 ] ); // Go North up the West edge of the S1 MegArray. $$terminal([ 228.0, 283.0 ] ); // Go East Across the top of S1 and S2 MegArrays. $$terminal([ 228.0, 237.0 ] ); // Go Down the East edge of the S2 MegArray $$terminal([ 250.0, 237.0 ] ); // Go East Across the Bottom of the BULK_1V8 // DCDC Converter $$terminal([ 250.0, 317.5 ] ); // Go North up the East edge of the BULK_1V8 // DCDC Converter back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: BULK_1V8 fill finger under the U1 FPGA // // Resolution: Hi // $$initial([ 89.0, 173.0 ], , @nosnap ); // NO_MITER Start in the NW corner $$terminal([ 89.0, 107.0 ] ); // NO_MITER Go South overlapping the main BULK_1V8 fill $$terminal([ 92.2, 107.0 ] ); // NO_MITER Go East a little to get into the Hi res area $$terminal([ 103.8, 118.6 ] ); // NO_MITER Go NE at 45 degrees $$terminal([ 103.8, 126.9 ] ); // NO_MITER Go North into the FPGA footprint $$terminal([ 106.1, 129.2 ] ); // NO_MITER Go North-East to get above MGT_AVAUX fill $$terminal([ 126.2, 129.2 ] ); // NO_MITER Go East above MGT_AVAUX fill $$terminal([ 127.2, 130.2 ] ); // NO_MITER Go 45 deg NE to get above 2 MGT_AVAUX pins $$terminal([ 139.0, 130.2 ] ); // Go East to to the East edge of the FPGA // to get all of the FPGA's 1V8 pins. $$terminal([ 139.0, 149.8 ] ); // Go North up the East edge of the FPGA // get just above the upper 1V8 pins $$terminal([ 125.2, 149.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 124.2, 150.8 ] ); // NO_MITER Go 45 deg NW to get above 2 MGT_AVAUX pins $$terminal([ 106.1, 150.8 ] ); // NO_MITER Go West across the top of the FPGA's 1V8 pins $$terminal([ 103.8, 153.1 ] ); // NO_MITER Go North-West between 1V8 and AVAUX pins $$terminal([ 103.8, 161.4 ] ); // NO_MITER Go North to get out of BGA field $$terminal([ 92.2, 173.0 ] ); // NO_MITER Go diagonally 45 deg NW $$terminal([ 89.0, 173.0 ] ); // NO_MITER Go West back to the Home corner. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: BULK_1V8 fill under the Config Flash Memory // // Resolution: Hi // $$initial([ 81.5, 149.5 ], , @nosnap ); // Start in the NE corner $$terminal([ 68.5, 149.5 ] ); // Go West across the Top $$terminal([ 68.5, 136.5 ] ); // Go Down the West edge $$terminal([ 81.5, 136.5 ] ); // Go East Across the Bottom $$terminal([ 81.5, 149.5 ] ); // Go Up the rest of the east edge and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVAUX // // Fill Layer: Signal_6 // // Location: from the DCDC_4 Converter to the Eastern part of FPGA // // Resolution: Medium // $$initial([ 163.5, 205.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 154.5, 205.0 ] ); // Go West across the Top of DCDC_4 $$terminal([ 154.5, 192.0 ] ); // NO_MITER Go Down the West edge of DCDC_4 $$terminal([ 151.2, 188.7 ] ); // NO_MITER Go Diagonally Down and West to FPGA NE corner $$terminal([ 135.8, 188.7 ] ); // NO_MITER Go West further West across Top of the FPGA // until just before C161 an AVAUX cap $$terminal([ 135.5, 189.0 ] ); // NO_MITER Go NW just 0.3 mm to get above C161 $$terminal([ 125.3, 189.0 ] ); // NO_MITER Finish going West further West // across Top of the FPGA $$terminal([ 121.3, 185.0 ] ); // NO_MITER Go 45 deg SW to escape converters $$terminal([ 99.0, 185.0 ] ); // Go far West to pick up some bypass capacitors $$terminal([ 99.0, 171.7 ] ); // NO_MITER Go Down the West edge of this AVAUX fill $$terminal([ 104.2, 166.5 ] ); // NO_MITER Go 45 deg SE to join Hi Res AVAUX fill $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 104.2, 113.5 ] ); // NO_MITER Go West $$terminal([ 103.2, 112.5 ] ); // NO_MITER Go SW at 45 deg for just 1 mm $$terminal([ 99.0, 112.5 ] ); // NO_MITER Go West $$terminal([ 93.5, 107.0 ] ); // NO_MITER Go 45 deg SW to pick up the Tant Cap $$terminal([ 93.5, 98.0 ] ); // Go South $$terminal([ 156.0, 98.0 ] ); // Go East Across the Bottom of FPGA $$terminal([ 156.0, 145.0 ] ); // NO_MITER Go Up part way the east edge of FPGA $$terminal([ 163.0, 152.0 ] ); // NO_MITER Go Diagonally NE $$terminal([ 163.0, 182.0 ] ); // NO_MITER Go Up $$terminal([ 163.5, 182.5 ] ); // NO_MITER Go 45 deg NE for more Cu - close to FEX lines $$terminal([ 163.5, 205.0 ] ); // Go Up the rest of the east edge of DCDC_4 and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: MGT_AVAUX // // Fill Layer: Signal_6 // // Location: MGT_AVAUX pins under the FPGA // // Resolution: HI // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 104.2, 167.0 ] ); // NO_MITER Go West across the Top of FPGA $$terminal([ 104.2, 153.3 ] ); // NO_MITER Go Down the West edge just far enough // to pick up all of the AVAUX pins $$terminal([ 106.3, 151.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 124.4, 151.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 125.4, 150.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 140.0, 150.2 ] ); // Go East between 1V8 and AVAUX pins $$terminal([ 140.0, 129.8 ] ); // Go South past the East edge of the 1V8 Finger $$terminal([ 127.4, 129.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 126.4, 128.8 ] ); // NO_MITER Go 45 deg SW $$terminal([ 106.3, 128.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 104.2, 126.7 ] ); // NO_MITER Go short SW diagonal $$terminal([ 104.2, 113.0 ] ); // NO_MITER Go Down $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom of FPGA $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go North up the East edge // of Hi Res fill and home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ECLK_3V3 // // Fill Layer: Signal_6 // // Location: ECLK_3V3 Fill Under the 25 MHz Ethernet Clock and Fanout // // Resolution: Midium // $$initial([ 47.5, 69.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 26.5, 69.0 ] ); // Go West across the Top $$terminal([ 26.5, 55.0 ] ); // Go Down the West edge $$terminal([ 47.5, 55.0 ] ); // Go East Across the Bottom $$terminal([ 47.5, 69.0 ] ); // Go Up the East edge and home $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_4", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: Main BULK_1V8 fill over a big section of the Hub PCB. // // Resolution: Medium // $$initial([ 250.0, 317.5 ], , @nosnap ); // Start in the NE corner $$terminal([ 24.5, 317.5 ] ); // Go West across the Top $$terminal([ 24.5, 210.0 ] ); // NO_MITER Go Down the West edge - stop // near the bottom of the IPMC connector. $$terminal([ 44.5, 190.0 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 44.5, 105.5 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 46.0, 104.0 ] ); // NO_MITER Go 45 deg to the SE to clear the MiniPODs $$terminal([ 46.0, 88.0 ] ); // Go the rest of the way Down to the bottom of the Phys Chips $$terminal([ 74.0, 88.0 ] ); // Go East Across the Bottom of the Phys Chips $$terminal([ 74.0, 101.0 ] ); // Go North to get just above the Clock chips $$terminal([ 90.0, 101.0 ] ); // Go East to pick of the West edge of FPGA $$terminal([ 90.0, 196.0 ] ); // NO_MITER Go North up the West edge of the FPGA // Note there is a separate high resolution // BULK_1V8 Fill Finger under the FPGA $$terminal([ 83.0, 203.0 ] ); // NO_MITER Jog at 45 deg to the NW to get a little West // to keep out of the DCDC2 Converter $$terminal([ 83.0, 222.0 ] ); // Finish going North $$terminal([ 130.0, 222.0 ] ); // Go East over to the West edge // of the S1 MegArray connector $$terminal([ 130.0, 283.0 ] ); // Go North up the West edge of the S1 MegArray. $$terminal([ 228.0, 283.0 ] ); // Go East Across the top of S1 and S2 MegArrays. $$terminal([ 228.0, 237.0 ] ); // Go Down the East edge of the S2 MegArray $$terminal([ 250.0, 237.0 ] ); // Go East Across the Bottom of the BULK_1V8 // DCDC Converter $$terminal([ 250.0, 317.5 ] ); // Go North up the East edge of the BULK_1V8 // DCDC Converter back to home. $$path( "DIELECTRIC_4", 0.0 ); // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: BULK_1V8 fill finger under the U1 FPGA // // Resolution: Hi // $$initial([ 89.0, 173.0 ], , @nosnap ); // NO_MITER Start in the NW corner $$terminal([ 89.0, 107.0 ] ); // NO_MITER Go South overlapping the main BULK_1V8 fill $$terminal([ 92.2, 107.0 ] ); // NO_MITER Go East a little to get into the Hi res area $$terminal([ 103.8, 118.6 ] ); // NO_MITER Go NE at 45 degrees $$terminal([ 103.8, 126.9 ] ); // NO_MITER Go North into the FPGA footprint $$terminal([ 106.1, 129.2 ] ); // NO_MITER Go North-East to get above MGT_AVAUX fill $$terminal([ 126.2, 129.2 ] ); // NO_MITER Go East above MGT_AVAUX fill $$terminal([ 127.2, 130.2 ] ); // NO_MITER Go 45 deg NE to get above 2 MGT_AVAUX pins $$terminal([ 139.0, 130.2 ] ); // Go East to to the East edge of the FPGA // to get all of the FPGA's 1V8 pins. $$terminal([ 139.0, 149.8 ] ); // Go North up the East edge of the FPGA // get just above the upper 1V8 pins $$terminal([ 125.2, 149.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 124.2, 150.8 ] ); // NO_MITER Go 45 deg NW to get above 2 MGT_AVAUX pins $$terminal([ 106.1, 150.8 ] ); // NO_MITER Go West across the top of the FPGA's 1V8 pins $$terminal([ 103.8, 153.1 ] ); // NO_MITER Go North-West between 1V8 and AVAUX pins $$terminal([ 103.8, 161.4 ] ); // NO_MITER Go North to get out of BGA field $$terminal([ 92.2, 173.0 ] ); // NO_MITER Go diagonally 45 deg NW $$terminal([ 89.0, 173.0 ] ); // NO_MITER Go West back to the Home corner. $$path( "DIELECTRIC_4", 0.0 ); // // Net: BULK_1V8 // // Fill Layer: Signal_6 // // Location: BULK_1V8 fill under the Config Flash Memory // // Resolution: Hi // $$initial([ 81.5, 149.5 ], , @nosnap ); // Start in the NE corner $$terminal([ 68.5, 149.5 ] ); // Go West across the Top $$terminal([ 68.5, 136.5 ] ); // Go Down the West edge $$terminal([ 81.5, 136.5 ] ); // Go East Across the Bottom $$terminal([ 81.5, 149.5 ] ); // Go Up the rest of the east edge and home $$path( "DIELECTRIC_4", 0.0 ); // // Net: MGT_AVAUX // // Fill Layer: Signal_6 // // Location: from the DCDC_4 Converter to the Eastern part of FPGA // // Resolution: Medium // $$initial([ 163.5, 205.0 ], , @nosnap ); // Start in the NE corner $$terminal([ 154.5, 205.0 ] ); // Go West across the Top of DCDC_4 $$terminal([ 154.5, 192.0 ] ); // NO_MITER Go Down the West edge of DCDC_4 $$terminal([ 151.2, 188.7 ] ); // NO_MITER Go Diagonally Down and West to FPGA NE corner $$terminal([ 135.8, 188.7 ] ); // NO_MITER Go West further West across Top of the FPGA // until just before C161 an AVAUX cap $$terminal([ 135.5, 189.0 ] ); // NO_MITER Go NW just 0.3 mm to get above C161 $$terminal([ 125.3, 189.0 ] ); // NO_MITER Finish going West further West // across Top of the FPGA $$terminal([ 121.3, 185.0 ] ); // NO_MITER Go 45 deg SW to escape converters $$terminal([ 99.0, 185.0 ] ); // Go far West to pick up some bypass capacitors $$terminal([ 99.0, 171.7 ] ); // NO_MITER Go Down the West edge of this AVAUX fill $$terminal([ 104.2, 166.5 ] ); // NO_MITER Go 45 deg SE to join Hi Res AVAUX fill $$terminal([ 141.5, 166.5 ] ); // NO_MITER Go East $$terminal([ 141.5, 113.5 ] ); // NO_MITER Go South $$terminal([ 104.2, 113.5 ] ); // NO_MITER Go West $$terminal([ 103.2, 112.5 ] ); // NO_MITER Go SW at 45 deg for just 1 mm $$terminal([ 99.0, 112.5 ] ); // NO_MITER Go West $$terminal([ 93.5, 107.0 ] ); // NO_MITER Go 45 deg SW to pick up the Tant Cap $$terminal([ 93.5, 98.0 ] ); // Go South $$terminal([ 156.0, 98.0 ] ); // Go East Across the Bottom of FPGA $$terminal([ 156.0, 145.0 ] ); // NO_MITER Go Up part way the east edge of FPGA $$terminal([ 163.0, 152.0 ] ); // NO_MITER Go Diagonally NE $$terminal([ 163.0, 182.0 ] ); // NO_MITER Go Up $$terminal([ 163.5, 182.5 ] ); // NO_MITER Go 45 deg NE for more Cu - close to FEX lines $$terminal([ 163.5, 205.0 ] ); // Go Up the rest of the east edge of DCDC_4 and home $$path( "DIELECTRIC_4", 0.0 ); // // Net: MGT_AVAUX // // Fill Layer: Signal_6 // // Location: MGT_AVAUX pins under the FPGA // // Resolution: HI // $$initial([ 142.0, 167.0 ], , @nosnap ); // NO_MITER Start in the NE corner $$terminal([ 104.2, 167.0 ] ); // NO_MITER Go West across the Top of FPGA $$terminal([ 104.2, 153.3 ] ); // NO_MITER Go Down the West edge just far enough // to pick up all of the AVAUX pins $$terminal([ 106.3, 151.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 124.4, 151.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 125.4, 150.2 ] ); // NO_MITER Go short SE diagonal $$terminal([ 140.0, 150.2 ] ); // Go East between 1V8 and AVAUX pins $$terminal([ 140.0, 129.8 ] ); // Go South past the East edge of the 1V8 Finger $$terminal([ 127.4, 129.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 126.4, 128.8 ] ); // NO_MITER Go 45 deg SW $$terminal([ 106.3, 128.8 ] ); // NO_MITER Go West between 1V8 and AVAUX pins $$terminal([ 104.2, 126.7 ] ); // NO_MITER Go short SW diagonal $$terminal([ 104.2, 113.0 ] ); // NO_MITER Go Down $$terminal([ 142.0, 113.0 ] ); // NO_MITER Go East Across the Bottom of FPGA $$terminal([ 142.0, 167.0 ] ); // NO_MITER Go North up the East edge // of Hi Res fill and home $$path( "DIELECTRIC_4", 0.0 ); // // Net: ECLK_3V3 // // Fill Layer: Signal_6 // // Location: ECLK_3V3 Fill Under the 25 MHz Ethernet Clock and Fanout // // Resolution: Midium // $$initial([ 47.5, 69.0 ], , @nosnap ); // Start in the NE corner and go CCW $$terminal([ 26.5, 69.0 ] ); // Go West across the Top $$terminal([ 26.5, 55.0 ] ); // Go Down the West edge $$terminal([ 47.5, 55.0 ] ); // Go East Across the Bottom $$terminal([ 47.5, 69.0 ] ); // Go Up the East edge and home $$path( "DIELECTRIC_4", 0.0 );